Abstract: Techniques are generally described related to a flash-based buffer management strategy. One example method to manage a buffer for a computer system may include maintaining a page-action list for monitoring a plurality of operations being executed on the computer system and utilizing a plurality of buffer pages of the buffer. An example page-action list may contain a hot-access queue for recently accessed buffer pages and a cold-access queue for less accessed buffer pages. The example method may also include, upon a determination that the buffer is full, identifying a victim buffer page from the plurality of buffer pages for eviction and evicting the victim buffer page from the buffer. The victim buffer page may be selected from the cold-access queue and based on a page weight, which is calculated based on a page state of the specific buffer page and a page hotness prediction for the specific buffer page might be accessed by an incoming operation.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction by delaying read access to data written during garbage collection. In one aspect, read access to a write unit to which data was written during garbage collection is delayed until a predefined subsequent operation has been completed.

Abstract: A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.

Abstract: Embodiments relate to methods, computer systems and computer program products for improving software performance by identifying and preloading data pages. Embodiments include executing an instruction that requests a data page from the one or more auxiliary storage devices. Based on determining that the instruction is present in the long-running instruction list, embodiments include examining one or more characteristics of a plurality of data pages that will be requested by the instruction. Based on determining that the plurality of data pages are located on a single auxiliary storage device and that the plurality of data pages can be efficiently retrieved by the single auxiliary storage device, embodiments include initiating a pre-load operation to move the plurality of data pages to the main memory.

Abstract: A system, method, and computer program product are provided for GPU demand paging. In operation, input data is addressed in terms of a virtual address space. Additionally, the input data is organized into one or more pages of data. Further, the input data organized as the one or more pages of data is at least temporarily stored in a physical cache. In addition, access to the input data in the physical cache is facilitated.

Abstract: A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.

Abstract: The described embodiments include a cache controller with a prediction mechanism in a cache. In the described embodiments, the prediction mechanism is configured to perform a lookup in each table in a hierarchy of lookup tables in parallel to determine if a memory request is predicted to be a hit in the cache, each table in the hierarchy comprising predictions whether memory requests to corresponding regions of a main memory will hit the cache, the corresponding regions of the main memory being smaller for tables lower in the hierarchy.

Abstract: A storage system which includes a cache memory needless of replacement of a power storage device, a cache memory with low power consumption, or a cache memory having no limitation on the number of writing operations is provided. An array controller for storing data externally input in any of a plurality of storage devices or a storage system including the array controller includes a processor which specifies at least one of the plurality of storage devices where the data is to be stored and a cache memory which stores the data and outputs the data to the at least one of the plurality of storage devices. The cache memory includes a storage circuit in which a transistor including an oxide semiconductor layer is used.

Abstract: Described are techniques for processing data operations. A read request for first data is received at a data storage system. It is determined whether the read request results in a cache hit whereby the first data is stored in a cache of the data storage system, or whether the read request otherwise results in a cache miss. If the read request results in a cache miss, processing is performed to determine determining whether to perform cacheless read processing or deferred caching processing to service the read request. Determining whether to perform cacheless read processing or deferred caching processing is performed in accordance with criteria including a measurement indicating a level of busyness of a back-end component used to retrieve from physical storage any portion of the first data not currently stored in the cache.

Abstract: A method, system and memory controller for implementing dynamic enabling and disabling of cache based upon workload in a computer system. Predefined sets of information are monitored while the cache is enabled to identify a change in workload, and selectively disabling the cache responsive to a first identified predefined workload. Monitoring predefined information to identify a second predefined workload while the cache is disabled, and selectively enabling the cache responsive to said identified second predefined workload.

Abstract: An apparatus and system are disclosed for reducing network traffic using a shared network response cache. A request filter module intercepts a network request to prevent the network request from entering a data network. The network request is sent by a client and is intended for one or more recipients on the data network. A cache check module checks a shared response cache for an entry matching the network request. A local response module sends a local response to the client in response to an entry in the shared response cache matching the network request. The local response satisfies the network request based on information from the matching entry in the shared response cache.

Abstract: A home node for selecting a source node using a cache coherency protocol, comprising a logic unit cluster coupled to a directory, wherein the logic unit cluster is configured to receive a request for data from a requesting cache node, determine a plurality of nodes that hold a copy of the requested data using the directory, select one of the nodes using one or more selection parameters as the source node, and transmit a message to the source node to determine whether the source node stores a copy of the requested data, wherein the source node forwards the requested data to the requesting cache node when the requested data is found within the source node, and wherein some of the nodes are marked as a Shared state corresponding to the cache coherency protocol.

Abstract: Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions. Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.

Abstract: A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Abstract: A data supply device includes an output unit, a fetch unit including a storage region for storing data and configured to supply data stored in the storage region to the output unit, and a prefetch unit configured to request, from an external device, data to be transmitted to the output unit. The fetch unit is configured to store data received from the external device in a reception region, which is a portion of the storage region, and, according to a request from the prefetch unit, to assign, as a transmission region, the reception region where data corresponding to the request is stored. The output unit is configured to output data stored in the region assigned as the transmission region by the fetch unit.

Abstract: A cache memory device includes a data array structure including a plurality of entries identified by indices and including, for each entry, data acquired by a fetch operation or prefetch operation and a reference count associated with the data. The reference count holds a value obtained by subtracting a count at which the entry has been referred to by the fetch operation, from a count at which the entry has been referred to by the prefetch operation. As for an entry created by the prefetch operation, a prefetch device inhibits replacement of the entry until the value of the reference count of the entry becomes 0.

Abstract: A method, computer program product, and computing system for copying a content directory associated with a cache system from a volatile memory system to a non-volatile memory system. A plurality of data requests concerning a plurality of data actions to be taken on an electro-mechanical storage device associated with the cache system are received on the cache system. The content directory on the volatile memory system is updated based, at least in part, upon the plurality of data requests. The plurality of data requests are stored on tracking queue included within the electro-mechanical storage device.

Abstract: A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether one or more discard scans are being performed or queued for the area of the cache. In response to determining that one or more discard scans are being performed or queued for the area of the cache, the controller avoids satisfying the request to perform the staging or the destaging operations or a read hit with respect to the area of the cache.

Abstract: A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. the control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data are stored in the non-volatile memory. If so, the requested read data are provided form the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. the volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.

Abstract: In accordance with an aspect of the present invention, a method and system for parallel computing is provided, that reduces the time necessary for the execution of program function. In order to reduce the time needed to execute aspects of a program, multiple program threads are executed simultaneously, while thread 0 of the program is also executed. These threads are executed simultaneously with the aid of at least one cache of the computing device on which the program is being run. Such a framework reduces wasted computing power and the time necessary to execute aspects of a program.

Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.

Abstract: The disclosed embodiments provide a system that uses broadcast-based TLB sharing to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an optical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the optical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the optical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.

Abstract: A system and method for clearing data from a cache in a storage device is disclosed. The method may include analyzing the cache for the least recently fragmented logical group, and evicting the entries from the least recently fragmented logical group. Or, the method may also include analyzing compaction history and selecting entries for eviction based on the analysis of the compaction history. The method may also include scheduling of different eviction mechanisms during various operations of the storage device. The system may include a cache storage, a main storage and a controller configured to evict entries associated with a least recently fragmented logical group, configured to evict entries based on analysis of compaction history, or configured to schedule different eviction mechanisms during various operations of the storage device.

Abstract: A buffer manager that manages blocks of memory amongst multiple levels of buffer pools. For instance, there may be a first level buffer pool for blocks in first level memory, and a second level buffer pool for blocks in second level memory. The first level buffer pool evicts blocks to the second level buffer pool if the blocks are not used above a first threshold level. The second level buffer pool evicts blocks to a yet lower level if they have not used above a second threshold level. The first level memory may be dynamic random access memory, whereas the second level memory may be storage class memory, such as a solid state disk. By using such a storage class memory, the working block set of the buffer manager may be increased without resorting to lower efficiency random block access from yet lower level memory such as disk.

Abstract: Data is securely stored on a storage device by encoding a data block into multiple encoded blocks, any number of which can be recombined to recover the data block. The encoded blocks are stored at known logical locations corresponding to physical locations on a storage device that change over time. When the data needs to be destroyed, at least one of the encoded blocks is overwritten with arbitrary data. In one aspect, the encoded blocks include at least one random block that is used to encode the data block. In another aspect, the known logical locations are stored in metadata.

Abstract: An information processing apparatus, a software update method, and an image processing apparatus capable of encrypting and decrypting information using values uniquely calculated from booted primary modules or booted backup modules with less effort are disclosed. The information processing apparatus includes primary modules and the same kinds of backup modules, and includes a value storage unit storing values calculated from the modules, an encryption information storage unit storing information unique to the modules, an information decryption unit decrypting the information unique to the modules using the values in the value storage unit, and an encryption information update unit, when the module is updated, encrypting the information unique to the modules based on a value calculated from the each kind of the primary modules or the backup modules after the update.

Abstract: A data protecting method for protecting a sub-directory and at least one pre-stored file in a rewritable non-volatile memory module is provided. The method includes receiving a write command from a host system and determining whether a write address indicated by the write command is an address storing a file description block of the sub-directory. The method also includes, when the write address is the address storing a file description block of the sub-directory, determining whether a portion of data streams corresponding to the write command is the same as a corresponding content recorded in the file description block of the sub-directory. The method further includes, when the portion of data streams corresponding to the write command is not the same as the corresponding content recorded in the file description block of the sub-directory, transmitting a write failure signal to the host system.

Abstract: Techniques for reducing overheads of primary storage transferring during a backup by transferring in an out-of-order manner are described herein. According to one embodiment, in response to a request at a primary storage for a backup of a plurality of data blocks, a transfer order of dirty data blocks is determined based on an access assessment of the dirty data blocks, wherein the dirty data blocks are data blocks of the plurality of data blocks that have been changed from a previous backup, and wherein the transfer order is different from a sequential logical order of the dirty data blocks provided by the primary storage. Then the dirty data blocks are transferred to a secondary storage in the determined order.

Abstract: While making it possible to register generation information used to generate a Web page for each topic by sending element information being components of the Web page by an email and add element information to the generation information by an email, it is made difficult for persons other than a person who registered the generation information to add the element information. When a receiver address included in a received email is a first address, an information registration apparatus registers generation information included in the email and transmits an email including a unique second address corresponding to the generation information to a sender of the received email, and when the receiver address is a second address and the receiver address is not the same as receiver addresses included in emails received before, the information registration apparatus adds element information to the generation information corresponding to the receiver address included in the currently received email.

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Abstract: Systems and methods for injecting interrupts in a virtualized computer system. An example method may comprise providing a data structure associating message destination addresses and virtual processor identifiers for a plurality of interrupt destination modes, receiving an interrupt message including a message destination address, looking up the message destination address in the data structure, and forwarding the interrupt message to a virtual processor associated by the data structure with the message destination address.

Abstract: A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.

Abstract: Systems, methods, apparatus, and techniques relating to a transmitter interface are disclosed. A soft-IP transmitter interface includes a Reed-Solomon encoder operating according to any one of multiple bus width and bandwidth parameter pairs, and a gearbox module that includes multiple gearboxes. The multiple gearboxes receive input data at a bus width and clock rate parameter pair specified by the soft-IP transmitter interface and convert the input data into output data according to a number of physical lanes and bandwidth parameter pair specified by a physical medium attachment (PMA) standard.

Abstract: A power/communication kit for use with a reader module where the code reader module includes a reader connector and a reader housing, the power/communication kit comprising a plurality of different power/communication modules wherein each module communicates via a different communication protocol and each includes a power source and a communication component suitable for communicating via an associated communication protocol, wherein, each of the modules is securable to the reader module in a similar fashion such that any one of the power/communication modules can be swapped for any other of the power/communication modules so that the reader can be used with different communication systems.

Abstract: A signal switching circuit allows a PCIe card access to additional data channels when installation of the PCIe cards on first and second PCIe connectors are detected. First and second PCIe connectors output a first detection signal when each of the first and second PCIe connectors receives a PCIe card. The first and second PCIe connectors output a second detection signal when each of the first and second PCIe connectors does not receive a PCIe card. A first multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the first multiplexer, to transmit PCIe signals to the first or second PCIe connector. A second multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the second multiplexer, to transmit PCIe signals to the first or second PCIe connectors.

Abstract: A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.

Abstract: In a method in a portable data carrier for executing an additional functionality in the data carrier, whereby the data carrier comprises a memory and whereby the additional functionality is called up by means of the one access of a conventional read command ordered from outside the data carrier to the memory of the data carrier, the additional functionality is further specified by a respective further access of at least one further conventional read command to the memory of the data carrier.

Abstract: A communication system where first and second devices communicate concurrently and bidirectionally over a single wire and a ground. The second device can be a computing device having a powered component which requires a certain power output, for instance, and the first device may be a power supply unit. The second device provides a signal on a control line (the single wire) which is characterized by a frequency, pulse width, duty cycle and/or an amplitude which is associated with a message from the second device. The first device recognizes the message in the signal and invokes a corresponding function, such as by enabling a corresponding power supply. The power supply provides power to the second device via a separate power line. Further, the first device modifies the signal, without adding power, to provide a message from the first device, concurrent with the message from the second device.

Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Abstract: A messaging system and method with dead man switching providing for hierarchical delivery of messages based on selected message hierarchy levels with controlled delivery/response timing is disclosed. The system and method incorporates a messaging host that communicates with a messaging source client that creates and prioritizes a message and targets address(es) for the message. This message is then transmitted to the target address(es) using a hierarchical transmission thread having set limits on response times for each address within the thread. Reception of the message by each target(s) produces visual and/or auditory notification at the target(s). Messages are automatically forwarded to remaining target(s) within the thread upon expiration of a timer should the target(s) fail to respond to the message within a predetermined time. Failure of the target(s) to respond to the message(s) is reported bi-directionally along the thread and forwarded to remaining target(s) in the thread.

Abstract: According to the present disclosure, there is provided a method of transferring content between a plurality of devices, and devices using the method. The method may include acquiring content at a first device, acquiring tag information associated with the content, adding the tag information to the content, the tag information including identification of a second device as a destination for the content, determining a cloud storage device on a cloud storage network associated with the second device based on the tag information, and transmitting the content to the cloud storage device associated with the second device.

Abstract: A method begins by generating list range requests. A list range request includes a payload section and a protocol header section. The payload section includes a start slice name field regarding a start slice name of a slice name range; an end slice name field regarding an end slice name of the slice name range; and a maximum response count field regarding a maximum slice name response count. The protocol header includes a payload length field that represents a length of the payload section and an operation code field to indicate the list range request operation. The list range request includes a request to provide a list of slices names corresponding to stored encoded data slices associated with slice names within the slice name range. The method continues by sending the range requests to storage units of the DSN.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: Machine-implemented methods, systems, processing devices and machine-readable media are provided for simulating a mill reline, which involve collecting mill relining data and processing the relining data as simulation parameters using a mill relining model. The relining data generally include variables treated as discrete time/frequency distributions. Simulated events for the mill reline may be generated based on the relining data. Additional relining data relating to a specific existing site may be included as simulation parameters. The simulation may be used in determining an optimal work flow for carrying out the mill reline at a specific existing site, e.g., where time to carry out the mill reline is minimized. The simulation may also be employed for benchmarking. The additional relining data may be provided in video format, and analysis of the video format data may be undertaken, e.g.

Abstract: Techniques are disclosed for producing a collaborative recording of an audio event. An online server or service identifies participating mobile devices with recording capabilities that are available for recording at least a portion of the audio event. The online server or service determines the locations of the potential participating mobile devices, and identifies ranges of frequencies to be recorded by each of the participating mobile devices. The individual recordings are then compiled into a final collaborative recording.

Abstract: The invention relates to a vehicle computer system. The vehicle computer system gathers data from a safety sensor to determine whether the proper safety conditions are present for the vehicle operator to interact with the vehicle computer system. A safety controller receives safety condition data gathered from the safety sensor and instructs the display manager to disable the display of information to the vehicle operator during unsafe operating conditions. The vehicle computer system advantageously employs a transparent display screen to provide greater field of vision of the vehicle operator than could be provided by a traditional display screen.

Abstract: Embodiments of the invention include an apparatus for performing Galois multiplication using an enhanced Galois table. Galois multiplication may include converting a first and second multiplicand to exponential forms using a Galois table, adding the exponential forms of the first and second multiplicands, and converting the added exponential forms of the first and second multiplicands to a decimal equivalent binary form using the Galois table to decimal equivalent binary result of the Galois multiplication.

Abstract: Polychoric correlations between two discrete random variables and polyserial correlations between a discrete random variable and a continuous random variable may be determined by using a normal-to-anything (NORTA) method and a stochastic root finding algorithm.

Abstract: Values of a metric are provided at irregular intervals. A forgetting factor is calculated based on a difference between the intervals, and a statistical parameter is computed using the forgetting factor that causes different weights to be placed on the corresponding values of the metric, where the statistical parameter is part of an adaptive baseline.

Abstract: A method for associating at least a link to an information resource with a multimedia content element. The method comprises identifying at least one multimedia content element in a web-page, wherein a uniform resource locator (URL) of the web-page is received from any one of a user device and a web server hosting the web-page; generating a signature for at least a portion of the at least one identified multimedia content element; determining at least a link to the at least a portion of the content respective of the generated signature; and providing the web-page with the at least a link respective of the signature of the at least a portion of the at least one multimedia content element to the user device.