Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11_1 and a second memory area 11_2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm_ are disposed in a boundary area 18 between the first and second memory areas 11_1 and 11_2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor apparatus includes a first output control unit and a second output control unit. The first output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert input signals and output the non-inverted input signals to a signal transmission line as transmission signal, and the inversion pipes invert input signals and output the inverted input signals to the signal transmission line as the transmission signals. The second output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert the transmission signals and output the non-inverted transmission signals, and the inversion pipes invert the transmission signals and output the inverted transmission signals.

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract: Techniques and circuits for storing and retrieving data using spin-torque magnetic memory cells as anti-fuses are presented. Circuits are included to allow higher-magnitude voltages and currents to be applied to magnetic memory cells to intentionally break down the dielectric layer included the magnetic tunnel junction. Magnetic memory cells having a normal-resistance magnetic tunnel junction with an intact dielectric layer are used to store a first data state, and magnetic memory cells having a magnetic tunnel junction with a broken-down dielectric layer are used to store a second data state. Data can be stored in such a manner during wafer probe and then later read out directly or copied into other magnetic or non-magnetic memory on the device for use in operations after the device is included in a system.

Abstract: A clock signal processor includes a duty cycle corrector, a switch point calculator, and a multiplexer. The duty cycle corrector generates a second clock signal by modifying a duty cycle of a first clock signal. The switch point calculator activates a switch signal at an end of a latency period in which a read command is provided to a non-volatile memory device and an invalid data is read from the non-volatile memory device. The multiplexer outputs one of the first and second clock signals as a third clock signal based on the switch signal.

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Abstract: A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

Abstract: A static random access memory (SRAM) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage. The first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.

Abstract: An integrated circuit includes a plurality of first memory cells and a plurality of second memory cells. Each cell of the plurality of first memory cells includes a first inverter, a second inverter, a first pass-gate (PG) transistor and a second PG transistor. Each inverter of the first and second inverters includes a P-type single FinFET transistor and an N-type single FinFET transistor. The first PG transistor and the second PG transistor each are an N-type single FinFET transistor. Each cell of the plurality of second memory cells includes a third inverter, a fourth inverter, a third PG transistor and a fourth PG transistor. Each inverter of the third and fourth inverters includes a P-type single FinFET transistor and an N-type transistor. Each transistor of the third and fourth PG transistors include at least two FinFET transistors electrically coupled in a parallel configuration.

Abstract: A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.

Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.

Abstract: Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be programmed to transition among more than two states representing multiple bits of information.

Abstract: A memory device for thermoelectric heat confinement and method for producing same. The memory device includes a plurality of phase-change memory cells, wherein each of the phase-change memory cells has a first electrode, a second electrode and a phase-change material. The first electrode and the phase-change material are arranged such that a surface normal of a dominating interface for a current flow between the first electrode and the phase-change material points on one side to the phase-change material of the phase-change memory cell and on an opposite side to a phase-change material of a neighboring phase-change memory cell. A method for producing a memory device for thermoelectric heat confinement is also provided.

Abstract: The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell.

Abstract: A nonvolatile memory device is writable to a high resistance state and a low resistance state. The nonvolatile memory device may be heated to at least a threshold temperature, based on application of an alternating current (AC) signal, and may be written based on application of a voltage bias.

Abstract: A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F2 and 36F2.

Abstract: Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A. plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.

Abstract: The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a substrate, first to three wells and first to three transistors. The first to three wells are disposed in the substrate, and the first to three transistors are respectively forming on the first to three wells. The first to third transistors are coupled in series. Wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal. Moreover, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.

Abstract: A nonvolatile memory includes a memory array. The memory array is connected to m word lines and (2+n) bit line pairs. These bit line pairs include an erase bit line pair, a program bit line pair and n data bit line pairs. Each word line is connected with (2+n) differential cells of a corresponding row. The (2+n) differential cells include an erase flag differential cell, a program flag differential cell and n data differential cells. The erase flag differential cell is connected with the erase bit line pair. The program flag differential cell is connected with the program line pair. The n data differential cells are connected with the data line pairs. The n data differential cells are determined as erased cells or programmed cells according to setting conditions of the erase flag differential cell and the program flag differential cell.

Abstract: An electrically erasable programmable read-only memory (EEPROM) device includes a plurality of data areas in the EEPROM associated with a corresponding plurality of memory addresses, respectively, a data status indicator associated with each of the plurality of data areas. The data status indicator is configured to indicate that a data area is in an erase state, an uncertain state, or a valid state. The EEPROM device also includes a controller. A first data area and a second data area are configured to be a backup storage area for each other. In an erase and program cycle, at least one of the first or second memory areas is in a valid state throughout the erase and program cycle. Further, in an erase and program cycle, an erase operation is performed in one of the first or second memory areas, and a program operation is performed in the other data areas.

Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.

Abstract: The semiconductor device may include a memory block including a memory string electrically coupled between a bit line and a common source line, the memory string including source select transistors and memory cells configured to operate in response to operating voltages applied to select lines and word lines coupled to the memory cells and the source select transistors. The semiconductor device may include an operation circuit configured to apply a source voltage to the common source line for an erase operation, and to control floating states of the select lines and the word lines. The operation circuit may be configured to set the select lines to a floating state after the source voltage starts to increase from a precharge level to an erase level.

Abstract: A method controlling the execution of a reliability verification operation in a storage device including a nonvolatile memory device includes; determining whether a read count for a designated unit within the nonvolatile memory device exceeds a count value limit, and upon determining that the read count exceeds the count value limit, executing the reliability verification operation directed to the designated unit, wherein the count value limit is based on at least one of read count information, page bitmap information and environment information stored in the storage device.

Abstract: An operating method of a non-volatile memory device may include erasing memory cells included in a plurality of strings of a memory block, wherein the memory cells are coupled between a bit line and a common source line. The operating method of the non-volatile memory device may include performing an erase verify operation on selected memory cells having a low erase speed, among the memory cells. The operating method of the non-volatile memory device may include repeating the erasing of the memory cells and the performing of the erase verify operation until the erase verify operation passes.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.

Abstract: A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.

Abstract: A method for measuring a temperature of magnetic junction switchable using spin transfer. The magnetic junction includes at least one magnetic layer. The method includes measuring a temperature variation of at least one magnetic characteristic for the magnetic layer(s) versus temperature. The method also includes measuring a bias variation in the magnetic characteristic versus an electrical bias for the magnetic junction. This measurement is performed such that spin transfer torque-induced variation(s) in the magnetic characteristic(s) are accounted for. The temperature versus the electrical bias for the magnetic junction is determined based on the temperature variation and the bias variation.

Abstract: A defective address information encoding method for a memory array is provided. A page of the memory array is divided into plural segments. Each segment contains 2m bits. The defective address information encoding method includes the following steps. Firstly, positions of N1 fail bits in a first segment of the plural segments are acquired. Then, an (N1+1)-bit first segment start code is generated. Then, N1 m-bit defective codes are generated. The N1 m-bit defective codes follow the first segment start code to indicate the positions of the N1 fail bits in the first segment, wherein N1 is zero or a positive integer, and m is a positive integer.

Abstract: A repair circuit includes a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal, a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal when the partial input addresses and the partial repair addresses correspond to each other, and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal.

Abstract: An object of the present invention is to efficiently improve uniformity of energy lines to be irradiated.

Abstract: The present invention relates to a novel material made of uranium, gadolinium and oxygen, having a crystalline phase having cubic crystallographic structure, having an atomic ratio Gd/[Gd+U] of 0.6 to 0.93, the uranium being present in an oxidation state of +IV and/or +V. The invention further relates to the use of such a material as a consumable neutron poison of a fuel element.

Abstract: An Ag alloy film used for a reflecting electrode or an interconnection electrode, the Ag alloy film exhibiting low electrical resistivity and high reflectivity and having exceptional oxidation resistance under cleaning treatments such as an O2 plasma treatment or UV irradiation, wherein the Ag alloy film contains either In in an amount of larger than 2.0 atomic % to 2.7 atomic % or smaller; or Zn in an amount of larger than 2.0 atomic % to 3.5 atomic % or smaller; or both. The Ag alloy film may further contain Bi in an amount of 0.01 to 1.0 atomic %.

Abstract: A copper alloy sheet for terminal and connector materials contains 4.5 mass % to 12.0 mass % of Zn, 0.40 mass % to 0.9 mass % of Sn, 0.01 mass % to 0.08 mass % of P, and 0.20 mass % to 0.85 mass % of Ni with a remainder being Cu and inevitable impurities, a relationship of 11?[Zn]+7.5×[Sn]+16×[P]+3.5×[Ni]?19 is satisfied, a relationship of 7?[Ni]/[P]?40 is satisfied in a case in which the content of Ni is in a range of 0.35 mass % to 0.85 mass %, an average crystal grain diameter is in a range of 2.0 ?m to 8.0 ?m, an average particle diameter of circular or elliptical precipitates is in a range of 4.0 nm to 25.0 nm or a proportion of the number of precipitates having a particle diameter in a range of 4.0 nm to 25.0 nm in the precipitates is 70% or more, an electric conductivity is 29% IACS or more, a percentage of stress relaxation is 30% or less at 150° C. for 1000 hours as stress relaxation resistance, bending workability is R/t?0.

Abstract: The present invention discloses a conductive plasma-resistant member including an yttrium oxide. The plasma-resistant member of the present invention includes an yttrium compound which includes a matrix phase consisting of yttrium oxides, and a conductive dispersed phase. According to the present invention, the present invention provides a semiconductor-grade yttria composite which may be used as a plasma-resistant member requiring conductivity like a focus ring.

Abstract: There is provided a conductive resin composition including epoxy resin, copper powder particles, and non-nitrogen-based hardeners.

Abstract: The object of the present invention is to provide a binder pitch increased in carbonization yield (fixed carbon content) without varying the softening point thereof. A binder pitch has a carbon-to-hydrogen molar ratio of 1.90 or more, a quinoline insoluble content of 12.0% to 30.0% by mass, a free carbon content of 12.0% to 30.0% by mass, a mesophase content of 0.50% by mass or less, a toluene insoluble content of 24.0% by mass or more, and a fixed carbon content of 58.0% by mass or more.

Abstract: Porous polymer nanocomposites with controllable distribution/dispersion of components are provided. These nanocomposites are useful for various applications, such as flexible 3D electrodes for batteries, flexible sensors and conductors and the like. Also provided are emulsion compositions and methods for preparing the porous polymer nanocomposites.

Abstract: A method for improving the electric field distribution in a high voltage direct current cable includes providing a cable that includes a conductor, a protective jacket, a shield layer disposed inside the jacket, and an insulation layer disposed inside the shield layer, surrounding the conductor. The insulation layer includes ethylene-propylene rubber, talc, and montmorillonite.

Abstract: Disclosed are methods of lowering application viscosities of or of reducing or eliminating monomer content in electrical impregnating materials comprising or consisting of an emulsion of an unsaturated polyester or a mixture of unsaturated polyesters, water, at least one radical polymerisation initiator or radical polymerisation initiator/promoter mixture, at least one surfactant having an HLB-value of greater than 15, optionally at least one reactive diluent, and optionally further additives, a process for preparing zero or low VOC electrical impregnation materials, a method of impregnating electrical or electromechanical devices and a method of increasing the stability of aqueous emulsions of unsaturated polyesters.

Abstract: A highly-flexible electric wire includes: a conductor; and an insulator layer covering the conductor and further includes a liquid lubricant interposed between the conductor and insulator layer. The lubricant contains at least one selected from the group consisting of polyethylene glycol, polypropylene glycol, and fluorine lubricants. Such a configuration enables the conductor and insulator layer to slide smoothly on each other, therefore increasing the flexibility.

Abstract: A method of manufacturing a touch device is provided. The method includes: providing a transparent substrate, the transparent substrate being curved and including a touch surface and a connecting surface; coating a conductive material layer on the connecting surface; coating a photo-resist material layer on the conductive material layer; providing a mask, the mask being curved and made of transparent material; coating a pattern of circuit on the mask, the pattern of circuit made of opaque material; placing the mask with the pattern of circuit on the photo-resist material layer, the pattern of circuit touching the photo-resist material layer and totally covered by the photo-resist material layer; photo-etching the conductive material layer to form a conductive circuit layer on the connecting surface; and connecting a drive circuit to the conductive circuit layer to obtain the touch device.

Abstract: A method of manufacturing a surface mount device includes forming a plaque from a material, forming a plurality of conductive protrusions on a top surface and a bottom surface of the plaque, and applying a liquid encapsulant over at least a portion of the top surface and at least a portion of the bottom surface of the plaque. The liquid encapsulant is cured and when cured encapsulant has an oxygen permeability of less than about 0.4 cm3·mm/m2·atm·day. The assembly is cut to provide a plurality of components. After cutting, the top surface of each component includes at least one conductive protrusion, the bottom surface of each component includes at least one conductive protrusion, the top surface and the bottom surface of each component include the cured encapsulant, and a core of each component includes the material.

Abstract: There is provided an iron oxide magnetic nanoparticle powder having a ferromagnetic property even if the particles have an average particle size of 15 nm or less, preferably 10 nm or less, and a method of producing the same, an iron oxide magnetic nanoparticle thin film containing the iron oxide magnetic nanoparticle powder and a method of producing the same, wherein the iron oxide magnetic nanoparticles having an ?-Fe2O3 single phase, having the average particle size of 15 nm or less, and further 10 nm or less, are generated by using ?-FeO(OH) (iron oxide hydroxide) nanoparticles as a starting material, and coating the (iron oxide hydroxide) nanoparticles with silicon oxide, and applying heat treatment thereto under an atmospheric air, and further the iron oxide magnetic nanoparticle thin film is obtained by using the iron oxide magnetic nanoparticles.

Abstract: Disclosed is a magnet plate assembly that includes a plurality of magnetic bodies, each magnetic body having a first surface formed to correspond to a flat surface of a substrate and to contact the flat surface of the substrate and a second surface formed in a different direction from that of the first surface, and a support frame which supports the plurality of magnetic bodies and has a plurality of grooves in which the plurality of magnetic bodies are respectively seated.

Abstract: Electromagnetic actuator components include a magnetic core, a conductor assembled with the core and defining a winding completing a number of turns, and a movable component that may be displaced by a magnetic field. The conductor is fabricated from a composite material including carbon nanotubes having an improved conductivity. The conductor has a cross section defined by an effective diameter. The conductor is fabricated to have performance parameters that are selected in view of a function of a ratio of conductivity and/or a function of a ratio of effective diameter of the composite conductor material relative to a reference conductor material as conventionally used in an electromagnetic actuator fabrication.

Abstract: There is provided a chip electronic component including: a magnetic body including an insulating substrate and having a size thereof in a length direction thereof larger than that in a width direction thereof; and an internal coil part provided on at least one surface of the insulating substrate, wherein a width of the internal coil part measured in the length direction of the magnetic body on the basis of the center of the magnetic body in the width direction thereof is larger than a width of the internal coil part measured in the width direction of the magnetic body on the basis of the center of the magnetic body in the length direction thereof.

Abstract: There are provided a chip electronic component and aboard having the same. The chip electronic component includes: a substrate; a first internal coil part disposed on one surface of the substrate; a second internal coil part disposed on the other surface of the substrate opposing one surface thereof; a via penetrating through the substrate to connect the first and second internal coil parts to each other; and first and second via pads disposed on one surface and the other surface of the substrate, respectively, to cover the via, wherein the first and second via pads are extended in a direction toward portions of the first and second internal coil parts adjacent thereto.

Abstract: An electronic component includes a body formed of an insulator, a coil positioned in the body and including first and second coil conductors, an outer electrode including a first bottom-surface electrode and a first substantially columnar electrode (first electrode) and connected to the second conductor, and an outer electrode including a second bottom-surface electrode and a second substantially columnar electrode (second electrode) and connected to the first conductor. The second conductor is positioned between the first conductor and a bottom surface of the body. The second electrode is positioned to oppose the first electrode across the coil's central axis when viewed from the z-axis direction. An outermost peripheral portion of the first conductor is superposed with the first electrode when viewed from the z-axis direction. A smallest distance between the first conductor and a first side surface is smaller than that between the second conductor and a second side surface.