Abstract: A computer-implemented method for securely storing backup data while facilitating fast failovers may include 1) identifying, at a primary site, a virtual disk file that includes a backup image, 2) modifying a boot sector within the virtual disk file to add a boot loader that supports reading disks encrypted with whole disk encryption, 3) encrypting the backup image within the virtual disk file, except for at least one decryption area, with whole disk encryption, and 4) storing the virtual disk file at a secondary site after encrypting the backup image within the virtual disk file. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: In one example of a time-based checkpoint restore method, a backup of data is commenced. Prior to completion of the backup, a failure is experienced such that only a portion of the data is backed up. A first partial saveset is created, and time and path checkpoints are identified. The backup is then retried, using the time and path checkpoints. Data backed up prior to failure is incrementally backed up, and the remaining data not already backed up is fully backed up. A second partial saveset of these backups is created and combined with the first partial saveset to create a resultant saveset that can then be used to create a full backup image that includes a full backup of the data.

Abstract: A computer-implemented method for restoring application data may include (1) receiving a request to restore resource data for a resource to a selected state, (2) identifying a plurality of backup datasets, each backup dataset within the plurality of backup datasets including at least a portion of backed up data for the resource, (3) determining an order in which to restore the plurality of backup datasets in order to restore the resource data to the selected state, and (4) restoring the resource data for the resource to the selected state by restoring the plurality of backup datasets in the order as determined. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A storage control device includes a processor. The processor is configured to request a plurality of disk devices storing data therein to notify the processor of degradation information on degradation of data stored in the respective disk devices. The processor is configured to instruct, based on first information among notified degradation information, the plurality of disk devices to rewrite data. The first information serves as a trigger of rewriting data. The first information is notified by at least one of the plurality of disk devices.

Abstract: Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.

Abstract: A method for recovering system status consistently to a designed recovering time point in a distributed database, wherein the distributed database comprises a primary server and multiple region servers, comprising: when the region servers detect a change of system status, analyzing an event for the change to generate an event log and storing the event log to the database; after a preset condition, the region servers generate a snapshot respectively; when the primary server receives the instruction to recover the system status to a designed time point, indicates the region servers to implement: reading the event log and snapshots stored in region servers; finding the snapshot closest to the designed time point; finding the event log and snapshot corresponding to an time interval between the time recorded in the snapshot and the designed time point to recover the system status to the designed time point.

Abstract: The present disclosure describes methods, systems, and computer program products for circumventing parallel processing load imbalance. One computer-implemented method includes generating a library function for a plurality of parallel-processing nodes, receiving timing statistics from each of the plurality of parallel-processing nodes, the timing statistics generated by executing the library function on each parallel-processing node, determining that a faulty parallel-processing node exists, signaling a simulator to checkpoint and stop a simulation executing on the parallel processing nodes, and removing the faulty parallel-processing node from parallel processing nodes available to execute the simulation.

Abstract: A recovery consumer framework provides for execution of recovery actions by one or more recovery consumers to enable efficient recovery of information (e.g., data and metadata) in a storage system after a failure event (e.g., a power failure). The recovery consumer framework permits concurrent execution of recovery actions so as to reduce recovery time (i.e., duration) for the storage system. The recovery consumer framework may coordinate (e.g., notify) the recovery consumers to serialize execution of the recovery actions by those recovery consumers having a dependency while allowing concurrent execution between recovery consumers having no dependency relationship. Each recovery consumer may register with the framework to associate a dependency on one or more of the other recovery consumers. The dependency association may be represented as a directed graph where each vertex of the graph represents a recovery consumer and each directed edge of the graph represents a dependency. The framework may traverse (i.e.

Abstract: Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.

Abstract: Disclosed herein are a server and an inspecting method thereof. The server comprises a baseboard management controller (BMC), a non-volatile memory coupled with the baseboard management controller, and a basic input/output system. After the server is powered on, the basic input/output system starts running, performs power-on self-test for the server to generate current hardware configuration data. The BMC then determines whether preset hardware configuration data, stored beforehand in the non-volatile memory, and the current one agree. If the preset and the current hardware configuration data have one or more mismatches, the BMC records the mismatch or mismatches in an event log.

Abstract: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyzes the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.

Abstract: A method of ganging memories in an Integrated Circuit (IC) design identifies a first subset of a first set of the memories that have word counts in a common power of two range, a common count of memory blocks, and a common column multiplexing factor, a first memory that does not have a word count in the common power of two range, a second memory of the first set of memories that does not have at least one of a common count of memory blocks and a common column multiplexing factor, and then inserts a common scrambling unit, a common chip select unit, a common comparator, a common repairing unit, a first scrambling unit, a second scrambling unit, a first comparator, and a first repairing unit into the IC design.

Abstract: A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.

Abstract: A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.

Abstract: A redundant computing architecture includes a first control unit, a second control unit, and a switch. The first control unit is configured to provide a first control signal in response to a sensory input and is further configured to provide a health status indicator that is indicative of a fault condition within the first control unit. Additionally, the second control unit is configured to provide a second control signal in response to the sensory input. Each of the first and second control signals is respectively operative to control an actuator. The switch is configured to: receive the health status indicator, the first control signal, and second control signal; provide the first control signal to the actuator if this health status indicator does not indicate a fault: and provide the second control signal to the actuator if this health status indicator does indicate a fault.

Abstract: Methods and apparatus for generating at risk probabilities for a pre-integrated cloud computing system. In one embodiment, a system determines a revised overall risk index after at least two component failures in at least two of the compute domain, storage domain, and storage paths to assist a user in selecting a first one of the at least two component failures to fix first.

Abstract: The presently disclosed subject matter includes a device, system and method for monitoring activity at a computerized device, the device running one or more processes, at least one of the processes executing one or more system events being part of an activity. An activity of interest can be identified if system events related to the activity of interest are identified. An activity is monitored at the device using API queries to obtain descriptive information of the at least one respective system event executed as part of the activity. Using non-intrusive monitoring methods which are based on API queries enables to reduce the potential of interference of the monitoring with applications running on the monitored device.

Abstract: Methods and arrangements for enhancing a ticket relative to user interaction with a system. An information technology ticket related to user interaction with an information technology system is received, and a system trace is activated, wherein additional input related to the user interaction with the information technology system is accepted. Information derived from the trace of the information technology system is associated with the information technology ticket. Other variants and embodiments are broadly contemplated herein.

Abstract: A computer-implemented method for collaborative caching of files during a collaboration session includes receiving a request from a first electronic device for a first file. The method determines whether the first file is stored in one or more caches, wherein the one or more caches are associated with one or more electronic devices. Responsive to determining the first file is stored in a cache of a second electronic device, the method determines whether the first file stored in the cache of the second electronic device meets a set of guidelines. Responsive to determining the first file stored in the cache of the second electronic device meets the set of guidelines, the method sends the first file from the cache of the second electronic device via an internal network to the first electronic device.

Abstract: A method includes inputting an application program to be tested to a data processing system; linking the application program to a software library; performing, in cooperation with the software library, a static analysis of a user interface of the application program, without executing the application program, to generate a set of static analysis results; performing, in cooperation with the software library, a dynamic analysis of the user interface of the application program while executing the application program to generate a set of dynamic analysis results and, based on the set of static analysis results and the set of dynamic analysis results, a step of determining if the user interface of the application program violates one or more user interface policy rules. Also disclosed is a computer program product that implements the method and a system configured to execute the computer program product in accordance with the method.

Abstract: A first stream operator in a stream computing application receives and processes a first stream of tuples. The processing at the first stream operator is paused in response to receiving a first one of the tuples in the first stream that triggers a breakpoint in the first stream operator. A determination of whether a condition to release the breakpoint is met is made, and the breakpoint is released in response to determining that the condition is met. The condition to release the breakpoint may be that a count of tuples of the first stream is outside of a threshold. A second stream of tuples may be received for processing at a second stream operator. The condition to release the breakpoint may be that a count of tuples of the second stream is outside of a threshold.

Abstract: In response to identification of an error in operation of a system, a debugging module determines where to set a debug entry point for a program subset debug session. An initial file state is captured for at least one file accessed by the system in response to initiation of a subsequent execution of the system. Prior to detection of execution of the system at the debug entry point, any file inputs and file outputs (I/Os) detected during the subsequent execution of the system are queued. Debug entry point metadata, including the captured initial at least one file state, the queued file I/Os, and an image of all instantiated objects at the debug entry point, is stored in response to detection of execution of the system at the debug entry point.

Abstract: Embodiments of the present invention provide a system and method for a dynamic tracing framework for debugging in a virtualized environment. Embodiment of the present invention can include selecting a home node and a set of remote nodes to which apply a set of probes. Data collection is performed by a tracing agent of each node and the collection of data is shared across multiple software systems.

Abstract: A method, apparatus and computer program for recording the core data of a computer process, the computer process comprising trace points and core data is provided for each such trace point. A first set of core data comprising an image of a memory for the computer process is stored in response to a first set of trace data being produced for the computer process for a first trace point. A second set of core data is stored in response to a second set of trace data being produced for the computer process for a second trace, where the second set of core data comprises a record of any change in current memory contents for the computer process with respect to the first set of core data.

Abstract: This disclosure relates to computer test systems and, more particularly, to automatically configuring computer test systems. A method, computer program product, and system receives a list of one or more software patches installed on an in-field computer system, the list including a version of each of the one or more software patches. Source code, managed by a source code revision tool, corresponding to the version of each of the one or more software patches, is identified. A compiling and installation system compiles one or more newly compiled software patches from the source code managed by the source code revision tool for each of the software patches installed on the in-field computer system. The compiling and installation system automatically installs the one or more newly compiled software patches on a test computer system to replicate the in-field computer system.

Abstract: A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit assumption is information that is not expressly stated in the documentation, but which would be useful in assisting an application developer in building an application. The framework also describes a systematic approach for identifying one or more vulnerability patterns based on the identified implicit assumptions. An application developer may run a test on an application that is being developed to ensure that it does not have any deficiency which matches a vulnerability pattern.

Abstract: Disclosed are various embodiments for a state monitoring application. A state monitoring application initiates the execution of test operations on a client device. States of the client device are monitored to determine when the client device is at risk of entering an unresponsive state. When the client device is at risk, the state monitoring application initiates the execution of remedy operations to prevent the client device from becoming unresponsive.

Abstract: According to some embodiments, a method and apparatus are provided to receive browser automation code to automatically test a software application executed in a web browser and receive a first parameter to indicate a first type of web browser and a second parameter to indicate a second type of web browser. The browser automation code is executed in the first type of web browser and the browser automation code is executed in the second type of web browser.

Abstract: A method includes determining a size of a recommended spare memory space of each of one or more storage nodes based on a state of the storage nodes, and adjusting a spare memory space of each of the storage nodes based on the size of the recommended spare memory space.

Abstract: Disclosed are systems, computer-readable mediums, and methods for reading a sequence number from regions of a solid state storage device. A latest region is determined based upon the sequence numbers and a checkpoint file is read within the latest region. A request for a block of data of a first branch is received. A first block of pointers associated with the first branch from the checkpoint file is read. A first pointer from the first block of pointers and a second block of pointers pointed to by the first pointer are read. A second pointer from the second block of pointers and a third block of pointers pointed to by the second pointer are read. A third pointer from the third block of pointers and data pointed to by the third pointer are read. The block of data of the first branch is determined based upon the read data. The block of data is returned.

Abstract: A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order.

Abstract: The invention relates to a method for masking the end-of-life transition of an electronic microprocessor device comprising a reprogrammable non-volatile memory containing an end-of-life state variable (FdVE). The value of the variable (FdVE) is loaded (A) into random access memory. Prior to the execution of any current command (COM), the value of the variable (FdVR) in random access memory is checked (B). The end-of-life transition is executed (C) in the event of an empty value. Otherwise, the initialization or the execution of the command (COM) is continued (D). Upon detection (E) of an intrusive attack, the end-of-life state variable (FdVR) is written (F) in the single random-access memory, and the end-of-life state variable (FdVE) is deleted (G) from the non-volatile memory in a delayed manner. The invention is suitable for all electronic devices, microprocessor cards or the like.

Abstract: A method of managing a non-volatile memory module, the method may include: receiving data sectors during a set of at least one write transactions; selecting, out of the currently buffered portions, to-be-merged memory space portions and to-be-cleaned memory space portions; merging, for each to-be-merged memory space portion and before the buffer becomes full, data sectors that belong to the to-be-merged memory space portion into a sequential portion of the non-volatile memory module, wherein the sequential portion differs from the buffer; and copying, for each to-be-cleaned memory space and before the buffer becomes full, data sectors that belong to the to-be-cleaned memory space portion into a buffer block of the buffer.

Abstract: A method, computer program product, and computing system for monitoring an application being executed on a host to generate a prediction concerning a quantity of data that may be needed in the future. The quantity of data is requested from a data array coupled to the host. The quantity of data is received from the data array. The quantity of data is stored within a frontend cache system included within the host.

Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to maintain cache coherency among multiple storage nodes. It can also be employed to avoid sending the data to a network node over a network if it already has the data.

Abstract: Provided are an apparatus and method for maintaining cache coherency, and a multiprocessor apparatus using the method. The multiprocessor apparatus includes a main memory, a plurality of processors, a plurality of cache memories that are connected to each of the plurality of processors, a memory bus that is connected to the plurality of cache memories and the main memory, and a coherency bus that is connected to the plurality of cache memories to transmit coherency related information between caches. Accordingly, a bandwidth shortage phenomenon may be reduced in an on-chip communication structure, which occurs when using a communication structure between a memory and a cache, and communication for coherency between caches may be simplified.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.

Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

Abstract: A data processing apparatus (2) comprises a first protocol domain A configured to operate under a write progress protocol and a second protocol domain B configured to operate under a snoop progress protocol. A deadlock condition is detected if a write target address for a pending write request issued from the first domain A to the second domain B is the same as a snoop target address or a pending snoop request issued from the second domain B to the first domain A. When the deadlock condition is detected, a bridge (4) between the domains may issue an early response to a selected one of the deadlocked write and snoop requests without waiting for the selected request serviced. The early response indicates to the domain that issued the selected request that the selected request has been serviced, enabling the other request to be serviced by the issuing domain.

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract: A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received.

Abstract: A method according to one embodiment includes outputting a first alert when a cache free space size is less than a first threshold and entering into a warning state, and outputting a second alert when the cache free space size is less than a second threshold and entering into a critical state. At least one scratch volume is deleted when in the critical state, the scratch volume chosen based on at least one of: a length of time the scratch volume has been designated scratch, a priority level of the information stored on the scratch volume, and a scratch delay value associated with the scratch volume.

Abstract: A data writing method, a hard disc module, and a data writing system for writing data into the hard disc module are provided, wherein the hard disc module includes a plurality of memory units. The data writing method includes the following steps. A cache data is received and a data class of the cache data is determined. If the data class of the cache data belongs to a first type, the cache data is distributed and written to the memory units. If the data class of the cache data belongs to a second type, the cache data is written to one of the memory units.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract: A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.

Abstract: An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.

Abstract: A system and method for efficiently storing data both on-site and off-site in a cloud storage system. Data read and write requests are received by a cloud data storage system. The cloud storage system has at least three data storage layers. A first high-speed layer, a second efficient storage layer, and a third off-site storage layer. The first high-speed layer stores data in raw data blocks. The second efficient storage layer divides data blocks from the first layer into data slices and eliminates duplicate data slices. The third layer stores data slices at an off-site location.