Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: A memory system and method for power management are disclosed. In one embodiment, a variable credit value that indicates an amount of power currently available for memory operations in the memory system, wherein for each update cycle of the variable credit value, the variable credit value is reduced by a computed consumed energy value for that update cycle; receives a request to perform a memory operation; determines if the variable credit value is greater than a minimum value required to perform the memory operation; and grants the request to perform the memory operation only if it is determined that the variable credit value is greater than the minimum value. Other embodiments are disclosed.

Abstract: A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.

Abstract: A semiconductor memory apparatus may include a data pad and a shared transmission line. The shared transmission line may be configured to transmit data received through the data pad to a data alignment unit in a write operation, and transmit data outputted from a pipe latch unit to the data pad in a read operation.

Abstract: An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to Nth signals and a first bit of a binary code, and a second stage including second logic gates each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code.

Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.

Abstract: Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data (DQ) and data strobe (DQS) signals from system memory during read operations. The memory interface circuitry may include startup calibration circuitry and runtime calibration circuitry. The startup calibration circuitry may be used upon device startup to perform a one-time data de-skew and DQ/DQS centering. The runtime calibration circuitry may include at least two data sampling circuits, a first of which is used in active mode to latch incoming data and a second of which is used in redundant mode to obtain data eye boundary information on a continuous basis. The received DQS signal may be adjusted based on the obtained eye boundary information so that DQS properly positioned within the data eye periodically or on an as-needed basis.

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.

Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

Abstract: A memory device includes a memory bank including a plurality of word lines, and a word line controller capable of activating a first word line, which is accessed during a previous write operation, among the plurality of word lines, while activating a second word line corresponding to an input address among the plurality of word lines, during an active operation.

Abstract: A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract: A NVDRAM includes a first NV element coupled to a first terminal of a second NV element at a transfer node. A volatile cell has a transfer transistor coupled to the transfer node and has a storage node. A first NV line is coupled to the second terminal of the first NV element. Circuitry applies an alternated signal to the transfer node, couples the second terminal of the second non-volatile element to a second NV line, and applies a program signal across the first and second NV lines during a program mode that establishes a logic state. The circuitry applies a read signal across the first and second NV lines, couples the second terminal of the second NV element to the second NV line, and replaces the alternated signal with floating during a restore mode that loads the logic state into the storage node.

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract: A memory cell includes a bistable element and two p-channel transistors (i.e., first and second p-channel transistors). The bistable element includes a plurality of inverting circuits and at least one data storage node. The bistable element may be formed in a first region on the substrate that is partially formed by a p-type diffusion region and an n-type diffusion region. The first and second p-channel transistors are coupled serially. The first p-channel transistor may also have its gate terminal coupled to the at least one data storage node of the bistable element. A method of manufacturing the memory cell includes forming a bistable element having at least first and second data storage nodes, forming a write-only port of the memory cell over an n-type diffusion region and forming a read-only port of the memory cell over a p-type diffusion region.

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell configured to be powered from a first voltage source, a bitline, and a write driver configured to write to the memory cell through the bitline, the write driver comprising a pull-up circuit to pull up bitline voltage towards a second voltage source while using the first voltage source to limit the bitline voltage, the first and second voltage sources being in different voltage domains.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Abstract: A memory driving circuit includes a current source configured to output a second current, a first switching unit configured to undergo switching to connect to the current source selectively to output the second current, a voltage generating unit configured to provide a reference voltage, a capacitive energy storage unit configured to store energy according to the reference voltage, a third switching unit configured to undergo switching to connect the voltage generating unit and the capacitive energy storage unit selectively, a second switching unit configured to undergo switching to connect the capacitive energy storage unit selectively to output a third current, and a current output terminal configured to output the second current, the third current, or the sum of the second current and the third current.

Abstract: An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.

Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, and a plurality of memory cells provided between the first lines and the second lines at intersections of the first lines and the second lines. Each of the memory cells includes a variable resistance element coupled to and disposed between a corresponding second line and first and second selection elements, the first selection element coupled to and disposed between the variable resistance element and a corresponding first line, and the second selection element coupled to and disposed between the variable resistance element and the corresponding first line. The first selection element allows a bidirectional current flow therethrough, and the second selection element allows a unidirectional current flow therethrough.

Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.

Abstract: A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current electrode. A second select transistor has a first current electrode coupled to a second bit line, a control electrode and a second current electrode. A first bi-directional resistive element has a cathode coupled to the second current electrode of the first select transistor and an anode coupled to an internal node. A second bi-directional resistive element has a cathode coupled to the internal node and an anode coupled to the second current electrode of the second select transistor. A third transistor has a first current electrode coupled to a third bit line, a second current electrode coupled to the internal node, and a control electrode coupled to a word line.

Abstract: An MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Abstract: A nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a CSL driver, and control logic. The memory cell array includes a plurality of memory blocks each having a plurality of strings that are formed in a direction perpendicular to a substrate and are connected between bit lines and a common source line. The CSL driver sets up the common source line with a predetermined voltage and supplies or drains charge to or from the common source line using a voltage level of the common source line as a feedback signal.

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming memory cells which share a data storage layer; performing a first strong program operation on first memory cells, arranged in a checker board pattern among the memory cells; performing a first annealing process after the first strong program operation; performing a second strong program operation on second memory cells arranged in a reverse checker board pattern among the memory cells, and performing a slight program operation on the first memory cells; and performing a second annealing process after the second strong program operation and the slight program operation.

Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Abstract: A NVM apparatus and an operation method thereof are provided. The NVM apparatus includes a NVM cell, a programming voltage generator, a WL-voltage generator and a CSL-voltage generator. A control terminal, and a first and second terminals of the NVM cell are electrically connected to a word line, a bit line and a common source line, respectively. The programming voltage generator provides a programming voltage to the bit line and detects a current thereof. The WL-voltage generator provides a WL-voltage to the word line, where a switch of the WL-voltage is a word line high voltage to a word line low voltage. The CSL-voltage generator provides a CSL-voltage to the common source line. According to the current of the bit line, the WL-voltage generator dynamical adjusts the word line low voltage, or the CSL-voltage generator dynamically adjusts the CSL-voltage.

Abstract: A storage device is provided. The storage device includes a memory controller and at least one nonvolatile memory device including memory blocks having a pipe-shaped bit cost scalable (PBiCS) structure. Each of the memory blocks penetrates word lines stacked on a substrate in the form of plates and includes a first pillar, a second pillar, and a back-gate. The second pillar includes a semiconductor layer, an insulating layer, and a charge storage layer. The back-gate includes a pillar connection portion to connect the first and second pillars to each other and is disposed between the substrate and the word lines. The memory controller includes an adjacent cell management unit configured to control the at least one nonvolatile memory device such that a program operation, an erase operation or a read operation is performed on memory cells adjacent to the back-gate, unlike the other memory cells.

Abstract: A method for driving a nonvolatile memory device includes performing an erase operation with respect to a plurality of memory cells, stopping the erase operation by a suspend command, calculating a residual time of the erase operation that has not yet been performed, performing a first operation, comparing a first vacant time between a completion time point of the first operation and a start time point of a second operation with the residual time, performing the erase operation that has not yet been performed if the residual time is equal to or shorter than the first vacant time, and performing the second operation if the residual time is longer than the first vacant time.

Abstract: In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current for a separately-selectable set of NAND strings of the block. A bit line voltage adjustment unit is configured to apply a first and second bit line voltages to separately-selectable sets of NAND strings that have bit line currents greater and less than the minimum current respectively, the second bit line voltage being greater than the first bit line voltage.

Abstract: A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled to one of the word lines. Each of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array. Each subset includes a plurality of memory cells. A voltage switch supplies a respective one of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the voltage supply lines. The aged voltage supplied to a first of the plurality of subsets of memory cells is different than the aged voltage supplied to a second of the plurality of subsets of memory cells.

Abstract: A fuse circuit includes an E-fuse array including a plurality of E-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the E-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals.

Abstract: A semiconductor device with a fuse controller and a fuse array. The fuse controller may be configured to generate internal address signals according to a level combination of repair data and may generate first and second voltage control signals in response to a rupture control signal that is enabled to rupture a predetermined fuse set for selecting a failed redundancy word line, in a test mode. The fuse array may include a plurality of fuse sets including the predetermined fuse set. Each of the plurality of fuse sets may be selected according to a level combination of the internal address signals, and the fuse array ruptures the predetermined fuse set for selecting the failed redundancy word line in response to the first and second voltage control signals to output fuse data.

Abstract: A multi-phase gate driver includes a start/end signal generator circuit and X shift register modules. The start/end signal generator circuit is configured to sequentially output N start signals and N end signals according to a first control signal, a second control signal and N groups of clock signals. Each start and end signals have a delay relative to the previous one. Each group of clock signals includes a first clock signal and a second clock signal, which are inverted to each other. The X shift register modules are electrically coupled to the start/end signal generator circuit and each includes N shift register units. The Mth shift register unit of the first shift register module outputs a gate signal according to the Mth group of clock signals, the Mth start signal, and the gate signal outputted from the Mth shift register unit in the second shift register module.

Abstract: Sampling is continuously performed at high speed with a simple sampling circuit including a polarity switcher to invert or non-invert the polarity of an input signal; an integrating circuit to integrate the signal output from the polarity switcher to output integrated values corresponding to the amount of charge stored in a capacitor; a computing section configured to compute a sampling value every sampling period in such a manner that a difference between one of the integrated values output from the integrating circuit at the start of the sampling period and another one of the integrated values output from the integrating circuit at the end of the sampling period is multiplied by a sign corresponding to the polarity set by the polarity switcher; and a control section configured to control the polarity switcher to alternately invert the polarity of the input signal every sampling period in synchronization with a sampling cycle.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Abstract: A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

Abstract: A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region of the MRAM array that includes second memory cells. The device includes a fail address region of the MRAM array, a first row of the fail address region including validity data, wherein the validity data includes multiple validity indicators, a last row indicator, or both.

Abstract: A post package repair device may include a plurality of bank groups, each of the plurality of bank groups including fuses indicating repair information, configured to share a predetermined number of fuses. The post package repair device may include a resource detection unit configured to determine the availability of the fuses from among the plurality of bank groups.

Abstract: Disclosed embodiments include nuclear fission reactor cores, nuclear fission reactors, methods of operating a nuclear fission reactor, and methods of managing excess reactivity in a nuclear fission reactor.

Abstract: An inspection apparatus for a penetration pipe of a nuclear reactor head comprising: a body; a probe module installed at the body and having a probe which is inserted in the penetration pipe to inspect damage of the penetration pipe; a fixing module installed along a longitudinal direction of the body and having an expanding cylinder which is inserted in the penetration pipe to support an inner diameter of the penetration pipe; and a rotating module installed in the longitudinal direction of the body and having an expanding cylinder which is inserted in the penetration pipe to support the inner diameter of the penetration pipe.

Abstract: Cu—Ni—Si—Co copper alloy strip having excellent balance between strength and electrical conductivity which can prevent the drooping curl is provided. The copper alloy strip for an electronic materials contains 1.0-2.5% by mass of Ni, 0.5-2.5% by mass of Co, 0.3-1.2% by mass of Si, and the remainder comprising Cu and unavoidable impurities, wherein the copper alloy strip satisfies both of the following (a) and (b) as determined by means of X-ray diffraction pole figure measurement based on a rolled surface: (a) among a diffraction peak intensities obtained by ? scanning at ?=20° in a {200} pole figure, a peak height at ? angle 145° is not more than 5.2 times that of standard copper powder; (b) among a diffraction peak intensities obtained by ? scanning at ?=75° in a {111} pole figure, a peak height at ? angle 185° is not less than 3.4 times that of standard copper powder.

Abstract: A method for forming a transparent conducting oxide product layer. The method includes use of precursors, such as tetrakis-(dimethylamino) tin and trimethyl indium, and selected use of dopants, such as SnO and ZnO for obtaining desired optical, electrical and structural properties for a highly conformal layer coating on a substrate. Ozone was also input as a reactive gas which enabled rapid production of the desired product layer.

Abstract: The present disclosure is directed to conductive, translucent water-borne conductive coatings comprising a water-borne lubricant coating base material, an amount of PEDOT:PSS solution, and an amount of metal-containing nanowire, methods for making the same, and articles coated with such coatings.