Abstract: As disclosed herein a method, executed by a computer, for enabling multi-tiered software stack diagnostic collection includes initiating, on a first tier of a multi-tiered software stack, a targeted diagnostics collection corresponding to a symptom of a failure, determining a symptom to a reason code mapping corresponding to the symptom in a product of a subsequent tier, and issuing a command to the product of the subsequent tier to initiate targeted diagnostics collection corresponding to the reason code. Problems or failures in a multi-tiered software stack environment may require analyses of programs or products corresponding to each tier of a multi-tiered software stack. The method described herein enables simultaneous collection of diagnostics for programs or products corresponding to each tier of a multi-tiered software stack. A computer system, and a computer program product corresponding to the method are also disclosed herein.

Abstract: A computing environment includes multiple software programs running on multiple endpoint computing machines. Each software program has associated diagnostics data. Each endpoint machine is running a diagnostics agent. The diagnostics agents are in communication with each other. A monitoring server interacting with the multiple software programs detects a malfunctioning associated with a software program running on a target endpoint, and submits a request to collect the diagnostics data of the malfunctioning software program. This collecting request is submitted to a service software program different from the malfunctioning program. The service software program may be running on a service endpoint different from the target endpoint. The requested diagnostics data is retrieved by the service software program from a diagnostics agent running on the target endpoint. The monitoring server then receives the requested diagnostics data from the service software program.

Abstract: One or more problems may be detected in an executing application by retrieving runtime execution information from the application executing on one or more computers. The runtime information is transformed into a temporal sequence of events. A knowledgebase is searched for a dialog that has nodes in an order that match the temporal sequence of events according to a threshold degree. Responsive to finding the dialog in the knowledgebase, the dialog is launched on a user interface to interact with a user and guide the user through a problem identification and solution. Responsive to not finding the dialog, additional instrumenter is enabled in the application.

Abstract: The present invention belongs to the technical field of software development and maintenance, and more especially related to a code consistency checking method. The consistency checking method of the present invention sustains the code consistency checking and maintenance in large-scale program at the code segment and function level rather than checking of duplicated files only, and maintains the consistency checking of duplicated codes at the development stage in the software development cycle, namely, before test phase, so as to greatly reduce the fix time of errors caused by inconsistency problems.

Abstract: A method to determine a valid input sequence for an unknown binary program is provided. The method may include obtaining an input sequence for an unknown binary program. The method may also include obtaining a memory address range for each of one or more variables in the unknown binary program and executing an instrumented version of the unknown binary program with the input sequence as an input to the instrumented version of the unknown binary program. The method may also include recording one or more memory addresses accessed during the execution of the instrumented version of the unknown binary program and determining that the unknown binary program accepts the input sequence as valid based on one or more of the one or more recorded memory addresses corresponding to the memory address range of one or more of the variables in the unknown binary program.

Abstract: A system and method for determination of code coverage for software applications in a network environment. In accordance with an embodiment, a software application can be instrumented by a code coverage tool to contain instructions for tracing executed code, and sending collected data to a network grabber at an indicated network address or port. A code coverage tool enables tests to be run on an instrumented software application. A network grabber receives, at a network address or port, code coverage data from one or more application tests.

Abstract: Techniques are disclosed for automatically determining tests to run on source code based on code coverage. In one embodiment, an extensible system takes as input a configuration file having pointers to an IP address of a server where tests are being run and a type of code coverage instrumentation. An agent configured to instrument source code and collect code coverage information is copied to the server at the IP address. During a training phase, the agent intercepts tests being run on source code and provides a dump of the interception results after each test is executed. Using such results, mappings of the tests to the source code is created and stored. During an execution phase, when new or modified source code file is being checked in, a testing application retrieves for execution tests which map to the source code file and to code dependent on the source code file.

Abstract: Example embodiments relate to determining code coverage based on production sampling. In example embodiments, a production execution data set that includes metrics for code units of a software application is obtained, where the metrics include input and output values for each of the code units and an average execution count for each of the code units. Further, application code execution is tracked during a testing procedure of the software application to determine executed lines of code. At this stage, production code coverage of the software application is determined based on the production execution data set and the executed lines of code.

Abstract: A test coverage analysis method and corresponding apparatus are disclosed, wherein, by executing the program under test using one or more test cases, generating one or more heapdump files containing the call stack information of the program under test, and analyzing the call stack information in the one or more heapdump files, the coverage information of the one or more test cases in terms of functions in the program under test is obtained.

Abstract: A method for creating an execution flow from a sequential list of test cases comprises receiving by an application lifecycle management tool used for computer software testing, the list and removing all dependency associations associated with the test cases. Independently of a graphical user interface, a first test case is designated as a source test case, a sequentially next test case is designated as a subordinate test case, and a dependency association is created between the source test case and the subordinate test case. If any test case is not associated with a dependency association, then the subordinate test case is designated as the source test case, a sequentially next test case from the list is designated as the subordinate test case, and a dependency association is crested between them until every test case in the list is associated with a dependency association.

Abstract: A system comprising at least one computer hardware processor configured to perform: generating an object hierarchy comprising a plurality of objects corresponding to active graphical user interface (GUI) elements of at least one application program; controlling the at least one application program to perform a task comprising a sequence of actions at least in part by using the object hierarchy to invoke actions in the sequence of actions; during performance of the sequence of actions, generating a log of already-performed actions in the sequence of actions; generating contextual information associated with the already performed actions, the contextual information containing at least some information not in the log and the log containing at least some information not in the contextual information; and providing to a user the log and the contextual information.

Abstract: A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit assumption is information that is not expressly stated in the documentation, but which would be useful in assisting an application developer in building an application. The framework also describes a systematic approach for identifying one or more vulnerability patterns based on the identified implicit assumptions. An application developer may run a test on an application that is being developed to ensure that it does not have any deficiency which matches a vulnerability pattern.

Abstract: A method and apparatus for testing an application. The method displays, by a computer system, simulations of a graphical user interface for the application for a group of different types of devices on a display system. The method further displays, by the computer system, a group of controls in the graphical user interface displayed in the group of different types of devices on the display system. The method still further displays, by the computer system, a change to the graphical user interface in all of the simulations when a user input manipulates a control in a simulation in the simulations. A testing of the graphical user interface for the application for the group of different types of devices is enabled.

Abstract: A memory manager in a computing device allocates memory to programs running on the computing device, the amount of memory allocated to a program being a memory commit for the program. When a program is in a state where the program can be terminated, the content of the memory pages allocated to the program is compressed, and an amount of the memory commit for the program that can be released is determined. This amount of memory commit is the amount that was committed to the program less any amount still storing (in compressed format) information (e.g., data or instructions) for the program. The determined amount of memory commit is released, allowing that amount of memory to be consumed by other programs as appropriate.

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

Abstract: A region descriptor management method and an electronic apparatus are provided. The region descriptor management method is adapted to a device controller of the electronic apparatus and includes following steps. Region descriptor entries are fetched from a region descriptor table. Each of the region descriptor entries includes a block initial address and a block length to describe a memory block of a memory module. According to the block initial addresses and the block lengths of the region descriptor entries, a portion of the region descriptor entries are adjusted to be at least one current region descriptor entry. Based on the at least one current region descriptor entry, a current region descriptor table is generated.

Abstract: A semiconductor device includes a mapping table that stores a corresponding relation between a logical address defined on a basis of regions and a physical address defined on a basis of extents, wherein one or more extents are dynamically allocated to one region.

Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency.

Abstract: A controller creates a basic volume based on the plurality of physical storage devices, creates a first virtual volume based on the basic volume, creates a first auxiliary volume based on the plurality of physical storage devices, and stores area information for associating a basic storage area with a first virtual storage area. In the case in which a read request to the first virtual storage area is issued, the controller determines whether or not a first auxiliary storage area is associated with the first virtual storage area based on the area information. In the case in which the first auxiliary storage area is not associated with the first virtual storage area, the controller executes a read access to the basic storage area. In the next place, the controller measures a read access frequency to the basic storage area.

Abstract: The present invention provides a storage system capable of preventing data loss when power failure or other failures occur to an external power supply, by determining whether the capacity corresponding to the write data can be saved from a volatile memory to a nonvolatile memory based on a charged capacity of a battery used as an internal power supply and a non-backed-up (not yet backed-up) data capacity from the volatile memory to the nonvolatile memory, when storing data from a host computer or a system drive to the volatile memory of the storage system. If it is determined that saving of data is possible, an area corresponding to the write data capacity is allocated in the volatile memory and data is written to the allocated area, but if it is determined that saving of data is not possible, the writing of data is suppressed.

Abstract: A data caching method is disclosed. The method comprises changing, according to an instruction, a cache value, corresponding to a key, in a cache on a volatile memory, recording the instruction following a first effective content of a log file in a non-volatile memory to obtain a second effective content, the second effective content including the first effective content and the recorded instruction, and storing the key and the changed cache value corresponding to the key into the non-volatile memory.

Abstract: A cache memory system including a primary cache and an overflow cache that are searched together using a search address. The overflow cache operates as an eviction array for the primary cache. The primary cache is addressed using bits of the search address, and the overflow cache is configured as a FIFO buffer. The cache memory system may be used to implement a translation lookaside buffer for a microprocessor.

Abstract: A data processing apparatus includes a first agent which generates a cache dormant indication when a cache is in a dormant state, and a second agent which issues cache maintenance requests for data stored in the cache accessed by the first agent. in response to the cache dormant indication generated by the first agent, the second agent may suppress issuing of cache maintenance requests for the cache accessed by the first agent.

Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Abstract: A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises: initiating a transaction for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system for access to system memory at that guest system memory address; storing identification information relating to that transaction including at least data identifying device which requested the transaction; detecting a translation error condition in respect of that transaction; and handling a detected error condition by: (i) providing information indicative of the translation error condition to the guest system overseeing the device which requested the transaction; (ii) receiving a command from the guest system in respect of that transaction, the command from the guest system comprising information identifying the device which requested the transaction; and (iii) validatin

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses using mappings in a first page table accessed by the guest operating system; translating from the intermediate physical addresses to physical addresses using mappings in a second page table accessed by the hypervisor; determining reuse information for a second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page; storing the determined reuse information in both the first page table and the second page table; and using the stored reuse information to store cache lines in selected portions of a first cache.

Abstract: The method for maintaining a storage mapping table is introduced. After a total number of logical blocks, which exceeds a specified number, have been programed into a storage unit, an access interface is directed to program a corresponding group of a storage mapping table of a DRAM (Dynamic Random Access Memory) into a first block of the storage unit according to a group number of an unsaved group queue. A group mapping table of the DRAM is updated to indicate that the latest data of the group of the storage mapping table is stored in which location in the storage unit. The group number is removed from the unsaved group queue.

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. The managing includes: at the second access level, translating from virtual addresses to intermediate physical; at the second access level, determining reuse information for ranges of virtual addresses based on estimated reuse of data stored within a virtual address space; at the first access level, translating from the intermediate physical addresses to physical addresses; at the first access level, determining reuse information for ranges of intermediate physical addresses based on estimated reuse of data stored within an intermediate physical address space; and processing reuse information determined at different access levels to store cache lines in selected portions of a first cache.

Abstract: A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.

Abstract: A self-authenticating encryption bridge, and method of operation thereof, including: a user input module for remaining locked until a user has been authenticated; an encryption/decryption control module responsive to the user input module for encrypting or decrypting data when the user has been authenticated; a first communication channel for transferring encrypted data from a mass storage device to the encryption/decryption control module; and a second communication channel for transferring clear data to a computer from the encryption/decryption control module.

Abstract: Systems and methods for securing configuration information for cloud-based services. A system comprises a data store and data sets including plant process information and configuration information. A memory device stores computer-executable instructions. When executed by a processor coupled to the cloud service, the instructions receive configuration information, store it in a data file, apply a generated certificate to the file, and deploy the resulting protected configuration data file to the cloud-based service. In addition, the protected configuration data file is made available by obtaining the file from the cloud-based service.

Abstract: An apparatus includes a processor having an array of processor interconnects arranged to connect the processor to conductive paths, a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects, an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate, and at least one peripheral circuit connected to the at least one conductive trace

Abstract: A method and system for direct memory transfers between memory modules are described that includes sending a request to a first memory module and storing the data sent on a memory bus by the first memory module into a second memory module. The direct transfer of data between the first and second memory modules reduces power consumption and increases performance.

Abstract: An information processing system comprising: an information processing device coupled to a terminal device; and a monitor device coupled to the information processing device, wherein the information processing device includes a first processor configured to process a request from the terminal device, and calculate a frequency of interrupts received by the first processor, and wherein the monitor device includes a memory, and a second processor configured to obtain, from the information processing device, information on the calculated frequency of interrupts, and determine whether or not the frequency of interrupts exceeds a threshold in a particular period based on the obtained information on the frequency of interrupts, and store a result of the determination in the memory.

Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

Abstract: Methods and systems for monitoring quality of service (QOS) data for a plurality of storage volumes from a storage operating system of a storage system are provided. A performance manager collects QOS data for a storage volume from among the plurality of storage volumes and the QOS data includes a response time in which the storage volume responds to an input/output (I/O) request; determines that the collected QOS data is noisy by comparing an average number of I/O requests processed within a time duration for the storage volume with a first threshold value; uses comparable QOS data of another storage volume for generating an expected range for future QOS data; and monitors QOS data for the storage volume for determining whether a current QOS data for the storage volume is within the expected range.

Abstract: Full bandwidth communication buses are disclosed. While primarily focused on the Serial Low-power Inter-chip Media Bus (SLIMbus) communication bus, the concepts of the present disclosure may be extended to other communication buses. Exemplary aspects of the present disclosure utilize a reserved segment distribution code and a segment length to define a Segment Interval that is better-sized relative to raw data bits. By fitting the segment interval to the size of the raw data bits, bandwidth utilization is maximized, resulting in faster effective data transfers. Completion of such efficient data transfers may allow the communication bus to spend more time in a low-power mode and thus, conserve power. Additionally, such efficient data transfers may allow for better quality in presentation of multimedia content to the user.

Abstract: Disclosed is a semiconductor device including: a bus; a slave function block coupled to the bus; a master function block coupled to the bus through a bus interface, and suitable for providing a bus ID to the slave function block together with a request when transmitting the request to the slave function block; and a subordinate slave function block suitable for monitor the bus interface. The subordinate slave function block catches the data communicated together with the bus ID is matched to any one of a plurality of determined bus IDs.

Abstract: A high frequency apparatus includes a master control device having a serial interface, and a plurality of slave devices having a serial interface. A control device for controlling the operations of the plurality of slave devices is provided. The serial interface of the master control device is connected to the control device and the serial interfaces of the slave devices. The slave devices have a control terminal for receiving a control signal for controlling whether or not each slave device is operable, and each of the control terminals is connected to the control device. The control device transmits the control signal to the control terminals of the slave devices in accordance with a data signal from the master control device.

Abstract: A method for reading/writing a chip in a USB type-C cable comprises converting a read/write command into unstructured vendor defined message (UVDM) that is conforming to a USB power delivery specification. Such UVDM will be delivered to the chip via a type-C configuration channel interface. The chip analyzes the UVDM to acquire the read/write command and reads or modifies the content of a non-volatile memory in the chip according to the read/write command. Due to use of the type-C configuration channel interface, which is inherent in the USB type-C cable, to read/write the chip, it needs no extra interface which otherwise increases costs.

Abstract: A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit is adapted for detecting the state by determining an electrical property of a passive electronic component when connected to the static address selection terminal. The communication circuit is adapted for receiving/transmitting data over the data bus in accordance with a first communication protocol using the node address identifier for identification of the IC, and for receiving/transmitting data over said data bus in accordance with a second communication protocol using a further node address identifier for identification of the IC, wherein the communication circuit is adapted for configuring the further node address identifier by using data received using the first protocol.

Abstract: An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at different power levels to consume different amounts of power. Also, any of the multiple processors may perform different functions. For example, one processor may be a low power processor that may control or operate at least one peripheral device to perform a low capacity function. Control may also switch from the low power processor to a high capacity processor. In one example, the high capacity processor controls the low power processor and further controls the at least one peripheral device through the lower power processor.

Abstract: A communication device is provided. The communication device can include a processing device for communicating data via a data connection or receiving power via an electrical connection and a connector for providing the data connection or electrical connection. The connector can include at least one terminal and a sensing module. The terminal can be communicatively coupled to the processing device. The terminal can form the data connection or electrical connection with at least one external terminal of a mating connector. The sensing module can detect a movement associated with removing the mating connector. The sensing module can provide a termination signal to the processing device to terminate the data connection or electrical connection. The processing device can terminate data communication via the data connection or current flow via the electrical connection in response to the termination signal.

Abstract: System and method for providing adaptive access to a hardware block on a computer system.

Abstract: A motherboard including a socket and a memory slot is provided. The socket is adapted for disposing a processor with at least one memory channel, and each of the memory channels supports at least two memory cards. The memory slot is coupled to the socket and transmits signals from the memory channel. The memory slot includes a plurality of pins. A first part of the pins of the memory slot is assigned to transmit a signal from one of the memory cards supported by the memory channel, and a second part of the pins of the memory slot is assigned to transmit a signal from another one of the memory cards supported by the memory channel.

Abstract: A universal I/O interposer system for processing an I/O signal transmitted between an I/O field device and a controller, the system includes a base connected between the field device and the controller and a number of connector halves attached to the base. An interposer circuit carrier includes a corresponding connector half and includes a signal processing circuit for processing an I/O signal being transmitted between an I/O field device and a controller. An interposer circuit carrier can be changed without disconnecting the base from the field device or controller.

Abstract: A USB chipset coupled between a first device and a second device is provided. A data processing unit is coupled to the first device and generates a plurality of transmission information according to first information provided by the first device. A transmitting unit is coupled to the data processing unit to transmit the transmission information to the second device and includes a converting module, a first output driving module, a second output driving module, and a transmitting-terminal selecting module. The converting module is coupled to the data processing unit to receive the transmission information in parallel and serially outputs the transmission information. The first output driving module is coupled to a first pin set. The second output driving module is coupled to a second pin set. The transmitting-terminal selecting module is coupled between the converting module and the first and second output driving modules.

Abstract: Embodiments of the inventive concept include 2.5 inch hard disk drive form factor solid state drive multi-card adapters that can include multiple M.2 solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate M.2 solid state drive technology into servers. Multiple M.2 solid state drive cards and a peripheral component interconnect express (PCIe) switch can be included within a 2.5 inch hard disk drive form factor solid state drive multi-card adapter. The solid state drive multi-card adapters can be attached to or seated within drive bays of a computer server that supports non-volatile memory express (NVMe) 2.5 inch drives without any changes to the server architecture, thereby providing a straight-forward upgrade path.

Abstract: Aspects disclosed in the detailed description include high-frequency signal observations in electronic systems. In this regard, a high-frequency signal observation circuit is provided in an electronic system to enable high-frequency signal observations. In one aspect, the high-frequency signal observation circuit comprises an observation signal selection circuit. The observation signal selection circuit is programmably controlled to select an observation signal among a plurality of electronic input signals (e.g., control signals) received from the electronic system. In another aspect, the high-frequency signal observation circuit is configured to utilize a bypass data path, which is routed around serializer/deserializer (SerDes) logic in the electronic system, to output the observation signal for observation. By programmably selecting the observation signal and outputting the observation signal via the bypass data path, it is possible to examine accurately any high-frequency signal (e.g.

Abstract: Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.