Abstract: A first network connection is identified between a first software component and a second software component. First data is received from the first software component identifying an amount of data sent over the first network connection. Second data is also received, from the second software component, that identifies the amount of data sent over the first network connection. Further, a particular transaction fragment involving the first and second software components over the first network connection is determined from the received first and second data. In some aspects, the particular transaction fragment can be used in the analysis of a transaction including the particular transaction fragment.

Abstract: An apparatus and method are provided for opportunistically performing scrubbing operations on a memory device. The apparatus is used for accessing the memory device in response to access requests issued by at least one requesting device and comprises interface circuitry that is configured to access the memory device in response to the access requests. The apparatus also comprises activity monitoring circuitry which generates memory access activity data that results from memory access activity between the interface circuitry and the memory device. Scrubbing circuitry is also included and is configured to issue scrubbing access requests to perform the scrubbing operations, the scrubbing access requests being issued in response to the memory access activity data indicating a trigger condition.

Abstract: An information processing apparatus includes a monitoring device including a first communication unit and a first processor. The first communication unit is configured to perform first communication using a first protocol and perform second communication using a second protocol different from the first protocol. The first processor is configured to conduct the first communication via the first communication unit to obtain first data and conduct first determination to determine whether the first data is obtained through the first communication. The first processor is configured to conduct, when it is determined that the first data is not obtained through the first communication, the second communication via the first communication unit to obtain the first data and conduct second determination to determine whether the first data is obtained through the second communication. The first processor is configured to output information on the basis of a determination result of the second determination.

Abstract: A report production apparatus includes a first collection unit configured to make requests depending on multiple types of device management systems respectively to collect pieces of device management information and convert the collected pieces into a common format, each piece of device management information being about usage of devices disposed at a base of the device management system; a second collection unit configured to make a request to collect contract information about quality assurance for the devices from a contract system; a third collection unit configure to make requests depending on multiple types of service desk systems respectively to collect pieces of service information and convert the collected pieces into another common format, each piece of service information being about device abnormality of the devices disposed at the base of the service desk system; and a production unit configured to produce a report using the above information.

Abstract: Tools and techniques assist developers with the detection of memory leaks by using correlation of data type memory usage trends. In particular, investigations of memory leaks can be prioritized without always resorting to the use of bulky and performance-degrading memory dumps, by using these tools and techniques to identify leaky correlated data types. Data about a program's memory usage is processed to identify memory usage trends over time for respective data types, and the trends are searched for significant correlations. Correlated trends (and hence their corresponding data types) are grouped. Memory usage analysis information is displayed for grouped data types, such as the names of the most rapidly leaking data types, the names of correlated data types, leak rates, and leak amounts in terms of memory size and/or data object counts. Memory usage data may also be correlated with processing load requests to indicate which requests have associated memory leaks.

Abstract: Techniques for segregating one or more logs of at least one multitasking user to derive at least one behavioral pattern of the at least one multitasking user are provided. The techniques include obtaining at least one of at least one action log, configuration information, domain knowledge, at least one task history and open task repository information, correlating the at least one of at least one action log, configuration information, domain knowledge, at least one task history and open task repository information to determine a task associated with each of one or more actions and segregate the one or more logs based on the one or more actions, and using the one or more logs that have been segregated to derive at least one behavioral pattern of the at least one multitasking user. Techniques are also provided for deriving intelligence from at least one activity log of at least one multitasking user to provide information to the at least one user.

Abstract: The present disclosure provides method, system, and computer readable medium for shared execution of software. The present disclosure relates to method, system, and computer readable recording medium for shared execution of software involving identifying the main modules of a specific software by analyzing its control flow, data flow, and modular structure through a static binary analysis and a runtime profiling, i.e. dynamic analysis, separating the modules from the main software body to store them in a secure environment of a smart card, and storing the main body in a user terminal with the identified modules removed and replaced by an interface code, whereby a co-processing the software at the user's end by the smart card in engagement with the user terminal exclusively enables an execution of the software.

Abstract: A software test apparatus and a software test method and a computer readable medium thereof are provided. The software test apparatus stores a software testing program, an under-tested code, a plurality of basic test benches and a plurality of candidate test benches. The under-tested code includes a hard-to-detect code and the hard-to-detect code has at least one hard-to-detect section. The software test apparatus runs the software testing program to execute the following operations: parsing the hard-to-detect code to generate a condition-statement tree; based on the basic test benches and the condition-statement tree, using a support vector machine (SVM) to establish a support vector regression (SVR) predictor; and applying the SVR predictor to choose a best candidate test bench from the candidate test benches.

Abstract: A plurality of processing elements having stream operators and operating on one or more computer processors receive a stream of tuples. A first stream operator adds a first attribute to a tuple received on a first port of the first stream operator. The first attribute indicates the first port and the first stream operator. A second stream operator adds a second attribute to a tuple received on a first port of the second stream operator. The second attribute indicates the first port of the second stream operator and the second stream operator. It is determined whether a debug tuple has been received by a third stream operator. A debug tuple is a tuple that includes the first and second attributes. An operation, such as halting execution or incrementing a count of debug tuples, is performed when it is determined that a debug tuple has been received.

Abstract: A method, and associated computer system and computer program product, of detecting source code merge conflicts and compilation errors. Uncommitted changes associated with a source code are received periodically at each time of a sequence of times. A temporary branch corresponding to each uncommitted change associated with the source code is created. The temporary branch corresponding to each uncommitted change is merged to corresponding portions of the source code. It is ascertained that no merge conflict resulted from the merging and in response, a compilation of a merged version of the source code is performed, wherein the merged version of the source code includes the temporary branch corresponding to each uncommitted change. It is determined that no compilation error occurred from the compilation and in response, a version of a product that includes the merged version of the source code is created.

Abstract: Methods, systems, and media for providing determinism in multithreaded programs are provided. In some embodiments, methods for providing determinism in multithreaded programs are provided, the methods comprising: instrumenting a program with: a proxy that: receives inputs to the program; and determines whether a schedule corresponding to a set of input constraints satisfied by the inputs has been memoized; and a replayer that: if it is determined that a schedule corresponding to a set of input constraints satisfied by the inputs has been memoized, processes the inputs by the program according to the schedule.

Abstract: A computer implemented method for identifying program flow in a computer program, executing in a debugger on at least one processor, subsequent to suspending execution of the computer program at a user breakpoint can include suspending execution of the computer program at a first user breakpoint, setting, by the debugger, one or more tracking breakpoints in one or more routines that can continue execution from the first user breakpoint, then resuming execution of the computer program. The method may be continued by suspending execution of the computer program at a second user breakpoint after processing by the at least one processor at least one instruction of the computer program. The method may further include determining whether to provide an indicator to indicate that at least one of the one or more tracking breakpoints was hit during the executing, and providing the indicator in response to determining to provide the indicator.

Abstract: The invention relates to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor.

Abstract: A computer system comprising a display, one or more computer readable medium storing a computer application comprising computer executable code for creating a graphical user interface, one or more processors receiving and executing the computer executable code to provide the graphical user interface on the display, the computer readable medium also storing a testing application comprising computer executable code for activating the graphical user interface, the testing application defining a command execution server embedded into the computer application, and a command client external to the computer application.

Abstract: An application development center system is described. A method may comprise receiving an application at a server computing device; accessing test data from one or more data sources; testing the application within a development environment resident on the server computing device utilizing the test data; and presenting test results on a user interface accessible by a client computing device. Other embodiments are described and claimed.

Abstract: A method, computer program product, and system for risk monitoring of continuous software delivery include a first plurality of test data. The first plurality of test data is associated with one or more software components. In response to receiving a changelog, a change in the received plurality of test data is determined. A risk profile for the one or more software components is generated, in response to receiving the first plurality of test data and the received changelog. A component code graph is generated, based on the risk profile associated with the one or more software components and a risk value associated with the generated risk profile is calculated, based on the component code graph.

Abstract: A methods, apparatus and product for explaining partially illegal combinations in combinatorial models. The method comprising: obtaining a combinatorial model defining a legal test space, the combinatorial model comprising a set of attributes, a respective domain for each attribute defining possible values for the attribute, and a set of restrictions, wherein the restrictions define a combination of values of the attributes that are illegal and are excluded from the legal test case; obtaining a partially illegal combination defining value assignments to a portion of the attributes; automatically identifying an extension of the partially illegal combination, wherein the extension is excluded from the legal test space, wherein the extension can be modified to become legal by changing a portion of the value assignments defined by the partially illegal combination; and outputting the extension.

Abstract: A method of mining test coverage data includes: at a device having one or more processors and memory: sequentially processing each of a plurality of coverage data files that is generated by executing the program using a respective test input of a plurality of test inputs, where the processing of each current coverage data file extracts respective execution counter data from the current coverage data file; after processing each current coverage data file, determining whether the respective execution counter data extracted from the current coverage data file includes a predetermined change relative to the respective execution counter data extracted from previously processed coverage data files; and in response to detecting the predetermined change for the current coverage data file, including the respective test input used to generate the current coverage data file in a test input collection for testing the program.

Abstract: In one embodiment, a method of testing a software is disclosed. The method comprises: providing an input event to the software under test, wherein the software under test is associated with a time delay between an input event and an output event; identifying one or more discrete time instances based on the time delay between the input event and the output event; and testing the software under test by synthetically setting a clock to the one or more discrete time instances.

Abstract: In some implementations, a testing service receives a test execution request for executing test operations on a test target. The testing service may map the test execution request to a particular type of supported test framework from among a plurality of types of supported test frameworks. The testing service may obtain a test package provided by a user that requested the testing, such as from a cloud storage location. The testing service determines a computing capacity for executing the testing and appropriates a plurality of workers in a cloud computing service. The testing service configures the plurality of workers for executing the test operations based on at least one of the test framework, the test execution request or the test package. The testing service provides test execution chunks from the test package to the plurality of workers for executing the testing on the test target.

Abstract: Removing high level logic structure from a source program. Two or more source program fields are characterized by their respective value characteristics. A first field is mapped, with respect to the source program, to a second field having similar value characteristics as the first field. A target program is then created by replacing, in the source program, the first field with the second field and replacing each first field value with a corresponding second field value thereby preserving the value characteristics of the source program.

Abstract: An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.

Abstract: Embodiments of the invention relate to sparsity-driven matrix representation. In one embodiment, a sparsity of a matrix is determined and the sparsity is compared to a threshold. Computer memory is allocated to store the matrix in a first data structure format based on the sparsity being greater than the threshold. Computer memory is allocated to store the matrix in a second data structure format based on the sparsity not being greater than the threshold.

Abstract: Embodiments relate to granular management of data storage blocks in a data storage system. In one aspect, status values are employed to track “used”, “free”, and “claimed free” storage blocks. A storage block having stored data is identified as used, a storage block available to store data is identified as free, and a storage block having previously stored data removed that has not been reclaimed is identified as claimed free. These values are maintained on a map to track each data block within the data storage system. One or more used blocks are de-allocated, which includes changing the status value of each used block to claimed free Available claimed free data blocks are prioritized for data block allocation over available free data blocks for efficient storage, including enabling efficient reclamation of data blocks and minimizing data movement needed for reclamation-oriented de-fragmentation.

Abstract: A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.

Abstract: A control device includes a control unit that performs a writing control of supplied host data, according to a data writing request from a host apparatus, with respect to a non-volatile memory where multi-value storage with 2 bits or more is performed in one memory cell, having a lower level page and an upper level page for at least the multi-value storage as a physical page in which a physical address is set, and where data writing is performed using each physical page in an order of physical addresses, and that causes the data writing to be performed until the physical page immediately before the lower level page, such that the data writing according to a next data writing request is started from the lower level page.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: At least one guest system, for example, a virtual machine, is connected to a host system, which includes a system resource such as system machine memory. Each guest system includes a guest operating system (OS). A resource requesting mechanism, preferably a driver, is installed within each guest OS and communicates with a resource scheduler included within the host system. If the host system needs any one the guest systems to relinquish some of the system resource it currently is allocated, then the resource scheduler instructs the driver within that guest system's OS to reserve more of the resource, using the guest OS's own, native resource allocation mechanisms. The driver thus frees this resource for use by the host, since the driver does not itself actually need the requested amount of the resource.

Abstract: Provided are a method, system, and computer program product for processing read and write requests in a storage controller. A host adaptor in the storage controller receives a write request from a host system for a storage address in a storage device. The host adaptor sends write information indicating the storage address updated by the write request to a device adaptor in the storage controller. The host adaptor writes the write data to a cache in the storage controller. The device adaptor indicates the storage address indicated in the write information to a modified storage address list stored in the device adaptor, wherein the modified storage address list indicates modified data in the cache for storage addresses in the storage device.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.

Abstract: A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system executes a lock-acquire instruction in an HLE environment and records information about a lock elided to begin HLE transactional execution of a code region. The processor detects a pending point of failure in the code region during the HLE transactional execution. The processor stops HLE transactional execution at the point of failure in the code region. The processor acquires the lock using the information, and based on acquiring the lock, commits the speculative state of the stopped HLE transactional execution. The processor starts non-transactional execution at the point of failure in the code region.

Abstract: An integrated circuit system including a first integrated circuit chip including first logic, a second integrated circuit chip, and second logic distributed across the first and second integrated circuit chips. The second logic includes a first unit integrated in the first integrated circuit chip and a second unit integrated in the second integrated circuit chip. The integrated circuit system further includes a physical communication link coupling the first unit in the first integrated circuit chip and the second unit in the second integrated circuit chip and a request interface between the first logic and first unit of the second logic. The request interface is implemented in the first integrated circuit such that communication via the request interface between the first logic and the first unit of the second logic has low latency and such that the request interface is decoupled from the physical communication link.

Abstract: Sharing local cache from a failover node, including: determining, by a managing compute node, whether a first compute node and a second compute node each have a local cache, where the second compute node is a mirrored copy of the first compute node; responsive to determining that the first compute node and the second compute node each have a local cache, combining, by the managing compute node, local cache on the first compute node and local cache on the second compute node into unified logical cache; receiving, by the managing compute node, a memory access request; and sending, by the managing compute node, the memory access request to an appropriate local cache in the unified logical cache.

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a pending request buffer and a control circuit. The pending request buffer may include a plurality of buffer entries. The control circuit may be coupled to the pending request buffer and may be configured to receive a request for a first cache line from a pre-fetch engine, and store the received request in an entry of the pending request buffer. The control circuit may be further configured to receive a request for a second cache line from a processor, and store the request received from the processor in the entry of the pending request buffer in response to a determination that the second cache line is the same as the first cache line.

Abstract: Techniques for using a host-side cache to accelerate virtual machine (VM) I/O are provided. In one embodiment, the hypervisor of a host system can intercept an I/O request from a VM running on the host system, where the I/O request is directed to a virtual disk residing on a shared storage device. The hypervisor can then process the I/O request by accessing a host-side cache that resides one or more cache devices distinct from the shared storage device, where the accessing of the host-side cache is transparent to the VM.

Abstract: Systems and methods for managing records stored in a storage cache are provided. A cache index is created and maintained to track where records are stored in buckets in the storage cache. The cache index maps the memory locations of the cached records to the buckets in the cache storage and can be quickly traversed by a metadata manager to determine whether a requested record can be retrieved from the cache storage. Bucket addresses stored in the cache index include a generation number of the bucket that is used to determine whether the cached record is stale. The generation number allows a bucket manager to evict buckets in the cache without having to update the bucket addresses stored in the cache index. Further, the cache index can be expanded to accommodate very small records, such as those generated by legacy systems.

Abstract: When a request is made to retrieve a guest physical page from memory and a page fault occurs, a guest virtual page address that corresponds to the guest physical page is identified along with addresses for guest virtual pages that are near the guest virtual page in the virtual address space. Each identified guest virtual page address is translated into a corresponding guest physical page address and the corresponding guest physical pages are loaded into memory.

Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

Abstract: One method includes streaming a data segment to a write buffer corresponding to a virtual page including at least two physical pages. Each physical page is defined within a respective solid-state storage element. The method also includes programming contents of the write buffer to the virtual page, such that a first portion of the data segment is programmed to a first one of the physical pages, and a second portion of the data segment is programmed to a second one of the physical pages.

Abstract: Systems and methods for verifying the wiping of a storage device using one of either a partial scan verification or a full scan verification, wherein a partial scan verification may be conducted based on at least one metric associated with the storage device and a threshold value for the at least one metric.

Abstract: Methods, devices, and systems for encrypting a communication from a device are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to generate a subset-sum problem and a Goldreich-Levin hash function and encrypt a communication from the device using the subset-sum problem and the Goldreich-Levin hash function.

Abstract: According to one embodiment, a memory system includes an application module, a storage module, and a control module. The storage module stores user data, application software configured to control operation of the application module, and management information used to manage the user data and the application software. The control module controls writing and erasing of the storage module. The control module masks information indicating an access-prohibited area included in the management information read from the storage module, the access-prohibited area includes the application software.

Abstract: A memory system is provided, which includes a real memory space and a virtual memory space. The memory system includes a memory device having a first memory space which is accessed using a first memory address and a second memory space which is accessed using a second memory address, and a memory controller configured to control access to the memory device; wherein the memory controller is configured to translate the first memory address into the second memory address mapped thereto in response to a request for access to the first memory space, access the second memory space using the translated second memory address, and access the second memory space using the non-translated second memory address, in response to a request for access to the second memory space.

Abstract: Technologies for secure inter-virtual-machine shared memory communication include a computing device with hardware virtualization support. A virtual machine monitor (VMM) authenticates a view switch component of a target virtual machine. The VMM adds configures a secure memory view to access a shared memory segment. The shared memory segment may include memory pages of a source virtual machine or the VMM. The view switch component switches to the secure memory view without generating a virtual machine exit event, using the hardware virtualization support. The view switch component may switch to the secure memory view by modifying an extended page table (EPT) pointer. The target virtual machine accesses the shared memory segment via the secure memory view. The target virtual machine and the source virtual machine may coordinate ownership of memory pages using a secure view control structure stored in the shared memory segment. Other embodiments are described and claimed.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.