Abstract: A variable speed drive system employing an electric motor and a frequency converter arranged between an AC power source and the electric motor is operated. The frequency converter functions to convert AC power obtained from the AC power source at a source frequency to converted power at a variable drive frequency. A mechanical assembly can be coupled to the electric motor. Electric modulation circuitry is provided interacting with the frequency converter. It is arranged to impose fluctuations, independently from any torsional excitation in the mechanical assembly and the AC power source, in the inter-harmonic frequencies of inter-harmonic currents generated in the frequency converter.

Abstract: A power circuit is configured with mostly passive electrical components to connect a phase shift capacitor to a phase shift winding of a PSC motor selectively. The power circuit includes a timing circuit, a switching circuit, and a triac having a first anode connected to the second capacitor and a second anode connected to electrical ground. The timing circuit has a plurality of passive electrical components and a single active comparator configured to generate a signal indicative of an expiration of a predetermined time period after application of a line voltage to the motor. The switching circuit has a plurality of passive electrical components and a single active switch, which generates a signal to operate the triac to electrically connect the second capacitor to the second winding during the predetermined time period and to disconnect electrically the second capacitor from the second winding in response to a signal generated by the timing circuit indicating the predetermined time period has expired.

Abstract: A poly-phase motor drive includes an input EMI filter having a poly-phase filter input and a poly-phase filter output and an active rectifier connected to the filter output. The input EMI filter includes notch filters tuned at active rectifier and motor drive inverter switching frequencies and diverts common-mode current into DC bus. The active rectifier has a DC output. A motor drive inverter is connected to the DC output. The motor drive inverter has a poly-phase motor control output.

Abstract: In a control apparatus, a target harmonic current obtainer obtains, according to a phase current flowing through at least one phase winding of a stator, a target harmonic current component flowing in a rotary machine. The target harmonic current component is included in a fundamental current component of the phase current. An inducing unit superimposes, on the phase information, a fluctuating signal that changes at an angular velocity identical to an angular velocity of the target harmonic current component, to induce a counteracting harmonic current component in the at least one phase winding. The counteracting harmonic current component counteracts the target harmonic current component.

Abstract: An over temperature protection device for electric motors applicable to a railway vehicle driving system that operates a plurality of electric motors in parallel using one or a plurality of inverter devices includes a control device configured to control the operation of an inverter device and a protecting device configured to detect, on the basis of a frequency fs including frequency information at the time when the inverter device is applying control for fixing a ratio of a voltage and a frequency to electric motors and electric currents of at least one phase flowing to the electronic motors, an over temperature that could occur in the electric motors, to generate an over temperature protection signal Tf for protecting the electric motors from the over temperature, and to output the over temperature protection signal Tf to the control device.

Abstract: A controller for an electric compressor sets a temperature rise region A, a temperature drop region B, and a steady region C from change in temperature of switching elements, and sets a carrier frequency for each of the set regions. In the region A, the carrier frequency is changed according to the element temperature so that the carrier frequency decreases with increase of the element temperature at startup of a motor. In the region B and the region C, the carrier frequency is changed according to the number of revolutions of a compression mechanism, so that the carrier frequency decreases with increase of the number of revolutions of the compression mechanism, regardless of the element temperature.

Abstract: Device for fastening at least one PV module (1) to a roof which comprises a trapezoidal metal sheet (2) with a trapezoidal bead (3) with two oblique sides (4, 5) and an upper side (6), wherein the device comprises: exactly one holding plate (10) for fastening to one of the two oblique sides (4, 5), a supporting face (11), a holding-down element (12) for clamping the at least one PV module (1) against the supporting face (11), a threaded shaft (13) which is assigned a central shaft axis (S) and which is provided for actuating the holding-down element (12) in the direction of the supporting face (11), exactly one hinge joint (R, 14, 15) which is assigned a central axis of rotation (R) and by means of which the exactly one holding plate (10) and the threaded shaft (13) are rotatably coupled to one another and which has a joint pin (14) and a pin receptacle (15), wherein the threaded shaft (13) and the joint pin (14) are arranged perpendicular to one another in such a way that a common plane (E) results in which

Abstract: A solar power system is mounted to a solar power componentry support structure suspended above a pre-existing surface by a collective of solar collector suspension base supports. Suspended solar power system row support structure members and suspended solar power system column support structure members may for a solar component position lattice to which a matrix of individual solar power components such as solar panels can be attached. Solar module quick-fasten assemblages may serve also as solar componentry emergency releases and may include loose axis retainers and firm axis fasteners such as dual component, single point operative emergency releases and fasteners. Slide-in retainers and corner slot tabs can be included as well as frame alignment notches. Fulcrum pivot fasteners and slide wedge releases can aid in installation and release. Pre-sealed roof base supports such as semidome base supports can include a sandwiched membrane.

Abstract: A portable power generation device includes a protective case and a power source. The protective case has a lower case portion and an upper case portion, the upper case portion including a plurality of upper case portion segments, wherein the upper case portion is rotatable with respect to the lower case portion between a closed configuration and an open configuration. The power source is sized to fit within the protective case in the closed configuration, rotatable with respect to the lower case portion, and supported by the protective case in the open configuration.

Abstract: An alternation voltage- or current generator comprises a first switch driving output network whose frequency can be tuned. The tuneable network comprises a first Inductor that is coupled with a first capacitor. A second inductor and/or at least a second capacitor and/or at least a series circuit of a third inductor and a third capacitor which is coupled via at a second switch to the network. The second switch is controlled by a controlled delay (PWM) which is synchronized by a sign change of current and/or voltage in the network.

Abstract: A clock signal generating circuit includes: an oscillator having a trimming function of arbitrarily adjusting an oscillation frequency of a first clock signal generated by the oscillator depending on trimming data; and a trimming data modulation part configured to dynamically change a reference trimming data for adjusting the oscillation frequency of the first clock signal to generate modulation trimming data, and output the modulation trimming data, as the trimming data, to the oscillator.

Abstract: A quadrature voltage controlled oscillator includes a first voltage controlled oscillator having a first current source, a first oscillator circuit, a first tuning circuit, and a first resonator tank; a second voltage controlled oscillator having a second current source, a second oscillator circuit, a second tuning circuit, and a second resonator tank. A first biasing circuit is connected between first and second transistors of the first oscillator circuit to bias them in Class-C mode; and a second biasing circuit is connected between third and fourth transistors of the second oscillator circuit to bias them in Class-C mode. The first and second voltage controlled oscillators are electrically coupled by bulk terminals of the first and second transistors coupled with drain terminals of the third and fourth transistors respectively, and bulk terminals of the third and fourth transistors coupled with drain terminals of the first and second transistors respectively.

Abstract: A duplexer, applying in a cable modem, comprises a first mixer, a band-pass filter and a second mixer, in order to filter MoCA interference signal of downstream signals, a series of steps are carried out, which comprising up-conversion, filtering lower and lower frequency. The duplexer use a synthesizer to provide the local oscillator source to the first mixer and the second mixer according to the channel scan signals and use a channel scan controller to provide the channel scan signal of the local oscillator source to the synthesizer.

Abstract: A capacitive trans-impedance amplifier circuit with charge injection compensation is provided. A feedback capacitor is connected between an inverting input port and an output port of an amplifier. A MOS reset switch has source and drain terminals connected between the inverting input and output ports of the amplifier, and a gate terminal controlled by a reset signal. The reset switch is open or inactive during an integration phase, and closed or active to electrically connect the inverting input port and output port of the amplifier during a reset phase. One or more compensation capacitors are provided that are not implemented as gate oxide or MOS capacitors. Each compensation capacitor has a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between two compensation voltage values, and a second port connected to the inverting input port of the amplifier.

Abstract: A radio-frequency amplifier circuit includes first and second FETs cascode-connected to each other. The gate of the first FET is connected to a radio-frequency input terminal, and the drain of the second FET is connected to a radio-frequency output terminal. The source of the first FET is connected to a ground, and the drain of the first FET and the source of the second FET are connected to each other. A drive voltage is applied to the drain of the second FET. A bias setting unit is connected to the gate of the second FET. The bias setting unit sets a second control voltage to be applied to the second FET so that a node voltage between the drain of the first FET and the source of the second FET will be substantially half of the drive voltage.

Abstract: Power supply circuitry, which includes a parallel amplifier and a parallel amplifier power supply, is disclosed. The power supply circuitry operates in either an average power tracking mode or an envelope tracking mode. The parallel amplifier power supply provides a parallel amplifier power supply signal. The parallel amplifier regulates an envelope power supply voltage based on an envelope power supply control signal using the parallel amplifier power supply signal, which provides power for amplification. During the envelope tracking mode, the envelope power supply voltage at least partially tracks an envelope of an RF transmit signal and the parallel amplifier power supply signal at least partially tracks the envelope power supply control signal. During the average power tracking mode, the envelope power supply voltage does not track the envelope of the RF transmit signal.

Abstract: Disclosed is an amplifier circuit capable of achieving high efficiency at back off power while maintaining high output power when an amplifier of a driving stage is saturated in a multistage amplifier in which a plurality of amplifiers are connected in series to each other. In the amplifier circuit, at least two amplifiers including a first amplifier and a second amplifier, the first amplifier preceding the second the first amplifier, are connected in series to each other, the second amplifier changes input impedance according to output power from the first amplifier, and an impedance adjusting unit for adjusting output load impedance of the first amplifier is disposed between the first amplifier and the second amplifier, wherein the impedance adjusting unit optimizes the output load impedance of the first amplifier according to a change of input impedance of the second amplifier.

Abstract: Provided is a fully differential signal system including a first amplification unit including first and second output terminals configured to output an output differential signal generated based on an input differential signal and a common mode feedback signal; a common mode detection unit configured to detect a common mode signal included in the output differential signal; a second amplification unit including a feedback signal output terminal configured to output the common mode feedback signal generated based on the detected common mode signal and a reference signal; a first stabilization unit connected between the first output terminal and the feedback signal output terminal; and a second stabilization unit connected between the second output terminal and the feedback signal output terminal. The fully differential signal system stably operates and an operation performance of the fully differential signal system is improved.

Abstract: A switched mode power supply arranged to provide a switched supply at one terminal of an inductor, another terminal of the inductor being connected to a first input of an error amplifier having a reference signal at a second input, the error amplifier generating a corrected switched supply at an output in dependence on the difference between signals at its first and second inputs, there being provided a feedback path between the output of the error amplifier and the first input of the error amplifier, and further comprising circuitry for sensing a switcher interference current in the feedback path of the error amplifier, and for adjusting the corrected switched supply output to reduce the switcher interference current in the output.

Abstract: An apparatus having an amplifier and a correction circuit is disclosed. The amplifier may be configured to amplify an intermediate signal to generate an output signal. The amplifier is generally a microwave frequency power amplifier. The correction circuit may be configured to (i) generate a control signal based on a plurality of characteristics of the amplifier, and (ii) adjust a plurality of phases of a plurality of pulses in a pulse burst to generate the intermediate signal. The adjusting may be in response to the control signal. The pulse burst is generally received in an input signal. The phases of the pulses as adjusted in the intermediate signal generally cancel a plurality of phase errors induced by the amplifier in the pulses.

Abstract: The present disclosure describes a method and system for linearizing an amplifier using transistor-level dynamic feedback. The method and system enables nonlinear amplifiers to exhibit linear performance using one or more of gain control elements and phase shifters in the feedback path. The disclosed method and system may also allow amplifiers to act as a pre-distorter or a frequency/gain programmable amplifier.

Abstract: A distortion compensation device for correcting balance between a first branch and a second branch, includes: an adjustment unit that is arranged in an input stage of a first nonlinear amplifier on the first branch and outputs a signal obtained by adjusting a phase and an amplitude of a first branch signal by using a balance correction amount to the first nonlinear amplifier; a first calculation unit that calculates a first inverse distortion characteristic of an entire outphasing amplifier based on an input signal and a combined signal; a second calculation unit that calculates a replica signal of the first branch signal based on the calculated first inverse distortion characteristic, a second branch signal, and the combined signal; and a third calculation unit that calculates the balance correction amount based on the calculated replica signal of the first branch signal and the signal output from the adjustment unit.

Abstract: A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input.

Abstract: In accordance with an embodiment, a circuit includes a first signal path coupled between an input port and an output port, and a second coupled between the input port and the output port in parallel with the first signal path. The first signal path includes a low noise amplifier (LNA) having an input node coupled to the input port, and the second signal path includes a switch coupled between the input port and the output port.

Abstract: A power amplification apparatus generates a code for controlling the number of class D power amplifiers that are in operation among a plurality of class D power amplifiers, changes the duty ratio of a carrier wave signal in accordance with output voltage, and amplifies a transmission signal. A code for decreasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is increased, while a code for increasing the number of class D power amplifiers in operation is generated when the duty ratio of the carrier wave signal is decreased.

Abstract: A multi-mode power amplifier comprises a regulation control circuit, an AMP 1, a demultiplexer, an AMP 2, a low power output matching circuit, a medium power output matching circuit, and a high power output matching circuit. In low power mode, the regulation control circuit controls AMP 1 to work in a first power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to the low power output matching circuit. In the medium power mode, the regulation control circuit controls AMP 1 to work in a second power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to the medium power output matching circuit. In high power mode, the regulation control circuit controls AMP 1 to work in the second power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to AMP 2.

Abstract: An audio amplifier is disclosed. The audio amplifier for driving an electroacoustic transducer includes an H bridge circuit including a 1D-class amplifier connected to a (+) electrode terminal and a 2D-class amplifier connected to a (?) electrode terminal of the electroacoustic transducer; a pulse width modulator configured to receive an audio signal, generate a first and second pulse signal for each driving the 1D-class and the 2D-class amplifier, and adjust a phase difference between the first and the second pulse signal; a first driver driving the 1D-class amplifier depending on the first pulse signal; a second driver driving the 2D-class amplifier depending on the second pulse signal; a level detector detecting a level of the audio signal; a phase adjuster configured to set a phase difference between the first pulse signal and the second pulse signal of the pulse width modulator based on a detection result from the level detector.

Abstract: This disclosure relates to real-time calibration of a tunable matching network that matches the dynamic impedance of an antenna in a radio frequency receiver system. The radio frequency receiver system includes two non-linear equations that may be solved to determine the reflection coefficient of the antenna. Control system that calculates, in real time, a value of an input impedance of the antenna to match a load in a receiver system, wherein said impedance is calculated directly using a closed-form solution. The reflection coefficient of the antenna may be used to determine the input impedance of the antenna. The elements of the matching circuit are then adjusted to match the input impedance of the antenna.

Abstract: An apparatus includes a first amplification stage configured to amplify a first carrier signal and a second amplification stage configured to amplify a second carrier signal. The first amplification stage is direct-current (DC) coupled to the second amplification stage. First circuitry is coupled to the first amplification stage and configured to control a first gain of the first amplification stage. The first circuitry includes a first gain control transistor configured to selectively divert a first bleed current from a first output of the first amplification stage. Second circuitry is coupled to the second amplification stage and configured to control a second gain of the second amplification stage independently of the first gain. The second circuitry includes a second gain control transistor configured to selectively divert a second bleed current from a second output of the second amplification stage.

Abstract: A system and method of frequency conversion or demodulation can be used in wireless environments. A demodulator or frequency converter can include a forward mixer path including an amplifier, a first mixer, a first input, a second input, and a first output. The forward mixer path can be configured to receive a first radio frequency signal at the first input, receive an oscillator signal at the second input and provide a baseband signal. The first mixer can configured to provide a gain.

Abstract: The present invention relates to a power detection circuit and an RF signal amplification circuit having the same. According to an embodiment of the present invention, a power detection circuit including a coupling unit adjacent to an RF matching inductor to extract induced power; a rectification unit for rectifying the signal output from the coupling unit to output the rectified signal; a slope adjustment unit connected between an output terminal of the rectification unit and a ground and adjusting a voltage slope for power detection by changing the output signal of the output terminal of the rectification unit according to changes in internal impedance; and a smoothing unit for receiving the output signal of the output terminal of the rectification unit to smooth the received signal into a DC voltage for power detection using the voltage slope is provided. Further, an RF signal amplification circuit having the same is provided.

Abstract: A position detecting system detects and responds to the movement of a target through a sensing domain area of a plane. The movement causes the amount of the target that lies within a sensing domain area to change. A portion of the target always lies within at least one of the sensing domain areas of the plane.

Abstract: A method for manufacturing a piezoelectric vibration device wherein a substrate is prepared, and a piezoelectric resonator element is mounted on the substrate. Before or after a packaging member is joined to the substrate, the piezoelectric resonator element is exposed to an environment at a higher temperature than ambient temperature and a higher humidity than ambient humidity, and then an electrical property is measured to detect attachment of dust and/or foreign matter according to a variation of the electrical property.

Abstract: In an electronic component, first through n-th LC parallel resonators respectively include first through n-th inductors disposed in a device body such that they are sequentially arranged in a first direction in an order from the first inductor to the n-th inductor. The first and the n-th inductors are wound around respective winding axes extending along the first direction. At least one predetermined inductor among the second through the (n?1)-th inductors is wound around a winding axis extending in a second direction which is perpendicular or substantially perpendicular to the first direction. A center of the predetermined inductor in the second direction is positioned toward one side of the second direction with respect to the winding axes of the first and the n-th inductors, as viewed from a plane of the device body in a third direction which is perpendicular or substantially perpendicular to the first and second directions.

Abstract: A filter device includes a single terminal and first and second balanced terminals. A balanced filter is connected between the single terminal and the first and second balanced terminals. The filter device includes a compensation circuit including at least one of a first compensation circuit portion connected between the single terminal and the first balanced terminal and a second compensation circuit portion connected between the single terminal and the second balanced terminal. The compensation circuit includes a resonant circuit that increases attenuation in a specified frequency band within a stop band of the balanced filter, compared with a case in which the compensation circuit is not connected.

Abstract: A microelectromechanical systems device package includes a MEMS device mounted in flip-chip technology on a substrate. A film of non-evaporable getter material is disposed between the substrate and the MEMS device. A cover structure encapsulates the MEMS device. This invention further provides a method for manufacturing the microelectromechanical systems device package.

Abstract: An acoustic resonator device includes a composite first electrode on a substrate, a piezoelectric layer on the composite electrode, and a second electrode on the piezoelectric layer. The first electrode includes a buried temperature compensating layer having a positive temperature coefficient. The piezoelectric layer has a negative temperature coefficient, and thus the positive temperature coefficient of the temperature compensating layer offsets at least a portion of the negative temperature coefficient of the piezoelectric layer.

Abstract: A complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative IF (?IF) for channel selection and image rejection, offering image rejection and channel selection concurrently.

Abstract: A low-pass filter comprising: a filter input terminal; a filter output terminal; a filter FET configured to provide a resistance between the filter input terminal and the filter output terminal; a filter capacitor connected between the filter output terminal and a reference terminal; a bias FET configured to provide a bias voltage to the filter FET; a buffer connected between the filter input terminal and the bias FET, the buffer configured to source a bias current for the bias FET; and an offset voltage source configured to contribute to the bias voltage provided to the filter FET.

Abstract: A method and system of compensating for phase error. A phase error compensation circuit is configured to generate a phase-corrected quadrature Q output signal and a corresponding phase-corrected in-phase I output signal, the circuit includes a first transconductance circuit configured to convert a voltage signal related to an I input voltage signal to an I current signal. A second transconductance circuit is configured to convert a voltage signal related to a Q input signal to a Q current signal. A first multiplier circuit is configured to multiply the Q current signal times a Q scaling constant. A second multiplier circuit is configured to multiply the I current signal times an I scaling constant. An I summer sums the I current signal with the scaled Q signal. A Q summer sums the Q current signal with the scaled I signal.

Abstract: Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

Abstract: A clock system including a ring oscillator having a plurality of cascaded inverters, each of the cascaded inverters having a pair of inputs coupled to outputs of a respectively adjacent inverter stage and having a pair of outputs coupled to inputs of another respectively adjacent inverter stage, each inverter stage having a common mode control circuit provided therein, and a feedback controller adapted to transmit a control signal to the common mode control circuit of at least one of the inverters.

Abstract: A novel PLL is provided. An oscillator circuit includes first to n-th inverters, and first and second circuits. A first terminal of each of the first and second circuits is electrically connected to an output terminal of the i-th inverter. A second terminal of each of the first and second circuits is electrically connected to an input terminal of the (i+1)-th inverter. The first circuit has functions of storing first data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the first data. The second circuit has functions of storing second data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the second data.

Abstract: A data output device may include a driving control, a voltage supply unit, and an output driving unit. The driving control unit outputs a pull-up control signal and a pull-down control signal in response to a logic value of data when an output enable signal is activated. The voltage supply unit generates a driving voltage lower than a supply voltage. The output driving unit is driven in response to the driving voltage, and controls an amplitude and a slew rate of a voltage supplied to a global line according to the pull-up control signal and the pull-down control signal.

Abstract: A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.

Abstract: A clamping circuit clamps a serial data signal between a first high voltage level and a first low voltage level to yield a clamped serial data signal. A first comparator circuit compares the clamped serial data signal to a second high voltage level less than the first high voltage level to yield a high output equal to one just when a voltage of the clamped serial data signal is greater than the second high voltage level. A second comparator circuit compares the clamped serial data signal to second low voltage level greater than the first low voltage level to yield a low output equal to one just when the voltage of the clamped serial data signal is greater than the second low voltage level. An edge circuit detects an edge of the serial data signal from the high output and the low output.

Abstract: An overshoot compensation circuit for an input signal, having a slew rate detection circuit configured to detect a slew rate of the input signal; a run time circuit configured to initialize a predetermined run time when an absolute value of the slew rate of the input signal is greater than or equal to a predetermined threshold; and a low pass filter configured to decrease the slew rate of the input signal only during the predetermined run time.

Abstract: A multi-phase clock circuit includes: a phase tuning circuit configured to receive a primitive N-phase clock including N primitive clocks of the same period but distinct phases and output a calibrated N-phase clock including N calibrated clocks in accordance with a first tuning signal, where N is integer greater than one; a clock multiplexing circuit configured to receive the N calibrated clocks and output a first output clock and a second output clock in accordance with a multiplexing control signal; a time-to-digital converter configured to receive the first output clock and the second output clock and output a digital code; and a calibration controller configured to receive the digital code and output the first tuning signal in accordance with a mode select signal.

Abstract: Delay circuits may be controlled by apparatuses and methods during an idle state to reduce degradation of an electrical characteristic. An example apparatus includes a delay line circuit including a plurality of delay stages, and further includes a delay line control circuit coupled to the delay line circuit. The delay line control circuit is configured to enable delay stages of the plurality of delay stages, and is further configured to control enabled delay stages of the plurality of delay stages to provide a respective output clock signal having a high logic level during an idle state.

Abstract: A semiconductor device capable of simply performing power gating and a driving method thereof are provided. Power gating is started passively (automatically in the case of satisfying predetermined conditions). Specifically, the semiconductor device includes a transistor for selecting whether a power source voltage is supplied or not to a functional circuit. The power gating is started by turning off the transistor in the case where a voltage between a source and a drain is less than or equal to a predetermined voltage. Therefore, complicated operation is not needed at the time of starting power gating. Specifically, it is possible to start power gating without a process for predicting the timing at which an arithmetic operation performed in the functional circuit is terminated. As a result, it is possible to start power gating easily.