Abstract: In some embodiments, a circuit may include a plurality of peripherals and a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to reset a count in response to detecting the activity. In some embodiments, the peripheral watchdog timer circuit may be configured to generate an alert signal when the count exceeds a threshold count before detecting the activity. In some embodiments, the peripheral watchdog timer circuit is configured to initiate a reset operation when the alert is not serviced within a period of time.

Abstract: An approach is provided for personalizing an error message for a user. Corrective actions performed by the user are monitored. The corrective actions include the user visiting online forums. The corrective actions cause a resolution of an instance of an error condition described in the error message and which specifies an error in an operation of a software application. Based on the monitored corrective actions, sources of information accessed by the user to resolve the error condition instance are determined. The sources include online forums visited by the user. After resolution of the error condition instance, another instance of the same error condition is detected, and in response, the error message is augmented with a summary of the sources including the online forums and/or hyperlinks that access the sources including the online forums. The augmented error message is presented to the user.

Abstract: Systems and methods for providing service and to computing devices. In some embodiments, an Information Handling System (IHS) includes a Basic I/O System (BIOS) and a memory coupled to the BIOS, the memory including program instructions stored thereon that, upon execution by the IHS, cause the IHS to: determine that the IHS is operating in a degraded state; and initiate one or more support, diagnostics, or remediation operations in response to the determination.

Abstract: The disclosure relates to cloud-based mobile discovery networks. For example, a mobile discovery network may include a network responsive to successful watermark detection or fingerprint extraction. One claim recites a cloud-based computing resolver cell in a mobile discovery network, the mobile discovery network having a cloud-based traffic router for forwarding requests from remote devices. The resolver cell includes: memory for storing response information; one or more processors programmed for: combine results from a third party inquiry, a traffic router health check, and an internal component or processing check within a certain time period determine whether to enter into a stabilization mode; entering the stabilization mode when a determination indicates stabilization is warranted; verifying, for a predetermined period, the status of the resolver cell before exiting the stabilization mode. Of course other claims and combinations are provided as well.

Abstract: Provided are a method, a system, and a computer program product in which a storage controller determines one or more resources that are impacted by an error. A cleanup of tasks associated with the one or more resources that are impacted by the error is performed, to recover from the error, wherein host input/output (I/O) operations continue to be processed, and wherein tasks associated with other resources continue to execute.

Abstract: Storage infrastructures and methods that generate hash values based on error correction codes. A system is provided that includes: a code retrieval system implemented on a host having logic for issuing a redundancy read command to a storage system to retrieve a redundancy code for an identified data block; and a hashing system implemented on the host for hashing the redundancy code to generate a hash value based on the redundancy code. A storage system is also provided that includes: a memory for storing data blocks and associated redundancy codes; and a controller having: an input/output for receiving a hash value read command for a specified data block from a host and returning a hash value; a decoding system that extracts a redundancy code associated with the specified data block; and an in-memory hashing system for computing a hash operation on the redundancy code.

Abstract: A method is provided for storing data. The method implements an error-correction code defining a set of variables linked by constraints, each variable being associated with source data and/or redundancy data. The method implements the following steps: determining variables forming at least one stopping set of said code, determining a scheme for allocating said variables, allocating a distinct storage carrier to each variable forming a stopping set, distributing said variables, or data associated with said variables, to said storage carriers according to said allocation scheme.

Abstract: Techniques are disclosed for generating codes for representation of data in memory devices that may avoid the block erasure operation in changing data values. Data values comprising binary digits (bits) can be encoded and decoded using the generated codes, referred to as codewords, such that the codewords may comprise a block erasure-avoiding code, in which the binary digits of a data message m can be encoded such that the encoded data message can be stored into multiple memory cells of a data device and, once a memory cell value is changed from a first logic value to a second logic value, the value of the memory cell may remain at the second logic value, regardless of subsequently received messages, until a block erasure operation on the memory cell.

Abstract: On the basis of data addresses indicative of write bit positions of each of the write data pieces in each of blocks, write page addresses indicative of pages having each of the write data pieces written thereto in each of the blocks are detected. At least one write data piece is incorporated into each of the page data pieces indicated by the write page addresses among k page data pieces corresponding to the k pages, the page data pieces having the write data pieces incorporated therein are used as page data pieces, and an error-correction encoding process is applied to each of the write page data pieces to obtain encoded write data pieces. Then, a voltage based on the encoded write data pieces is applied to each of the memory cells belonging to the pages indicated by the write page addresses.

Abstract: There is provided a distributed object storage system that includes several performance optimizations with respect to efficiently storing data objects when coping with a desired concurrent failure tolerance of concurrent failures of storage elements which is greater than two and with respect to optimizing encoding/decoding overhead and the number of input and output operations at the level of the storage elements.

Abstract: A computing core includes memory and a memory controller. The memory is partitioned into a user section and a kernel section. The user section is divided into a first set of pillars and the kernel section is divided into a second set of pillars. The memory controller is operable to dispersed storage error encode a data segment of user data into a set of encoded user data slices. The memory controller is further operable to store the set of encoded user data slices in the first set of pillars of the user section. The memory controller is further operable to dispersed storage error encode a data segment of system data into a set of encoded system data slices. The memory controller is further operable to store the set of encoded system data slices in the second set of pillars of the kernel section.

Abstract: Technologies are described for systems, devices and methods effective to decode data read from a memory. Coded data may be stored in a buffer. A parity check syndrome vector may be calculated by a bit flip module, based on the coded data and based on a parity matrix. The parity check syndrome vector may include unsatisfied bits. The parity check syndrome vector may be stored in the buffer. The bit flip module may calculate a speculated bit flip threshold based on a feature of the parity matrix. The bit flip module may determine, based on the parity check syndrome vector, a number of unsatisfied parity checks participated in by a particular bit of the coded data. The bit flip module may flip the particular bit in response to the number of unsatisfied parity checks for the particular bit being greater than or equal to the speculated bit flip threshold.

Abstract: A configuration is generated for a software that is to be deployed for providing high service availability to satisfy configuration requirements. One or more configuration patterns are identified, each of which specifies a set of attribute values and an actual recovery action for a failed component as a configuration option of the software. The unchangeable attribute values of the software are matched with the configuration patterns to obtain a matching configuration pattern, whose actual recovery action incurs a smallest component failure recovery impact zone. The matching configuration pattern is selected as at least a portion of the configuration of the software. Then the changeable attribute values of the software are set to the corresponding attribute values of the matching configuration pattern to satisfy the configuration requirements.

Abstract: A method of optimizing the number and type of database backups to achieve a given RTO is provided and may include receiving a RTO and receiving a heuristic for determining an amount of unencumbered processing time. A type of next backup, (i.e., a next backup), is determined wherein the type of next backup is an incremental backup when the sum of the heuristic, and the times to: restore the latest full backup, restore zero or more incremental backups, complete a current incremental backup, and perform a full backup is less than the received RTO, else the type of the next backup is a full backup. A time to schedule the next backup is scheduled based on the received RTO being a total of an amount of time to: complete the type of next backup; rollforward zero or more transaction log records; and to restore at least one backup.

Abstract: Described are methods, systems and computer readable media for the importation, presentation, and persistent storage of data.

Abstract: Provided are a computer program product, system, and method for recovering a volume table and data sets from a volume. Content from a backup volume table comprising a valid backup of a volume table from backup of the volume is processed to generate a recovery volume table for a recovery volume. The data sets in the volume are processed to determine whether they are valid. The valid data sets are moved to the recovery volume. A data recovery operation is initiated for the data sets determined not to be valid.

Abstract: A suite of network-based services, such as the services corresponding to the server application distributed by Microsoft® SharePoint™, may be provided to users with high availability. The suite of network-based services may include browser-based collaboration functions, process management functions, index and search functions, document-management functions, help and help search functions, and/or other functions. A plurality of computing devices functioning as servers may be backed up by a single computing device.

Abstract: Embodiments include obtaining at least one system metric of a distributed storage system, generating one or more recovery parameters based on the at least one system metric, identifying at least one policy associated with data stored in a storage node of a plurality of storage nodes in the distributed storage system, and generating a recovery plan for the data based on the one or more recovery parameters and the at least one policy. In more specific embodiments, the recovery plan includes a recovery order for recovering the data. Further embodiments include initiating a recovery process to copy replicas of the data from a second storage node to a new storage node, wherein the replicas of the data are copied according to the recovery order indicated in the recovery plan.

Abstract: Various technologies and techniques are disclosed for providing stepping and state viewing in a debugger application. A start and end breakpoint are assigned. Source code execution begins, and upon reaching the start breakpoint, a logging feature begins storing one or more values that may be impacted upon execution of code between the start breakpoint and an end breakpoint. More lines of source code are executed until the end breakpoint is reached. When the end breakpoint is reached, the debugger is put into break mode. While in break mode, a playback feature is provided to allow a user to play back a path of execution that occurred between the start breakpoint and the end breakpoint. The playback feature uses at least some of the values that were stored with the logging feature to show how each referenced variable changed in value.

Abstract: Systems and methods disclosed herein may include real-time analysis of application programming interfaces (APIs). The method may include detecting that the programming code input is associated with at least a portion of an application programming interface (API). At least one coding error associated with the API may be detected based on static analysis of the code. The static analysis may include receiving an indication of a browser version, and comparing the received code with programming code for the API verified for the browser version, to detect the at least one coding error. Information identifying at least a first remediation action for correcting the at least one coding error may be received based at least in part on the at least one browser version. The at least a first remediation action may be provided for display to a user of the computing device.

Abstract: To identify a source of a memory leak in an application, a pattern of objects is identified in an object hierarchy of a heap dump, the pattern including an indication of the memory leak. The pattern is matched with a metadata of the application. A static entry in the metadata describes a relationship between a component of the application and an object of a class used in the component. A flow entry in the metadata describes a relationship between a pattern of instantiation of a set of objects corresponding to a set of classes and an operation performed using the application. When the pattern matches the flow entry in the flow section of the metadata, a conclusion is drawn that the memory leak is caused in the operation identified in the flow entry. A portion of a code that participates in the operation is selected for modification.

Abstract: A model checking device for a distributed-environment-model according to the present invention, includes: a distributed-environment-model search unit that adopts a first state as start point when obtaining information indicating a distributed-environment-model, searches the state attained by the distributed-environment-model by executing straight line movements for moving from the first state to a second state which is an end position, and determines whether the searched state satisfies a predetermined property; a searched state management unit that stores the searched state in the past; a searched-transition-history management unit that stores an order of the transitions of the straight line movements in the past; a searched state transition association information management unit that stores the transition when moving to another state in the past search in such a manner that the transition is associated with each of the searched states.

Abstract: A method of modeling elements in an automated test of a software application is disclosed. An attribute is created for a set of user-interface elements of a selected species. The attribute defines interactions for the selected species. The user-interface elements are reduced to a primitive type. An application program interface can be used to apply the attribute to the software application.

Abstract: A method is disclosed of generating program analysis data for analysing the operation of a computer program. The method includes running a first instrumented version of machine code representing the program, wherein said running defines a reference execution of said program, capturing a log of non-deterministic events during reference execution to reproduce states of a processor and memory during the re-running, generating a second instrumented version of machine code to replay execution of said machine code representing the program and to capture and store program state information, wherein said program state information comprises one or both of one or more values of registers of said processor and one or more values of memory locations used by said program, running said instrumented machine code whilst reproducing said non-deterministic events during said running to reproduce said reference execution; and capturing said program state information whilst reproducing said reference execution.

Abstract: A method translates the native machine codes that do not allocate memory for metadata, do not store, and do not propagate metadata by augmenting them with extra instructions to allocate memory for metadata, to store, and to populate metadata such that metadata are readily available at run time for checking programming errors.

Abstract: Example embodiments relate to generalized snapshots based on multiple partial snapshots. An example method may include accessing multiple partial snapshots, each from a different client. The method may include creating a generalized snapshot from the multiple partial snapshots. The generalized snapshot includes multiple target pixels, and the color of each of the multiple target pixels may be determined by considering colors of multiple source pixels, each from a different partial snapshot.

Abstract: A method to determine valid input sequences for an unknown binary program is provided. The method includes obtaining multiple input sequences, which each include two or more different inputs, for an unknown binary program. The inputs for the input sequences may be valid inputs for the unknown binary program. The method may further include executing an instrumented version of the unknown binary program separately for each input sequence. For each execution of the instrumented version of the unknown binary program, a set of execution traces may be generated by recording execution traces generated by the execution of the instrumented version of the unknown binary program. The method may further include comparing the sets of execution traces and determining which of the input sequences the unknown binary program accepts as valid based on the comparison of the sets of execution traces.

Abstract: Mechanisms for recreating a first inconsistency in storage system metadata encountered by an installation module during a software installation process on a first computing device are provided. A test computing device accesses on a remote storage device inconsistent storage system metadata associated with the first computing device. The inconsistent storage system metadata includes a plurality of storage system metadata segments, location information that identifies corresponding locations of the respective storage system metadata segments on at least one storage device of the first computing device, and length information that identifies corresponding lengths of the respective storage system metadata segments. For each respective storage system metadata segment of the plurality of storage system metadata segments, the respective storage system metadata segment is stored at the corresponding location on a first test storage device of a test computing device.

Abstract: A cache management method and apparatus are disclosed, in order to improve cache resource utilization, where the method includes receiving an access request, determining data that is to be accessed and that needs to be accessed according to the access request, determining a strength level of spatial locality of the data to be accessed, and allocating, according to the strength level of the spatial locality of the data to be accessed, a cache subunit corresponding to the level to the data to be accessed, where the method is applicable to the communications field, and may used to implement cache management.

Abstract: Systems and methods for utilizing wear leveling windows with non-volatile memory systems are disclosed. In one implementation, a memory management module of a non-volatile memory system compares a metric reflecting wear of a memory block to a wear leveling window and determines whether a wear leveling indicator associated with the memory block restricts performing a wear leveling operation on the memory block. The memory management module performs a wear leveling operation on the memory block in response to determining that the metric reflecting wear of the memory block falls outside the wear leveling window and determining that the wear leveling indicator does not restrict performing a wear leveling operation on the memory block. After performing the wear leveling operation, the memory management module places the memory block on a free block list.

Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for determining a pool of blocks from the plurality of blocks as garbage collection (GC) victim block candidates based on a number of valid pages left in each of the plurality of blocks, and selecting a block from the pool of blocks having a minimum number of valid pages as a victim block for garbage collection.

Abstract: Described are methods, systems and computer readable media for distributed and optimized garbage collection of remote and exported object handle links to update propagation graph nodes.

Abstract: An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.

Abstract: Described are methods, systems and computer readable media for computer data distribution architecture.

Abstract: A grace period detection technique for a preemptible read-copy update (RCU) implementation that uses a combining tree for quiescent state tracking. When a leaf level bitmask indicating online/offline CPUs is fully cleared due to all of its assigned CPUs going offline as a result of hotplugging operations, the bitmask state is not immediately propagated to the root level of the combining tree as in prior art RCU implementations. Instead, propagation is deferred until all tasks are removed from an associated leaf level task list tracking tasks that were preempted inside an RCU read-side critical section. Deferring bitmask propagation obviates the need to migrate the task list to the combining tree root level in order to prevent premature grace period termination. The task list can remain at the leaf level. In this way, CPU hotplugging is accommodated while avoiding excessive degradation of real-time latency stemming from the now-eliminated task list migration.

Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.

Abstract: A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Abstract: A technique for managing data storage in a data storage system is disclosed. Data blocks are written to a data storage system cache, pluralities of the data blocks being organized into cache macro blocks, the IO cache macro blocks having a fixed size. Access requests for the data blocks are processed, wherein processing includes generating block access statics. Using access statics, data blocks stored in the cache macroblocks having block a access times that overlap are identified. Data blocks identified as having overlapping access times are rearranged into one or more overlap cache macroblocks.

Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

Abstract: The present disclosure provides a cache cleaning method, a cache cleaning apparatus and a client, which improves a cache cleaning efficiency in a client and improves a user experience effectively. The method includes: detecting an amount of used caches in a mobile terminal; if the amount of used caches is larger than a preset threshold, sending a cache application request to an operating system of the mobile terminal so as to trigger a preset cache release rule in the operating system; and after the operating system releases corresponding caches according to the preset cache release rule, sending a cache release request to the operating system such that the operating system releases caches allocated for the cache application request according to the cache release request. The present disclosure may be used in a cache management technique of a mobile terminal.

Abstract: A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource is allocated; and a cache state management mechanism that manages a cache state of the virtual computer. The virtualization mechanism provides a first virtual computer and a second virtual computer. The cache state management mechanism manages the cache state of each of the first virtual computer and the second virtual computer. When the cache state management mechanism detects transition of the cache state in a state where a memory area allocated to a cache of the first virtual computer and a memory area allocated to a cache of the second virtual computer include duplicated areas storing same data, the virtualization mechanism releases the duplicated area in one of the first virtual computer and the second virtual computer.

Abstract: A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache.

Abstract: A processor including an extended page table (EPT) translation mechanism that is enabled for virtualization, and a load EPT instruction. When executed by the processor, the load EPT instruction directly invokes the EPT translation mechanism to directly convert a provided guest physical address into a corresponding true physical address. The EPT translation mechanism may include an EPT paging structure and an EPT tablewalk engine. The EPT paging structure is generated and stored in an external system memory when the EPT translation mechanism is enabled. The EPT tablewalk engine is configured to access the EPT paging structure for the physical address conversion. The EPT tablewalk engine may perform relevant checks to trigger EPT misconfigurations and EPT violations during execution of the load EPT instruction.

Abstract: The present invention provides a storage device adopting a semiconductor device as a storage media having a nonvolatile property and must be erased for writing data, wherein the device divides and manages a logical storage space provided to a higher level device in logical page units, and manages a virtual address space which is a linear address space to which multiple physical blocks of the semiconductor device are mapped. The storage device uses a page mapping table managing a correspondence between a logical page and an address in the virtual address space, and a virtual address configuration information managing a correspondence between an area in the virtual address space and a physical block, in order to manage the correspondence between the respective logical pages and storage areas of the semiconductor device.

Abstract: A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (OTP) memory of a device. Furthermore, a second virtual address of the virtual memory may be mapped to a second physical address of a static memory of the device. The virtual memory that is mapped to the OTP memory and the static memory may be provided for accessing of the data of the OTP memory of the device.

Abstract: A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.

Abstract: Disclosed herein are techniques for maintaining an indirection manager for a mass storage device. According to some embodiments, the indirection manager is configured to implement different algorithms that orchestrate a manner in which data is read from and written into memory sectors when handling I/O requests output by a computing device that is communicatively coupled to the mass storage device. Specifically, the algorithms utilize a mapping table that is limited to two levels of hierarchy: a first tier and a second tier, which constrains the overall size and complexity of the mapping table and can increase performance. The embodiments also set forth a memory manager that is configured to work in conjunction with the indirection manager to provide a mechanism for efficiently allocating and de-allocating variably-sized groups of sectors.