Patents Issued in January 17, 2017
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Patent number: 9547561Abstract: A computer readable medium and method for providing checkpointing to Windows application groups. The checkpointing may be triggered asynchronously using Asynchronous Procedure Calls. The computer readable medium includes computer-executable instructions for execution by a processing system. The computer-executable instructions may be for reviewing one or more command line arguments to determine whether to start at least one of the application groups, and when determining to start the at least one of the application groups, creating a process table in a shared memory to store information about each process of the at least one of the application groups. Further, the instructions may be for registering with a kernel module to create an application group barrier, creating a named pipe for applications of the application group to register and unregister, triggering a checkpoint thread to initiate an application group checkpoint; and launching an initial application of the applications of the application group.Type: GrantFiled: November 25, 2015Date of Patent: January 17, 2017Assignee: Open Invention Network LLCInventors: Keith Richard Backensto, Allan Havemose
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Patent number: 9547562Abstract: A boot restore system and associated processes for rapidly restoring virtual machine images are described. The boot restore system can boot a virtual machine from a set of one or more backup files in a backup repository. The boot restore system can make the backup set available for use by the virtual machine immediately or otherwise rapidly. Thus, users may not have to wait for an actual virtual disk image to be copied to a separate file system before accessing the restored backup set. While a user is accessing the virtual machine, a live migration process can migrate the backup set to a target file system, without any disruption or substantial disruption in use of the running virtual machine.Type: GrantFiled: October 12, 2010Date of Patent: January 17, 2017Assignee: Dell Software Inc.Inventors: David Allen Feathergill, Jason Mattox
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Patent number: 9547563Abstract: A recovery system and method for performing site recovery utilizes recovery-specific metadata and files of protected clients at a primary site to recreate the protected clients at a secondary site. The recovery-specific metadata is collected from at least one component at the primary site, and stored with the files of protected clients at the primary site. The recovery-specific metadata and the files of the protected clients are replicated to the secondary site so that the protected clients can be recreated at the secondary site using the replicated information.Type: GrantFiled: June 30, 2014Date of Patent: January 17, 2017Assignee: VMware, Inc.Inventors: Ilia Langouev, Ryan D. Gallagher, Aleksey Pershin, Ruopeng Ye
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Patent number: 9547564Abstract: Functionality is disclosed for automated deployment of applications. A network-based deployment service provides functionality for deploying software components to physical or virtual hosts in a service provider network and/or to hosts in other types of networks external to the service provider network. A user of the deployment service creates an application revision that includes deployable content and an application specification defining how the application is to be deployed and one or more lifecycle events. The application revision is then uploaded to a storage service, source code repository, or other location. A deployment configuration is also created that defines the location of the application revision, a deployment group, and a schedule for the deployment. A deployment agent executing on hosts in the deployment group obtains the application revision from the specified location, deploys the deployable content according to the schedule, and performs the lifecycle events.Type: GrantFiled: November 10, 2014Date of Patent: January 17, 2017Assignee: Amazon Technologies, Inc.Inventors: Andrew Thomas Troutman, Suryanarayanan Balasubramanian, Joshua William McFarlane
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Patent number: 9547565Abstract: Embodiments of the Message Retransmission Mechanism Apparatuses, Methods and Systems (“MRM”) transform application requests for message journals via MRM components into expedited access to segmented message streams. In one implementation, the MRM may obtain message journal of messages written by applications during system operations and divide up the message obtained from the complete message journal into message segments. In some implementations, the MRM may provide recovering applications access to said message segments for expedited message consumption.Type: GrantFiled: March 11, 2015Date of Patent: January 17, 2017Assignee: IEX Group, Inc.Inventors: James Michael Cape, Robert Park, Allen Zhang, Zoran Perkov, Lieting Yu, Prerak Pukhraj Sanghvi, Beau Tateyama, Constantine Sokoloff, Eric Quinlan
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Patent number: 9547566Abstract: A storage control apparatus includes an uncorrectable error generation flag management section configured to manage an uncorrectable error generation flag in a memory configured to store a first error detection and correction code corresponding to a first data unit, and a second error detection and correction code corresponding to a second data unit including first data units, the uncorrectable error generation flag representing whether or not an uncorrectable error with the first code has occurred, the uncorrectable error generation flag being managed for each second data unit, a controller configured to prohibit access to the second data unit representing that the uncorrectable error has occurred when a command for the access with data change is issued, and a correction section configured to use the second code to correct the second data unit when the second data unit representing that the uncorrectable error has occurred is restored.Type: GrantFiled: September 16, 2014Date of Patent: January 17, 2017Assignee: Sony CorporationInventor: Kenichi Nakanishi
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Patent number: 9547567Abstract: An information processing system includes a first control unit including a first memory configured to store first software, and a first controller configured to perform processing based on the first software and to update the first software in a case where an instruction to update the first software is received, and a second control unit configured to be coupled to the first control unit, the second control unit including a second memory configured to store second software that is the same as the first software, a second controller configured to perform processing based on the second software, and a first power supply circuit configured to start power supply to the second controller in a case where a failure in the first control unit is detected.Type: GrantFiled: September 24, 2013Date of Patent: January 17, 2017Assignee: FUJITSU LIMITEDInventor: Ryota Tanaka
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Patent number: 9547568Abstract: A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first slave unit during a first transfer period while a second signal is transferred between a second master unit and a second slave unit during a second transfer period. The second transfer period overlaps at least a part of the first transfer period. When the first transfer period is longer than a third transfer period, first combination information indicating the combination of the first master unit and first slave unit is stored in a storage unit, in conjunction with second combination information indicating the combination of the second master unit and second slave unit.Type: GrantFiled: December 19, 2013Date of Patent: January 17, 2017Assignee: SOCIONEXT INC.Inventor: Taku Kawamura
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Patent number: 9547569Abstract: To provide a vehicle electronic control unit including a first microcomputer (2, 3) and a second microcomputer (3, 2) capable of transmitting and receiving signals to and from the first microcomputer. One of the first microcomputer and the second microcomputer outputs a PWM signal to the other microcomputer (3, 2). The other microcomputer detects an on-time of the PWM signal, performs a self diagnosis according to the detected on-time, and outputs a self diagnosis result to the one microcomputer. The one microcomputer diagnoses the other microcomputer based on the self diagnosis result.Type: GrantFiled: September 14, 2010Date of Patent: January 17, 2017Assignee: KEIHIN CORPORATIONInventor: Yusuke Ikegami
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Patent number: 9547570Abstract: The devices, systems, and methods test network connectivity, where the physical network is used to provide one or more service chains connecting service appliances, including firewalls, intrusion detection systems, load balancers, network address translators, web servers, and so on. A service chain may involve multiple routing paths. The devices, systems, and methods test network connectivity test network connectivity by injecting customized echo request packets on each routing path and collecting customized echo reply packets in response. The customized echo reply packets are processed and aggregated to isolate network connectivity problems.Type: GrantFiled: January 29, 2015Date of Patent: January 17, 2017Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xingjun Chu, Yinfeng Henry Yu, Guoli Yin, Yapeng Wu, Tao Wan, Peter Ashwood-Smith, Khaldoon Al-Zoubi
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Patent number: 9547571Abstract: A storage device with a memory may include memory block health monitoring and behavior tracking. Each memory block may be analyzed based on one or more dummy wordlines within the block may not be accessible for normal data storage. The dummy wordlines may be programmed with a known data pattern that can be tracked and analyzed for potential errors, which may be used as representation of the health of the memory block. Adjustments can be made to the operating parameters (e.g. read voltages) to optimize each memory block based on its error analysis.Type: GrantFiled: May 20, 2015Date of Patent: January 17, 2017Assignee: SanDisk Technologies LLCInventors: Niles Yang, Rohit Sehgal, Abhi Kashyap
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Patent number: 9547572Abstract: The invention relates to a predictive maintenance method for a cooled detection module, comprising: a detector (1) comprising a matrix consisting of pixels that are sensitive to light signals; a cryostat (2) containing the detector (1); and a cooling machine (3), said method being characterized in that it comprises a step according to which a processing board (4) of the module, which is electrically connected to the detector (1), to the cryostat (2), and to the cooling machine (3) measures, stores, and processes at least: one motor current, i.e. a supply current of the machine (3); one motor voltage, i.e. a supply voltage of the machine (3); and a number of defective pixels of the detector (1). The invention further relates to a module for implementing the invention.Type: GrantFiled: October 18, 2011Date of Patent: January 17, 2017Assignee: SAGEM DEFENSE SECURITEInventors: Aubry Picard, Thomas Tillard
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Patent number: 9547573Abstract: Methods and apparatus, including computer program products, are provided for serial communications over a communications control pin. The method may include detecting, by a first device including a data interface, a current flow at a first communication control pin at the data interface; and assigning, by the first device based on the detection of the current flow at the first communication control pin, serial data communication circuitry to a second communication control pin at the data interface to carry serial data communications to another device. Related apparatus, systems, methods, and articles are also described.Type: GrantFiled: October 10, 2013Date of Patent: January 17, 2017Assignee: Nokia Technologies OyInventors: Pekka E. Leinonen, Kai Inha, Timo T. Toivola, Pekka Talmola, Rune Lindholm, Timo J. Toivanen
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Patent number: 9547574Abstract: A method includes, in a host that stores data in a storage device, detecting an event that is indicative, statistically and not deterministically, of an imminent power shutdown in the host. A notification is sent to the storage device responsively to the detected event, so as to cause the storage device to initiate preparatory action for the imminent power shutdown.Type: GrantFiled: November 20, 2014Date of Patent: January 17, 2017Assignee: Apple Inc.Inventors: Avraham Poza Meir, Shai Ojalvo, Moshe Neerman
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Patent number: 9547575Abstract: Systems and methods are disclosed which facilitate the management of host computing devices through the utilization of a host computing device control component. The host computing device control component includes a state monitoring component that monitors operating states of the control component. Based on monitoring the operating of the control component, the state monitoring component causes the generation of one or more visual indicator indicative of the operating state of the control component.Type: GrantFiled: August 30, 2011Date of Patent: January 17, 2017Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Matthew T. Corddry, Wyatt D. Camp, Jacob Gabrielson
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Patent number: 9547576Abstract: A multi-core processor system includes a multi-core processor that has plural core groups; and a storage device that stores a constraint on execution time for each application. A first identified core of the multi-core processor is configured to identify a constraint on execution time of a given application that is among the applications and for which an invocation instruction is received; determine whether the identified constraint meets a performance drop condition; assign the given application to a predetermined core of the multi-core processor, upon determining that the identified constraint meets the performance drop condition; and notify a second identified core of a core group among the core groups, of an assignment instruction for the given application, upon determining that the identified constraint does not meet the performance drop condition.Type: GrantFiled: January 9, 2014Date of Patent: January 17, 2017Assignee: FUJITSU LIMITEDInventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo
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Patent number: 9547577Abstract: A method of determining the performance of a processor when processing a unit of data is described. The method comprises the steps of: receiving, at a first sample rate, information indicating the performance of the processor when processing the unit of data; generating an identifier that identifies the unit of data being processed; comparing the identifier with previous identifiers at a second sample rate; and outputting the identifier of the unit of data being processed and the performance information when, during the comparing step, a predetermined condition is met.Type: GrantFiled: September 13, 2010Date of Patent: January 17, 2017Assignee: Sony Computer Entertainment Europe LimitedInventors: Vincenzo Diesi, Lionel Lemarie, Paul Alexander Thomson
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Patent number: 9547578Abstract: Embodiments describe techniques for reducing resource overhead in verbose trace operations by recursively pruning object data prior to string serialization. According to one embodiment, a trace operation is initiated. The trace operation generates a string and specifies one or more objects to serialize and append to the string. At least one object is a nested object. The trace operation recursively parses the nested object while generating the string. Data associated with one or more of the objects to prune from the serialization is determined based on a current prioritization level. The one or more objects is serialized into the string.Type: GrantFiled: February 13, 2015Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sterling W. Bates, Christopher M. Laffoon, William A. Parvin, Aaron J. Quirk
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Patent number: 9547579Abstract: Data being processed by source code modules of a test version of an application is captured and analyzed during execution of the test version of the application. Based on the analysis, errors caused by the source code modules of the test version of the application are automatically detected. Based on a comparison of the source code modules associated with the test version of the application to corresponding source code modules associated with a baseline version of the application, the source code module in the test version of the application that caused the error is identified and reported to a developer or other appropriate personnel so that the error may be corrected.Type: GrantFiled: December 30, 2014Date of Patent: January 17, 2017Assignee: CA, Inc.Inventors: Tony Shen, Kevin Liu
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Patent number: 9547580Abstract: A device may receive an indication to evaluate a portion of program code. The device may cause the portion of program code to be evaluated based on receiving the indication to evaluate the portion of program code. The device may determine an intermediate result used to generate an overall result of evaluating the portion of program code based on causing the portion of program code to be evaluated. The intermediate result may be determined by evaluating a sub-portion of program code included in the portion of program code. The device may receive information that identifies a granularity level for displaying the intermediate result. The granularity level may indicate whether the intermediate result is to be provided for display. The device may selectively provide the intermediate result for display based on the granularity level.Type: GrantFiled: June 22, 2015Date of Patent: January 17, 2017Assignee: The MathWorks, Inc.Inventors: Joseph R. Bienkowski, Claudia G. Wey, Michelle D. Erickson, Benjamin V. Hinkle, Jared D. MacDonald, John E. Booker, Joseph F. Hicklin
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Patent number: 9547581Abstract: This disclosure relates generally to application development, and more particularly to systems and methods for fixing software defects in a binary or executable file. In one embodiment, a software defect management system is disclosed, comprising: a processor; and a memory disposed in communication with the processor and storing processor-executable instructions comprising instructions for: obtaining an application programming interface call for a black-box software application; determining whether the black-box software application is configured in a defective manner to process the application programming interface call; identifying a call processing application to process the application programming interface call, based on determining whether the black-box software application is configured in a defective manner to process the application programming interface call; and providing the application programming interface call for the identified call processing application.Type: GrantFiled: October 1, 2013Date of Patent: January 17, 2017Assignee: WIPRO LIMITEDInventor: Sourav Sam Bhattacharya
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Patent number: 9547582Abstract: Embodiments of the invention provide a method, system and computer program product for selectable data on file viewing in a debugger. A method includes specifying a file in a user interface of a debugger executing in memory of a computer and debugging a target application and determining whether to view data in the file from a perspective of the computer or the target application. The method additionally includes loading the data in the file directly from the computer externally to the target application in response to determining to view the data in the file from the perspective of the computer, but otherwise loading the data through operations performed by the debugger on behalf of the target application in response to determining to view the data in the file from the perspective of the target application. Finally, the method includes displaying the loaded data in a file viewer of the user interface of the debugger.Type: GrantFiled: January 20, 2015Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Christopher D. Filachek, Adris E. Hoyos, Joshua B. Wisniewski
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Patent number: 9547583Abstract: A method for executing a system application test case of a runtime system in an integrated server environment is provided. The method includes establishing a transmission control protocol connection between a client development environment and an integrated server environment, to initiate execution of the system application test case in the integrated server environment. The method further includes issuing a data transfer protocol transmission request to the integrated server environment for a description script of the system application test case. The method further includes transmitting an extensible markup language of the requested description script. The method further includes issuing a data transfer protocol transmission request to execute a test of the system application test case. The method further includes executing the system application test case in the integrated server environment.Type: GrantFiled: March 16, 2016Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventor: Elias K. Jordan
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Patent number: 9547584Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for remote testing. In one aspect, a method includes receiving a first message from a first user device indicating initialization of a client application. The method includes determining that the first user device is a member of a first testing group. The method includes identifying a first testing component associated with the first testing group and capable of altering the client application. The method includes sending the first testing component to the first user device.Type: GrantFiled: March 7, 2012Date of Patent: January 17, 2017Assignee: Google Inc.Inventors: Anish Acharya, Jeson Patel
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Patent number: 9547585Abstract: An information processing device includes a memory and a control unit. The memory is employed as a program work area. The control unit switches between a first mode and a second mode; during the first mode, detects a resident program resident in the memory, and saves information identifying the resident program, as resident program information; and during the second mode, determines whether a requestor program, requesting allocation of the work area, is the resident program or not by comparing requestor-program identifying information with the resident program information, and in succession allocates in the memory respective work areas for one or more requestor programs determined to be resident programs.Type: GrantFiled: March 27, 2015Date of Patent: January 17, 2017Assignee: Kyocera Document Solutions Inc.Inventor: Tomoki Oyasato
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Patent number: 9547586Abstract: A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container.Type: GrantFiled: July 11, 2013Date of Patent: January 17, 2017Assignee: Macronix International Co., Ltd.Inventors: Hung-Sheng Chang, Cheng-Yuan Wang, Hsiang-Pang Li, Yuan-Hao Chang, Pi-Cheng Hsiu, Tei-Wei Kuo
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Patent number: 9547587Abstract: A mechanism is provided for dynamic power and thermal capping in a flash storage system. A set of measurement values are received for the flash storage system, the set of measurement values comprising one or more of a set of current (I) measurement values, a set of voltage (V) measurement values, or a set of temperature (T) measurement values. An average current (Iavg) value from the set of current (I) measurements and, responsive to the average current (Iavg) value being greater than a predetermined maximum current (Imax) value, a determination is made as to whether a rate at which erase operations are performed for the flash storage system is greater than a predetermined minimum erase rate. Responsive to the rate at which erase operations are performed for the flash storage system being greater than the predetermined minimum erase rate, the rate at which erase operations are performed for the flash storage system are decreased by a predetermined value.Type: GrantFiled: May 23, 2014Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Shawn P. Authement, Charles R. Lefurgy, Karthick Rajamani, Andrew D. Walls
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Patent number: 9547588Abstract: Flash memory is subject to a wear out failure mechanism which may depend on the number of times each cell of the memory is programmed and erased. The higher the programming voltage used, the more rapidly the cell degrades. A system and method for reducing the average programming voltage for data sets is disclosed.Type: GrantFiled: September 9, 2014Date of Patent: January 17, 2017Assignee: VIOLIN MEMORY INC.Inventors: Daniel C. Biederman, Jon C. R. Bennett
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Patent number: 9547589Abstract: A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.Type: GrantFiled: December 18, 2014Date of Patent: January 17, 2017Assignee: Super Talent Technology, Corp.Inventors: Frank Yu, Abraham C. Ma, Shimon Chen
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Patent number: 9547590Abstract: Embodiments of the present disclosure provide a method and apparatus for managing memory. Embodiments of the present disclosure, is related to a method and apparatus for managing memory, comprising: monitoring usage status of memory in a first computer device so as to determine available addresses; mapping at least one part of the available addresses to externally accessible shared addresses; and managing the shared addresses on the basis of a memory table so that the at least one part of the available addresses are accessible to a second computer device via the shared addresses, wherein the memory is connected to a dual in-line memory module interface of the first computer device.Type: GrantFiled: December 16, 2014Date of Patent: January 17, 2017Assignee: EMC IP Holding Company LLCInventor: Guoxing Liao
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Patent number: 9547591Abstract: A method, computer program product, and computing system for associating a heatmap file with a multi-portion data file located on a data array. The heatmap file is configured to monitor the usage of each portion of the multi-portion data file. At least one portion of the multi-portion data file is used via a virtual machine executed on a first physical machine. The heatmap file is updated to reflect the usage of the at least one portion of the multi-portion data file.Type: GrantFiled: September 28, 2012Date of Patent: January 17, 2017Assignee: EMC IP Holding Company LLCInventors: Assaf Natanzon, Philip Derbeko, Anat Eyal
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Patent number: 9547592Abstract: A method and system of selecting and migrating relevant data from among data associated with a workload of a virtual machine and stored in source storage cache memory in a dynamic computing environment is described. The method includes selecting one or more policies, the one or more policies including a size policy defining a default maximum size for the relevant data. The method also includes selecting the relevant data from among the data based on the one or more policies in a default mode, and migrating the relevant data from the source storage cache memory to target storage cache memory.Type: GrantFiled: July 29, 2014Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Muhammad Sohaib Aslam, Steven Langridge, Tiia Salo
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Patent number: 9547593Abstract: A microprocessor system is disclosed that includes a first data cache that is shared by a first group of one or more program threads in a multi-thread mode and used by one program thread in a single-thread mode. A second data cache is shared by a second group of one or more program threads in the multi-thread mode and is used as a victim cache for the first data cache in the single-thread mode.Type: GrantFiled: February 28, 2011Date of Patent: January 17, 2017Assignee: NXP USA, Inc.Inventor: Thang M. Tran
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Patent number: 9547594Abstract: A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.Type: GrantFiled: March 15, 2013Date of Patent: January 17, 2017Assignee: Intel CorporationInventor: Thomas Willhalm
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Patent number: 9547595Abstract: A transactional memory system salvages hardware lock elision (HLE) transactions. A computer system of the transactional memory system records information about locks elided to begin HLE transactional execution of first and second transactional code regions. The computer system detects a pending cache line conflict of a cache line, and based on the detecting stops execution of the first code region of the first transaction and the second code region of the second transaction. The computer system determines that the first lock and the second lock are different locks and uses the recorded information about locks elided to acquire the first lock of the first transaction and the second lock of the second transaction. The computer system commits speculative state of the first transaction and the second transaction and the computer system continues execution of the first code region and the second code region non-transactionally.Type: GrantFiled: September 16, 2015Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Harold W. Cain, III, Michael Karl Gschwind, Maged M. Michael, Chung-Lung K. Shum
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Patent number: 9547596Abstract: A data processing apparatus forms a portion of a coherent cache system and has a master device for performing data processing operations including a wait for event operation causing the master device to enter a power saving mode. A cache stores data values for access by the master device when performing the data processing operations. Coherency handling circuitry is responsive to a coherency request from another portion of the coherent cache system, to detect whether a data value identified by the coherency request is present in the cache, and if so, to cause a coherency action to be taken in respect of that data value stored in the cache. Wake event circuitry issues a wake event to the master device if the coherency action is taken, and the master device exits the power saving mode.Type: GrantFiled: December 24, 2009Date of Patent: January 17, 2017Assignee: ARM LimitedInventor: Simon John Craske
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Patent number: 9547597Abstract: A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.Type: GrantFiled: September 25, 2013Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, David W. Cummings, Brian Flachs, Michael S. Siegel, Jeffrey A. Stuecheli
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Patent number: 9547598Abstract: A method of communication between networked devices in a local storage area network includes forming a message for in-band communication within a local storage area network. The message includes at least one major task and one or more associated sub tasks for execution within the storage area network. The method further includes establishing a first communication link at least between a first networked device and a second networked device in response to the formation of the message; transmitting the message from the first networked device to at least the second networked device within the local storage area network; and in response to receiving the message, executing the sub tasks within the message with a processor to complete the major task and support local storage area network functionality.Type: GrantFiled: December 31, 2014Date of Patent: January 17, 2017Assignee: Avego Technologies General IP (Singapore) Pte. Ltd.Inventors: Mark J. Karnowski, Jon Infante
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Patent number: 9547599Abstract: In one embodiment, a method for predicting false sharing includes running code on a plurality of cores and tracking potential false sharing in the code while running the code to produce tracked potential false sharing, where tracking the potential false sharing includes determining whether there is potential false sharing between a first cache line and a second cache line, and where the first cache line is adjacent to the second cache line. The method also includes reporting potential false sharing in accordance with the tracked potential false sharing to produce a false sharing report.Type: GrantFiled: July 25, 2014Date of Patent: January 17, 2017Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Chen Tian, Tongping Liu, Ziang Hu
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Patent number: 9547600Abstract: One embodiment of the system disclosed herein facilitates reduction of latency associated with accessing content of a memory page that has been swapped out by a guest operating system in a virtualized computer system. During operation, a hypervisor detects an I/O write command issued by the guest operating system at a swap location within the guest operating system's swap file and records the swap location. The hypervisor then prefetches contents of a page stored at the swap location within the guest operating system's swap file into a prefetch cache in host machine memory. Subsequently, the hypervisor detects an I/O read command issued by the guest operating system at the swap location within the swap file. In response, the hypervisor provides contents of the page to the guest operating system from the prefetch cache, thereby avoiding accessing the guest operating system's swap file.Type: GrantFiled: July 30, 2014Date of Patent: January 17, 2017Assignee: VMware, Inc.Inventors: Gabriel Tarasuk-Levin, Anne Holler
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Patent number: 9547601Abstract: Methods and systems are presented for custom caching. Application threads define caches. The caches may be accessed through multiple index keys, which are mapped to multiple application thread-defined keys. Methods provide for the each index key and each application thread-defined key to be symmetrical. The index keys are used for loading data from one or more data sources into the cache stores on behalf of the application threads. Application threads access the data from the cache store by providing references to the caches and the application-supplied keys. Some data associated with some caches may be shared from the cache store by multiple application threads. Additionally, some caches are exclusively accessed by specific application threads.Type: GrantFiled: February 27, 2015Date of Patent: January 17, 2017Assignee: PAYPAL, INC.Inventors: Christopher J. Kasten, Greg Seitz
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Patent number: 9547602Abstract: Presented systems and methods can facilitate efficient information storage and tracking operations, including translation look aside buffer operations. In one embodiment, the systems and methods effectively allow the caching of invalid entries (with the attendant benefits e.g., regarding power, resource usage, stalls, etc), while maintaining the illusion that the TLBs do not in fact cache invalid entries (e.g., act in compliance with architectural rules). In one exemplary implementation, an “unreal” TLB entry effectively serves as a hint that the linear address in question currently has no valid mapping. In one exemplary implementation, speculative operations that hit an unreal entry are discarded; architectural operations that hit an unreal entry discard the entry and perform a normal page walk, either obtaining a valid entry, or raising an architectural fault.Type: GrantFiled: March 14, 2013Date of Patent: January 17, 2017Assignee: NVIDIA CORPORATIONInventors: Alexander Klaiber, Guillermo Juan Rozas
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Patent number: 9547603Abstract: A memory management unit for I/O devices uses page table entries to translate virtual addresses to physical addresses. The page table entries include removal rules allowing the I/O memory management unit to delete page table entries without CPU involvement significantly reducing the CPU overhead involved in virtualized I/O data transactions.Type: GrantFiled: August 28, 2013Date of Patent: January 17, 2017Assignee: Wisconsin Alumni Research FoundationInventors: Arkaprava Basu, Mark D. Hill, Michael M. Swift
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Patent number: 9547604Abstract: Data operations, requiring a lock, are batched into a set of operations to be performed on a per-core basis. A global lock for the set of operations is periodically acquired, the set of operations is performed, and the global lock is freed so as to avoid excessive duty cycling of lock and unlock operations in the computing storage environment.Type: GrantFiled: October 2, 2014Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Lokesh M. Gupta, David B. Whitworth
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Patent number: 9547605Abstract: A method for backing up data in a data center, device and system are provided. The data in all the VMs of one data center can be backed up simultaneously, and the associations between the VMs are also backed up during the backup, so it is unnecessary to concern the recovery orders of the VMs when the data of the data center is recovered. Meanwhile, when the stored data is exported from the hypervisor node, it is unnecessary to notify the upper layer OS for a backup, thereby improving the data backup efficiency and reducing the system logical complexity.Type: GrantFiled: November 28, 2012Date of Patent: January 17, 2017Assignee: Huawei Technologies Co., Ltd.Inventors: Zhou Yu, Shaoyong Wang
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Patent number: 9547606Abstract: A peripheral device connected to a local electronic device which is connected to at least one communication network can communicate with a peripheral device attached to a remote electronic device as if the remote peripheral device was locally attached. Data designated for the remote peripheral device is received by a local virtual device object and transmitted to the remote electronic device via at least one of the electronic devices communication interfaces or peripheral devices. Data received by the remote electronic device's communication interface or peripheral device is written to the peripheral device at the remote electronic device by a virtual device object. For compensation of different transfer speeds or outages between the peripheral device and the communication interface or another peripheral device the virtual device provides the ability to utilize the virtual devices emulation driver that is attached to the virtual device object as an I/O buffer.Type: GrantFiled: March 21, 2016Date of Patent: January 17, 2017Assignee: Open Invention Network LLCInventor: Martin Wieland
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Patent number: 9547607Abstract: Systems, methods, and computer-readable storage media are provided for brokering access to peripheral devices and/or device models associated with a computing system. An access broker evaluates requests for access to peripheral devices/models on behalf of a plurality of applications. The access broker evaluates requests for access to peripheral devices including scanners, point-of-sale devices, and devices using ubiquitous device protocols (e.g., USB, HID, Bluetooth, and Bluetooth LE) utilizing application declarations and user consents based upon device model identifiers and/or device-specific identifiers associated with the various devices. Applications may be notified of consent changes at runtime and/or application firmware updates for peripheral devices may be conducted upon receipt of user consent, for instance, to ensure adequate battery power before performing a peripheral device firmware update.Type: GrantFiled: June 27, 2013Date of Patent: January 17, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Dylan David Miller, George Evangelos Roussos, Paul Sliwowicz, Peter William Wieland, Benjamin Scott McGregor
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Patent number: 9547608Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.Type: GrantFiled: February 18, 2016Date of Patent: January 17, 2017Assignee: TQ DELTA, LLCInventors: Marcos C. Tzannes, Michael Lund
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Patent number: 9547609Abstract: A data interface is provided for point-to-point communications between two devices, such as a read channel and a disk controller in an HDD system. An interface for communications from a transmitting device to a receiving device comprises a data bus configured to communicate m bits of data and a corresponding n bit data tag, wherein a given n bit data tag identifies a data type of a corresponding m bits of data on the data bus. An acknowledge signal from the receiving device optionally indicates that data on the data bus has been received and that the data on the data bus can be changed to a new value. A valid flag optionally indicates when a new predefined m-bit data value and corresponding n-bit tag value are on the data bus.Type: GrantFiled: October 31, 2013Date of Patent: January 17, 2017Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Edward J. D'Avignon, Keith R. Bloss, Semere T. Menghis
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Patent number: 9547610Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.Type: GrantFiled: March 18, 2016Date of Patent: January 17, 2017Assignee: INPHI CORPORATIONInventors: Christopher Haywood, Chao Xu, Fouad G. Tamer