Abstract: A system on chip is provided which performs a built-in self-test operation using an error access pattern. The system on chip includes a master device and a slave device. A bus is configured to transfer an instruction from the master device to the slave device. A built-in instruction capture circuit is configured to receive and store the instruction. The built-in instruction capture circuit stores the instruction as the error access pattern when an error occurs in the slave device due to the instruction.

Abstract: A logic design may include control and datapath circuitry. The datapath circuitry may be implemented in a double modular redundancy arrangement that generates respective first and second data signals. The control circuitry may be implemented in a triple modular redundancy arrangement. Storage circuitry may be used to buffer the first and second data signals. Real-time error detection circuitry may perform real-time error detection operations on the first and second data signals. Background error checking circuitry may perform background error checking operations such as cyclic redundancy check calculations on configuration data. In response to an error detected by the real-time error detection circuitry, the circuitry may select between the buffered first and second data signals to produce the output data signal. The selection may be performed based on the background error checking operations and may be delayed relative to the real-time detection of the error.

Abstract: In accordance with some embodiments, a DisplayPort control plane may be supported over a Wireless Gigabit Alliance or other wireless air interface. Some embodiments may efficiently optimize the amount of wireless bandwidth needed to accomplish tasks.

Abstract: Methods for dynamically instrumenting a program while the program is executing are described. In some embodiments, profiling hooks may be selectively inserted into and removed from a program while the program is running. The hooks may gather profiling information, such as the frequency and duration of function calls, for a selected set of functions. The hooks may be inserted into the program without requiring a special build or modifications to the binary by modifying machine-level instructions for the program stored in system memory. The ability to selectively insert instrumentation into the machine-level instructions stored in the system memory allows a set of functions to be selected during execution of the program and hooks for each function of the set of functions to be dynamically inserted or removed during execution of the program to precisely capture profiling information for the set of functions.

Abstract: An abnormal state of an allocated task in a processing node is detected correctly without using any resource of the processing node. A power usage statistics storing unit 240 stores a statistical value representing a power usage of the processing node in a state of executing the task. A power usage comparing unit 250 compares a newly collected power usage of the processing node in a state of executing the task with the statistical value representing a power usage of the processing node, which is stored in the power usage statistics storing unit 250, to detect an abnormal state of the task in the processing node.

Abstract: A Sub-Diagnostic Module incorporated into a System Module. The Sub-Diagnostic Module receives signals from the System Modules through the diagnostic signal interface. The diagnostic signal interface passes the signals through to the diagnostic signal evaluation logic where it determines if a signal or combination of signals is an event to be recorded in the sub-diagnostic registers and/or the sub-diagnostic log memory. The events recorded in the registers and log memory are accessed by the Portable Diagnostic Module through the Sub-Diagnostic Module's diagnostic protocol interface. Recorded events placed in log memory are synchronized by the sub-diagnostic time synchronizer. The time synchronizer receives high resolution time information from a local clock, such as a physical layer clock, and lower resolution network synchronized information from the diagnostic protocol interface.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted processor to generate an instruction set profile for each instruction of the instruction set architecture. A combination of instruction sequences for the targeted processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted processor. Performance of the targeted processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted processor to generate an instruction set profile for each instruction of the instruction set architecture. A combination of instruction sequences for the targeted processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted processor. Performance of the targeted processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: A meta-debugger receives a first debugging command from a debugger client to set a breakpoint in a first service in a first language and sets the breakpoint in a first native debugger. After receiving a service message invoking the first service, the breakpoint is triggered and the meta-debugger provides to the debugger client a first graphical representation of the first native debugger. The meta-debugger receives a second debugging command from the debugger client, converts the second debugging command into a third debugging command to provide to the first native debugger. After invoking a second service in a second language, the meta-debugger provides to the debugger client a second graphical representation of the second native debugger. The meta-debugger receives a fourth debugging command from the debugger client, converts the fourth debugging command into a fifth debugging command to provide to the second native debugger.

Abstract: A streams manager monitors data tuples processed by a streaming application represented by an operator graph. The streams manager includes a tuple breakpoint mechanism that allows defining a tuple breakpoint that fires when a tuple has been in the operator graph too long. What constitutes too long can be defined in a number of different ways, including a time limit, a processing limit for multiple operators, and a processing limit for an individual operator. When the tuple breakpoint fires, one or more operators in the operator graph are halted according to specified halt criteria. Information corresponding to the breakpoint that fired is then displayed. The tuple breakpoint mechanism thus provides a way to debug a streaming application that may have data tuples that stay in the operator graph too long.

Abstract: Methods and systems are provided for debugging application code in an on demand environment. The method includes executing the code on a server in the on demand environment; identifying a first location within the code having a suspected error; defining a first check point within the code corresponding to the first location; subsequently re-executing the code, including the first check point, on the server; creating a memory dump corresponding the first check point during re-execution of the code; and debugging the code based on the heap dump without suspending subsequent re-execution of the code.

Abstract: A streams manager monitors data tuples processed by a streaming application represented by an operator graph. The streams manager includes a tuple breakpoint mechanism that allows defining a tuple breakpoint that fires when a tuple has been in the operator graph too long. What constitutes too long can be defined in a number of different ways, including a time limit, a processing limit for multiple operators, and a processing limit for an individual operator. When the tuple breakpoint fires, one or more operators in the operator graph are halted according to specified halt criteria. Information corresponding to the breakpoint that fired is then displayed. The tuple breakpoint mechanism thus provides a way to debug a streaming application that may have data tuples that stay in the operator graph too long.

Abstract: A computer implemented system and method for testing code for implementation in web browsers, implements test class code defining test cases for testing operations on web applications implementable by different web browser types, and implements handler class code comprising code specific to each web browser and defining strategies to be used by test cases. The handler class code implements a handler interface and the test class code uses the handler interface to identify the methods to be used for test cases. A non-transient storage medium stores code for a handler template supporting different web browser types for use in a test environment, the code comprising code to identify browser specific strategies for implementation in the test environment; code to implement a strategy support interface for use by a handler factory to select a handler instance; and code to implement a handler interface for use by a test case to identify methods for testing web browser functions.

Abstract: Error logs, bug reports, and other databases identifying problems with a tracer system may be mined to determine how a tracer may interact with a given function, module, or other group of functions. Based on such reports, a tracer may be configured to avoid certain functions or to trace such functions in a specific manner. In some cases, tracer may be configured to limit tracing to certain parameters or with other limitations to avoid any known conditions under which errors occur.

Abstract: A system and method for indexing and annotating use cases and generating test scenarios using in-memory processing from the corresponding use case model includes a use case model creator to create/build an in-memory use case model for the use cases created by a user; a predetermined structural format, according to which the steps of the use cases are organized by an editor; an indexer to appropriately index the steps of the use case(s) in the use case model; a generator which facilitates extraction of the indexed steps from the use case and identification of at least one ordered set in which the indexed steps can be assembled; and a test scenario generator to generate a test scenario having the indexed steps arranged according to the ordered set identified by an identifier and being validated by a validator according to pre-determined validation criteria.

Abstract: Identifying performance issues in an application under test (AUT). The AUT executes on a system under test (SUT) in a test environment, and uses one or more context parameters of the SUT and/or the test environment. A rule engine identifies performance antipatterns in trace data generated by the AUT when executing a set of test suites, based on a set of performance antipattern definition rules, each performance antipattern associated with one or more context parameters. One or more performance test suites are identified that cause the AUT to use at least one of the one or more context parameters associated with the identified antipatterns. The list of identified performance test suites is ranked, based on respective priority values associated with each identified antipattern.

Abstract: A method for testing control software of a controlled system is disclosed. The method may involve providing control software code data for each of the one or more electronic control units. The method may further involve providing simulation code data for the controlled system. The method may further involve providing verification requirement information data that indicates one or more verification requirement conditions corresponding to a respective control error situation. The method may further involve creating a system model based on the provided simulation code data and the provided control software code data provided for each of the one or more electronic control units. The method may further involve creating an executable program based on the created system model and performing a software verification process on the basis of the executable program.

Abstract: In software development, the provision of a testing tool which includes a method for defining a data source dynamically during an execution run, instead of programming such a definition within test script.

Abstract: Methods, computer program products, and systems for managing memory in a computer system in which memory locations in use at any given time are represented as a set of memory objects in a first object graph. The first object graph includes a system root object associated by references to each of the memory objects. A method includes creating a second root object for the memory so as to form a second object graph for the memory. The method also includes, in response to the dereferencing of a first object from the first object graph, associating the dereferenced first object with the second object graph so that the second object graph includes at least one dereferenced object.

Abstract: A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an LIO line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (I/O) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information. If the page-size information is the first information, the LIO line switching circuit generates the first and second selection signals using a row address, and if the page-size information is the second information, the LIO line switching circuit generates the first and second selection signals using a column address.

Abstract: Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining a free physical page pair comprising a same physical address available on the first and second local volatile memory devices; and mapping the free physical page pair to a single virtual page address.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a memory controller. An apparatus includes a volatile memory medium located on a memory module. An apparatus includes a non-volatile memory medium located on a memory module. A memory controller is located on a memory module. A memory controller may be configured to provide access to at least a non-volatile memory medium over a direct wire interface with a processor.

Abstract: A control device includes: a management information generation unit configured to generate or update logical-physical block address management information with respect to either data to be written to a non-volatile memory or data which has been already written in the non-volatile memory, the logical-physical block address management information indicating association between a logical block address and a physical block address on the non-volatile memory; and an access control unit configured to, during write of the data to the non-volatile memory, control write of the data as well as the logical-physical block address management information to a physical write unit of the non-volatile memory.

Abstract: Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

Abstract: A data storage apparatus has a transmission interface, a nonvolatile memory and a controller. The controller records a non-completed flag. When the controller starts a card opening process, the nonvolatile memory is configured under card opening, and the non-completed flag is set non-completed status. When the controller receives a format command form the transmission interface, the nonvolatile memory is formatted and the non-completed flag is set as completed status. When the controller receives a write command, the write data are scrambled before being written to the nonvolatile memory. When in non-completed status, when the controller receives a read command from the transmission interface, no matter whether the data corresponding to the requested address are scrambled, the data are descrambled and descrambled are provided via the transmission interface.

Abstract: Systems and methods for storing data to a non-volatile storage device are provided. A request to store data to the storage device at a given address corresponding to one of a plurality of regions of the storage device is received. A region classification map associated with the storage device associates a classification with each of the plurality of regions. A determination is made based on the region classification map as to which classification is associated with the one of the plurality of regions corresponding to the given address. The data is stored at the given address in response to determining that the one of the plurality of regions is associated with a first classification. The data is stored to an alternate location in response to determining that the one of the plurality of regions is associated with a second classification.

Abstract: A memory device according to an embodiment includes a non-volatile storage device, a volatile storage device that stores saved data which is saved in the host-side storage device when a first operation mode changing process is executed by the memory device, and a control unit. The control unit transmits, to the host device, a write command that is an instruction to write the saved data to the host-side storage device and the saved data, when the first operation mode changing process is executed by the memory device.

Abstract: A semiconductor system includes a semiconductor memory device suitable for storing data, and a host suitable for controlling the semiconductor memory device in response to an external command signal, in which the semiconductor memory device includes a buffer block suitable for storing first data programmed under control of the host, and a main block suitable for storing the second data programmed under control of the host or a copy of the first data stored in the buffer block at a sudden power fail.

Abstract: A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers.

Abstract: Atomically accumulating memory updates in a computer system configured with an accumulator that is memory mapped. The accumulator includes an accumulator memory and an accumulator queue and is configured to communicatively couple to a processor. Included is receiving from the processor, by the accumulator, an accumulation request. The accumulation request includes an accumulation operation identifier and data. Based on determining, by the accumulator, that the accumulator can immediately process the request, immediately processing the request. Processing the request includes atomically updating a value in the accumulator memory, by the accumulator, based on the operation identifier and data of the accumulation request. Based on determining, by the accumulator, that the accumulator is actively processing another accumulation request, queuing, by the accumulator, the accumulation request for later processing.

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

Abstract: A snoop filter for a multi-processor system has a storage device and a control circuit. The control circuit manages at least a first-type entry and at least a second-type entry stored in the storage device. The first-type entry is configured to record information indicative of a first cache of the multi-processor system and first requested memory addresses that are associated with multiple first cache lines each being only available in the first cache. The second-type entry is configured to record information indicative of multiple second caches of the multi-processor system and at least a second requested memory address that is associated with a second cache line being available in each of the multiple second caches.

Abstract: A distributed processing system includes a first site and a second site, each containing at least one device having cache storage, nonvolatile storage, where, in response to moving a process running on the processor of the first site to the processor running on the second site, data in the cache storage of the first site is no longer accessed by the process, the data being read into the cache of the storage of the first site in response to the process accessing data in the non-volatile memory of the first site prior to being moved to the second site. A process running on the processor of the first site moving to the processor running on the second site and corresponding cache slots may be detected by parsing the VMFS containing virtual machine disks used by the process.

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract: A method for storing information may include determining whether a received data object fits inside a particular one of a plurality of free blocks in a memory bitmap. Each of the plurality of free blocks may include a column of the memory bitmap with a top margin, a bottom margin, and a predetermined width. If the received data object fits, the received data object may be stored in the particular one of the plurality of free blocks, starting at the margin of the particular one of the plurality of free blocks. The particular one of the plurality of data blocks may be resized by moving the margin to start below or next to the stored received data object. The determining may include, for each of the plurality of free blocks, a height of the received data object may be compared with a height of each of the free data blocks.

Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.

Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract: This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.

Abstract: An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave that directs one or more commands to two or more queues, where the one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.

Abstract: Embodiments of memory devices, computer systems, security apparatus, data handling systems, and the like, and associated methods facilitate security in a system incorporating the concept of a security perimeter which combines cryptographic and physical security. The memory device can comprise a memory operable to store information communicated with a processor, and a logic operable to create at least one cryptographic security perimeter enclosing at least one selected region of the memory and operable to manage information communication between the processor and the at least one selected region of the memory.

Abstract: A memory module secures data stored on the memory module. A request for the data from a computer system is received by the memory module. A verification key from the computer system is also received by the memory module. A reference key is retrieved by the memory module, the reference key is stored on the memory module. A comparison status is generated by the memory module by comparing the verification key with the reference key. A response is sent to the computer by the memory module that is dependent upon the comparison status.

Abstract: A storage controller is provided. The storage controller includes a memory storing an indication of a current owner, a previous owner, and a preferred owner for each of one or more logical volumes. The storage controller is configured to write protect the logical volumes where the current owner and the preferred owner is the storage controller and the previous owner of the logical volumes was a different storage controller. For the logical volumes where the storage controller is the preferred but not the current owner, the storage controller is set as the current and preferred owner of the logical volumes that the different storage controller was the current but not the preferred owner for, storage controller is set as the previous owner of the logical volumes that the storage controller is the current and preferred owner of, and allowing read and write access to the one or more logical volumes.

Abstract: Embodiments of systems and methods disclosed herein may isolate the working set of a process such that the data of the working set is inaccessible to other processes, even after the original process terminates. More specifically, in certain embodiments, the working set of an executing process may be stored in cache and for any of those cache lines that are written to while in secure mode those cache lines may be associated with a secure descriptor for the currently executing process. The secure descriptor may uniquely specify those cache lines as belonging to the executing secure process such that access to those cache lines can be restricted to only that process.

Abstract: Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system performs a maze unlock sequence by operating a memory device in a maze unlock mode. The maze unlock sequence involves writing a first data pattern of a plurality of data patterns to a memory address of the memory device, reading a first set of data from the memory address, and storing the first set of data in a validated data array. The maze unlock sequence further involves writing a second data pattern of the plurality of data patterns to the memory address, reading a second set of data from the memory address, and storing the second set of data in the validated data array. A difference vector array is generated from the validate data array and an address map of the memory device is identified based on the difference vector array.

Abstract: A recording apparatus includes a recording unit, a waveguide forming unit, a communication unit, and a memory controller. The recording unit is configured to record and hold data. The waveguide forming unit is configured to function as a transmission path that transmits the data. The communication unit is configured to communicate with the waveguide forming unit. The memory controller is configured to control input and output of the data to and from the recording unit.

Abstract: A compound USB device has a controller and a N+1 component USB devices. Each component USB device Ci is assigned Ei endpoints, where 0?i?N and where each component USB device is assigned at least as many endpoints as required by its functionality. At least one component USB device is assigned the maximum number endpoints. At least one other component USB device is assigned the minimum number of endpoints, which is less than the maximum. The controller includes a RAM-share subsystem with a RAM module. The RAM module includes a USB RAM segment that has a buffer descriptor (BD) table and an endpoint data buffer. The BD table includes a corresponding entry for each assigned endpoint. At least a portion of the USB RAM segment is assigned for non-USB uses.