Abstract: A system includes a plurality of data input ports, each port corresponding to one of a plurality of different levels of security classification; a security device, configured for cryptographic processing, coupled to receive incoming data from each of the plurality of input ports, wherein the incoming data includes first data having a first classification level; a key manager configured to select and tag-identified first set of keys from a plurality of key sets, each of the key sets corresponding to one of the different levels of security classification, wherein the first set of keys is used by the security device to encrypt the first data; and a common encrypted data storage, coupled to receive the encrypted first data from the security device for storage.

Abstract: Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a data from an arbiter, where the data is selected by the arbiter from data at memory link queues. The MEE interface may adjust a timing rate to send the data to match a timing of a MEE core. The MEE core may be coupled to the MEE interface and may receive the data from the MEE interface.

Abstract: Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The device may be configured according to a mode in which execution of a particular command is unauthorized while the device is configured in the mode. While in the mode, the device may authorize execution of the command to occur during the mod.

Abstract: A computing device has a security module that (i) receives a request to decrypt encrypted data; (ii) sets up an uninterruptible timer based on a specified time interval; (iii) decrypts the encrypted data to generate and stores corresponding decrypted data in a memory within the computing device; and (iv) provides a trigger signal to delete the decrypted data from the memory after expiration of the specified time interval as determined by the timer. The security module limits the duration that the decrypted data is stored in the memory and thus reduces the chance the data can be subject to unauthorized accessed.

Abstract: An integrated circuit, preferably for controlling vehicle functions, having an analog-digital converter for converting an analog signal into digital measurement values, a DSP unit, connected downstream from the analog-digital converter, for pre-processing the digital measurement values, a central computing unit, connected to the DSP unit so as to transmit data, for further processing of the digital measurement values, the DSP unit being set up to control the analog-digital converter during operation.

Abstract: Embodiments herein provide for avoiding ID collisions in a memory device. In one embodiment, a memory device includes slave logic operable to receive I/O commands from a plurality of master components and a memory controller operable to process the I/O commands from the master components to operate on data in the memory. Each I/O command comprises an ID assigned by its originating master component. The slave logic is further operable to determine the ID of a first I/O command from a first of the master components, to receive a second I/O command from a second of the master components having a same ID as the first I/O command while the first I/O command is being processed by the memory controller, and to stall the second I/O command until the first I/O command is complete while allowing other I/O commands with other IDs to access the memory.

Abstract: Starting a host computer and a high-speed data transfer achieved by NVMe are both realized. When the host computer is started and a command for instructing to read an OS in accordance with a specific protocol is issued from the host computer via a host-side bus to a specific function from among a plurality of functions, an interface device issues to a controller a request for instructing to read the OS and transfers the OS read by the controller to the host computer. When an NVMe command for instructing an I/O for the controller in accordance with an NVMe protocol is issued from the host computer via the host-side bus to an NVMe function from among a plurality of functions after the host computer is started, the interface device issues to the controller an I/O request based on the NVMe command.

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A multi-streaming memory system includes a memory, and a processor coupled to the memory, the processor executing a software component that is configured to identify multiple attributes that are each related to logical block addresses (LBAs), and that each correspond to each of a plurality of streams of data writes, evaluate an importance factor for each of the attributes for each of the streams, and clustering two or more of the LBAs by assigning a stream ID to each of the LBAs based on all of the importance factors for each of the LBAs and the assigned stream.

Abstract: A method performed by an information handling system, the method including detecting that a first device has been connected to the information handling system (IHS). The method further including in response to detecting that the first device has been connected, updating one or more fabric consistency validation rules of the IHS associated with the first device and one or more other devices that are connected to the first device by one or more links, and validating that the first device is compatible with each of the other devices based on the updated fabric consistency validation rules of the IHS.

Abstract: An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

Abstract: A communication device provides wireless communication between a controller in a motor vehicle and a network having at least one device external to the motor vehicle. The controller includes a computation device with at least two processor cores. Data interchange between the communication device and a first processor core takes place exclusively via a second of the processor cores.

Abstract: A signal name based method for automatic signal exchange between multiple embedded CPU boards, includes: dividing CPU boards into master board and slave board, where each slave board sends signal registration information to the master board; reading an exchange relationship between an output signal and an input signal that is represented by a connection line between signal names, calculating and allocating a data bus address to which the output signal and the input signal are mapped, and sending memory addresses, data types, and bus addresses of signals to each slave board; saving these as output signal tables and input signal tables; and writing, by a signal sender, a value of an output signal into a corresponding bus address according to the output signal tables, and reading, by a receiver, a value of an input signal from a corresponding bus address according to the input signal tables.

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.

Abstract: Techniques are disclosed to provide quality of service in bus interconnects with multi-stage arbitration. Source computing elements tag packets with a priority class and/or a number of credits that are based on a distance to a destination computing element of the packets. Arbiters controlling access to the bus interconnect perform arbitration operations to serve packets having higher relative priority based on the priority levels and/or numbers of credits of each packet.

Abstract: An operating method for a card reader, comprising: powering on a card reader, and setting an operating mode according to the type of a device connected thereto; judging the operating mode, waiting to receive audio data if the operating mode is an audio mode, converting the received audio data into a digital signal, forming a data packet by the digital signal, parsing the data packet to obtain a parsing result, judging an instruction type according to the parsing result, executing a corresponding operation according to the instruction type, converting the obtained operation result into an audio data packet, and sending the audio data packet to the device connected thereto; and waiting to receive USB data if the operating mode is a USB mode, judging an instruction type of the received USB data, executing a corresponding operation according to the instruction type, and returning the operation result to the device connected thereto.

Abstract: An information processing apparatus comprises a management module configured to manage peripheral device information relating to a peripheral device connected with connection destination devices in association with each of the connection destination devices, a selection module configured to select a connection destination candidate from the connection destination devices on the basis of the peripheral device information if connection is requested from a new peripheral device and an informing module configured to inform the connection destination device serving as the connection destination candidate selected by the selection module.

Abstract: A PCIe switch including a memory and a processor. The processor is operable to receive a transaction from an information handling system to an endpoint device, determine that the transaction is a request to receive firmware code from the endpoint device, block the transaction from being issued to the endpoint device, and provide the firmware code to the information handling system from the memory.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.

Abstract: Unified systems and methods for interchip and intrachip node communication are disclosed. In one aspect, a single unified low-speed bus is provided that connects each of the chips within a computing device. The chips couple to the bus through a physical layer interface and associated gateway. The gateway includes memory that stores a status table summarizing statuses for every node in the interface fabric. As nodes experience state changes, the nodes provide updates to associated local gateways. The local gateways then message, using a scout message, remote gateways with information relating to the state changes. When a first node is preparing a signal to a second node, the first node checks the status table at the associated local gateway to determine a current status for the second node. Based on the status of the second node, the first node may send the message or take other appropriate action.

Abstract: In a communication device according to one embodiment, a bridge processor transmits, through the second communication processor, a first data transfer request having been received at the first communication processor and transmits, through the first communication processor, a first response having been received at the second communication processor. A cache proxy processor transmits a second response including the data through the first communication processor when the data is present in a storage device and when the data is not present, receives a third response including data by proxy from the second communication device and transmits a fourth response including the data through the first communication processor. A state acquiring circuit acquires information indicating a state of the storage device. A distribution processor determines which of the bridge processor and the cache proxy processor performs processing related to the first data transfer request according to the state of the storage device.

Abstract: A new approach is proposed to offload of link aggregation from a host to a HBA in SRIOV mode. The HBA first creates one or more link aggregation offload engines each having one or more physical ports and to establish a first link between a VM running on the host and one of the link aggregation offload engines for network data transmission with the VM. Once a data packet is received from the VM over the first link, the link aggregation offload engine chooses a first physical port based on its link aggregation method and establish a second link with the chosen first physical port to transmit the packet out of the HBA. If the second link fails, the link aggregation offload engine then chooses a second physical ports and establish a third link with the chosen second physical port to transmit the packet out of the HBA device instead.

Abstract: The present disclosure provides an electronic device that includes a lower device configured to process local input/output communications between the electronic device and a host, wherein the lower device is stateless. The electronic device also includes a memory comprising a data flow identifier used to associate a data flow resource of the host with a data flow resource corresponding to the lower device. A data packet sent from the lower device to the host includes the data flow identifier.

Abstract: Methods and systems for connecting interchangeable input/output (I/O) modules having individual and shared personalities may include a generic I/O bay of a server hosting one or more compute nodes configured to be connected to one or more removable I/O modules. A first connector coupled to a first I/O module may connect the first I/O module to a compute node having a second connector. The first I/O module may be oriented about a first axis. The compute node may be oriented about a second axis. The first connector and the second connector may be capable of being connected in a plurality of orientations. In one embodiment the second axis may be orthogonal to the first axis, and the removable I/O modules may include shared I/O modules. In an embodiment the second axis may be parallel to the first axis, and the removable I/O modules may include individual I/O modules.

Abstract: A server is disclosed having at least one processor, at least one primary memory, and at least one secondary memory. The server further includes a primary memory board disposed primarily to support the at least one primary memory; a secondary memory board disposed primarily to support the at least one secondary memory; and a processor board disposed primarily to support the at least one processor. An optical bus couples the primary memory board, the secondary memory board, and the processor board to each other to communicatively couple the at least one processor to the at least one primary memory and the at least one secondary memory.

Abstract: A standardized hot-pluggable transceiving unit comprising a housing, a connector and a processing unit. The housing has specific standardized dimensions and can be inserted into a chassis of a hosting unit. The connector receives an IP flow. The processing unit processes packets of the IP flow based on a control plane message. The control plane message is received by the connector receiving the IP flow or by another connector of the transceiving unit. The processing unit may further generate a report or an alarm related to the IP flow, for transmission by the transceiving unit. The IP flow may for example transport a video payload. A system comprising a chassis and the transceiving unit is also disclosed. The chassis comprises a processing unit capable of processing packets of IP flows. The transceiving unit is inserted into the chassis and exchanges data with the processing unit of the chassis.

Abstract: An approach is provided for preventing access to mis=plugged devices by a service processor (SP). The SP retrieves an expected device identifier of a device associated with a hot-plug event. The hot-plug event was received in response to the device being connected to a selected port of a service processor, and the port is one many ports included in the SP. The SP sends a request for a device identifier via the port and actual device identifier is received from the device. The device is validated by comparing the expected device identifier with the actual device identifier. If the identifiers match, a link between the SP and the device is maintained. On the other hand, if the identifiers do not match, the link between the SP and the device is terminated or otherwise inhibited.

Abstract: A multifunction expansion device includes a driving unit, an expansion unit and a connecting unit. The multifunction expansion device is characterized that, the expansion unit is electrically connected to the driving unit and the connecting unit. The expansion unit further includes an input and output device and a signal device. The input and output device is provided with a plurality of connecting pins, and allows a plurality of connecting pins to enable corresponding connection and transmission through connecting pin combinations in different quantities and operating with the signal device. Accordingly, by utilizing various combinations of idle connecting pins and operating with the signal device, the expansion unit allows the driving unit to operate devices of the connecting unit, thereby allowing the expansion module to correspond with various devices.

Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.

Abstract: A universal serial bus (USB) device, an electronic apparatus including the same and a control method thereof are provided. The electronic apparatus includes a signal transceiver configured to transmit and receive a signal to and from an external apparatus; a first processor configured to communicate with the external apparatus; a switching unit configure to selectively supply a signal generating power to a signal transmission line between the signal transceiver and the first processor; a second processor configured to control the switching unit to generate a conversion signal corresponding to a predetermined event signal if the signal received from the external apparatus comprises the predetermined event signal; and a third processor configured to control the first processor to communicate with the external apparatus if the conversion signal is received.

Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.

Abstract: An example method for facilitating low latency remote direct memory access (RDMA) for microservers is provided and includes generating queue pair (QPs) in a memory of an input/output (I/O) adapter of a microserver chassis having a plurality of compute nodes executing thereon, the QPs being associated with a remote direct memory access (RDMA) connection between a first compute node and a second compute node in the microserver chassis, setting a flag in the QPs to indicate that the RDMA connection is local to the microserver chassis, and performing a loopback of RDMA packets within the I/O adapter from one memory region in the I/O adapter associated with the first compute node of the RDMA connection to another memory region in the I/O adapter associated with the second compute node of the RDMA connection.

Abstract: An “RDMA-Based Memory Allocator” applies remote direct memory access (RDMA) messaging to provide fast lock-free memory allocations and de-allocations for shared memory distributed across multiple servers in an RDMA-based network. Alternately, in various implementations, the RDMA-Based Memory Allocator combines RDMA messaging and remote procedure call (RPC) requests to provide fast lock-free memory allocations and de-allocations for shared memory distributed across multiple servers in an RDMA-based network. In either case, any of the networked servers can act as either or both a client for requesting (or releasing) memory allocations and a host for hosting a portion of the distributed memory. Further, any server (including the requesting client) may act as the host for the distributed memory being allocated or de-allocated by any client via RDMA messaging. Advantageously, being lock-free improves overall performance of memory access between networked computers by reducing overall system latency.

Abstract: According to an embodiment of the invention there may be provided a method for hybrid remote direct memory access (RDMA), the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing the data to the first application memory if it determined that the data should be indirectly written to the first application memory; (iv) if it determined that the data should be directly written to the first application memory then: (iv.a) directly writing, by the first hardware accelerator the data to the first application memory without writing the data to any buffer of the operating system; and (iv.

Abstract: An electronic chip and a chip assembly are described. The electronic chip comprises one or more processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one of the one or more processing cores implements a game engine in hardware.

Abstract: According to one embodiment, a method for solving a plurality of spatiotemporal planning problems. The method may include creating a domain model. The method may also include assigning a solution bound associated with the created domain model to infinity. The method may further include calculating a solution to the created domain model based on the assigned solution bound using at least one of a best-first search algorithm. The method may also include updating the assigned solution bound based on the calculated solution. The method may further include presenting the calculated solution to a user based on the updated solution bound not equaling infinity.

Abstract: An embodiment of the present invention discloses a data processing method, including: twiddling input data, so as to obtain twiddled data; pre-rotating the twiddled data by using a symmetric rotate factor, where the rotate factor is a·W4L2p+1, p=0, . . . , L/2?1, and a is a constant; performing a Fast Fourier (Fast Fourier Transform, FFT) transform of L/2 point on the pre-rotated data, where L is the length of the input data; post-rotating the data that has undergone the FFT transform by using a symmetric rotate factor, where the rotate factor is b·W4L2q+1, q=0, . . . , L/2?1, and b is a constant; and obtaining output data.

Abstract: A method for determining parameter values of an induction machine. The method may be executed by a dedicated computer system. The method includes sampling a voltage signal, a current signal and a rotational speed signal of the induction machine at the time the induction machine is started, calculating a resistance and a reactance of the induction machine at each of a plurality of slip rates according to the voltage signal and the current signal, calculating a plurality of coefficients of a polynomial fraction based on the resistances and the reactances, calculating the parameter values of an equivalent circuit according to the plurality of coefficients of the polynomial fraction, calculating a moment of inertia and a friction coefficient of the induction machine according to the calculated parameter values and the rotational speed signal of the equivalent circuit, and outputting the moment of inertia and the friction coefficient of the induction machine.

Abstract: A processing device in an electronic device receives a search query for a reflowable electronic content item, the search query indicating at least one of a first formatting style or a first formatting construct. The processing device determines a first page of the electronic content item for which style data indicates that at least a portion of content data associated with the first page was previously presented using the at least one of the first formatting style or the first formatting construct, wherein the content data associated with the first page is defined according to previous display configuration settings used to previously present the first page. The processing device causes presentation of an indication of the first page as a search result.

Abstract: The invention relates to electronic document processing. Embodiments of the present invention relate to a method and apparatus for copying a text format pattern. In one embodiment of the present invention there is a method for copying a text format pattern, including: receiving a selection of a sample object from a user, the sample object including multiple sample paragraphs of which at least two sample paragraphs have different format patterns; receiving a format copying instruction of from the user, the format copying instruction indicating reformatting a target object with the format pattern of the sample object, where the target object contains multiple target paragraphs; determining a corresponding relationship of the format pattern of the sample paragraphs with the target paragraphs; and applying the format pattern of the sample paragraphs to the target paragraphs in accordance with the corresponding relationship.

Abstract: Active content is deterministically rendered in a stable format that is independent of any particular targeted environment, which the active content may subsequently be rendered to. Environmental and dynamic dependencies are removed from a specification associated with the active content for purposes of producing a stable and consistent specification for the active content. The stable and static specification is used to subsequently render the active content into the stable format for any targeted or desired environment.

Abstract: An indication to render a webpage is received. The webpage includes two or more frames and the two or more frames are rendered in a first order. A second order from a user is received. The webpage is rendered. The two or more frames of the webpage are rendered in the second order.

Abstract: A computer system may identify a first and second predefined color that are found in a Cascading Style Sheets (CSS) style sheet for a webpage. The computer system may receive an object to be embedded in the webpage. The computer system may calculate a color similarity score for each of the predefined colors. The computer system may compare the color similarity scores for the predefined color and determine, based on the comparison, which predefined color is the mask color. The computer system may then mask the object using the mask color.

Abstract: A computer system may identify a first and second predefined color that are found in a Cascading Style Sheets (CSS) style sheet for a webpage. The computer system may receive an object to be embedded in the webpage. The computer system may calculate a color similarity score for each of the predefined colors. The computer system may compare the color similarity scores for the predefined color and determine, based on the comparison, which predefined color is the mask color. The computer system may then mask the object using the mask color.

Abstract: The present disclosure provides an information collection method. Aspects of the disclosure provide a method for collecting information. The method includes receiving, at a terminal device having a user account in a social group that is established by a communication service, a trigger message that is sent by a specific user account of the social group to members of the social group. The trigger message includes a prompt text and a jump instruction to a page for collecting specific information. Further, the method includes generating a text link associated with the jump instruction based on the prompt text, displaying the text link on an interface page for the communication service and executing the jump instruction to display the page for collecting the specific information when a trigger event with respect to the text link is detected.

Abstract: A computer-aided display for menu structures monitors use of the display elements to adjust the menu hierarchy. Promotion through the hierarchy is sensitive to an adjustable historical period. Hierarchy and information from the historical period can be captured in a single number for each menu element.

Abstract: An indication to render a webpage is received. The webpage includes two or more frames and the two or more frames are rendered in a first order. A second order from a user is received. The webpage is rendered. The two or more frames of the webpage are rendered in the second order.