Abstract: A method, system and product for predicting impact of workload migration. The method comprising: obtaining a utilization pattern of a workload that is being executed on a first platform; generating a synthetic workload that is configured to have the utilization pattern when executed on the first platform; executing the synthetic workload on a second platform; and identifying a change in performance between execution of the synthetic workload on the first platform and between execution of the synthetic workload on the second platform in order to provide a prediction of an impact of migrating the workload from the first platform to the second platform.

Abstract: An analysis system includes: analysis engines each executing predetermined analysis; an analysis executing part controlling operation of the analysis engines and causing the analysis engines to execute analysis; and a processing performance control part controlling processing performance of the analysis engines. The processing performance control part is configured by a processing module that is independent of the analysis engines and the analysis executing part and that can be installed into the analysis system, and configured to be invoked by the analysis executing part to detect state information representing a state of a specific one of the analysis engines and execute a previously set process based on the detected state information.

Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.

Abstract: Methods and systems for implementing dynamic rate adjustment for interaction monitoring are disclosed. At an entity, the collection of trace information is initiated according to a first sampling rate. The trace information is indicative of interactions between the entity and one or more additional entities. A second sampling rate is determined based at least in part on information external to the entity. The second sampling rate is determined after the collection of the trace information is initiated at the entity according to the first sampling rate. At the entity, the collection of additional trace information is initiated according to the second sampling rate.

Abstract: A method, a system, and a computer program product for generating test infrastructure for testing of software applications are disclosed. At least one first method associated with an application is determined. A testing version of a second method associated with the application is generated. The first method calls a runtime version of the second method during execution of the application in a runtime environment. The first method is tested using the testing version of the second method in a testing environment associated with the application.

Abstract: A population of devices provides telemetry data and receives software changes or updates. Event buckets for respective events are found. Event buckets have counts of event instances, where each event instance is an occurrence of a corresponding event reported as telemetry by a device. Records of the software changes are provided, each change record representing a software change on a corresponding device. The event buckets are analyzed to identify which indicate an anomaly. Based on the change records and the identified event buckets, correlations between the software changes and the identified event buckets are found.

Abstract: A streams manager monitors data tuples processed by a streaming application represented by an operator graph. The streams manager includes a tuple breakpoint mechanism that allows defining a tuple breakpoint that fires based on resource usage by the data tuple. When the tuple breakpoint fires, one or more operators in the operator graph are halted according to specified halt criteria. Information corresponding to the breakpoint that fired is then displayed. The tuple breakpoint mechanism thus provides a way to debug a streaming application based on resource usage by data tuples.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Abstract: A computer implemented method for identifying program flow in a computer program, executing in a debugger on at least one processor, subsequent to suspending execution of the computer program at a user breakpoint can include suspending execution of the computer program at a first user breakpoint, setting, by the debugger, one or more tracking breakpoints in one or more routines that can continue execution from the first user breakpoint, then resuming execution of the computer program. The method may be continued by suspending execution of the computer program at a second user breakpoint after processing by the at least one processor at least one instruction of the computer program. The method may further include determining whether to provide an indicator to indicate that at least one of the one or more tracking breakpoints was hit during the executing, and providing the indicator in response to determining to provide the indicator.

Abstract: A data processing apparatus includes a request receiving unit that receives a request from a program that causes a device to perform a predetermined process; an emulating unit that emulates a process performed by the device in accordance with the request; an instruction receiving unit that receives an instruction to change a status of the emulating unit from a user; a status changing unit that causes the emulating unit to change the status in accordance with the instruction to change the status; and a storing processing unit that stores, in response to generation of the request or generation of the instruction to change, information indicating the request or information indicating the instruction to change in a first storing unit, wherein the emulating unit emulates the process performed by the device under a status changed by the status changing unit.

Abstract: A computing device is provided that automatically assigns bugs or errors associated with an application program to one or more developers that are best suited to address the bug. The bugs may be detected either at runtime or during a build process. The assignment of a bug to any given developer is based on an analysis of the debug information contained in a log file generated for the application program, as well as the knowledge of which developers worked on the code particularly associated with the detected bug, and/or on the contents of a pre-defined list that associates developers with different parts of the application program.

Abstract: The embodiments described herein include a host that includes an operating system and a storage simulation module in communication with the host. The storage simulation module includes a pseudo-adapter configured to emulate a storage adapter and a pseudo-storage device coupled to the pseudo-adapter, wherein the pseudo-storage device is configured to emulate a storage device. The storage simulation module is configured to simulate an error event for the pseudo-adapter and/or the pseudo-storage device upon receipt of an operation from the operating system.

Abstract: There is provided with a resource allocation apparatus. An attribute indicating a requirement for a data storage resource to be allocated to a plurality of data flows to which the attribute is provided beforehand is acquired. A data flow relationship graph indicating a relationship between the plurality of data flows which potentially lead to access contention in the data storage resource is generated. Based on the attribute and the data flow relationship graph, allocation of the data storage resource to the plurality of data flows is determined such that no access contention occurs.

Abstract: A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules. The firmware module performs the processes when the hardware modules are not able to successfully perform them.

Abstract: The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.

Abstract: Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.

Abstract: Systems and methods for metablock relinking may be provided. A first physical block of a first metablock may be determined to have a different health than a second physical block of a second metablock based on health indicators of the first and second physical blocks. Each of the health indicators may indicate an extent to which a respective one of the first and second physical blocks may be written to and/or erased before the respective one of the first and second physical blocks becomes defective. The first physical block of the first metablock may be replaced with the second physical block of the second metablock based on a determination that the health of the first physical block of the first metablock is different than the health of the second physical block of the second metablock.

Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

Abstract: At least one read operation of at least one object of a data container is initiated. The data container includes an anchor object, a first internal data object and a first garbage collection object, the anchor object comprising a pointer to a versioned structure tree. Thereafter, in response to the at least one incompatible write operation, a second internal data object and a second garbage collection object are created for the data container. The second garbage collection object has a reference to the second internal data object. Subsequently, the second internal data object is installed in the anchor object and the first garbage collection object is passed to a garbage collection process so that space used by the first garbage collection object in a database can be reused. Related apparatus, systems, techniques and articles are also described.

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

Abstract: Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.

Abstract: According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.

Abstract: Systems, methods, and computer programs are disclosed for scheduling tasks in a heterogeneous processor cluster architecture in a portable computing device. One embodiment is a system comprising a first processor cluster and a second processor cluster. The first processor cluster comprises a first shared cache, and the second processor cluster comprises a second shared cache. The system further comprises a controller in communication with the first and second processor clusters for performing task migration between the first and second processor clusters. The controller initiates execution of a task on a first processor in the first processor cluster. The controller monitors a processor workload for the first processor and a cache demand associated with the first shared cache while the task is running on the first processor in the first processor cluster. The controller migrates the task to the second processor cluster based on the processor workload and the cache demand.

Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.

Abstract: A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies.

Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

Abstract: Data and a memory address associated with the data may be received. A hash value of the memory address may be calculated by using a first hash function. The data may be stored at a cache set of a plurality of cache sets of a cache memory based on the hash value calculated from the first hash function. A determination may be made as to whether the storing of the data at the cache set of the plurality of cache sets of the cache memory is associated with a conflict ratio of the cache memory exceeding a threshold ratio. In response to the conflict ratio exceeding the threshold ratio, a second hash value of a second memory address associated with a second data may be calculated by using a second hash function that is different than the first hash function.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing an address in a memory of a switch. One of the systems includes a switch that receives packets from and delivers packets to devices connected to a bus without any components on the bus between the switch and each of the devices, a memory integrated into the switch to store a mapping of virtual addresses to physical addresses, and a storage medium integrated into the switch storing instructions executable by the switch to cause the switch to perform operations including receiving a response to an address translation request for a device connected to the switch by the bus, the response including a mapping of a virtual address to a physical address, and storing, in the memory, the mapping of the virtual address to the physical address in response to receiving the response.

Abstract: Embodiments are disclosed for implementing a priority queue in a storage device, e.g., a solid state drive. At least some of the embodiments can use an in-memory set of blocks to store items until the block is full, and commit the full block to the storage device. Upon storing a full block, a block having a lowest priority can be deleted. An index storing correspondences between items and blocks can be used to update priorities and indicated deleted items. By using the in-memory blocks and index, operations transmitted to the storage device can be reduced.

Abstract: Encryption of virtual disc image is accomplished by increasing the size of a virtual disc to support the inclusion of a master boot record and a decryption program. Encrypting portions of a virtual disc image on the virtual disc, but leaving the boot record and decryption program unencrypted and accessible, where the decryption program will decrypt the encrypted portions if the appropriate cryptographic key is supplied. Subsequent decryption is accomplished by initiating a boot sequence through the master boot record, receiving the appropriate cryptographic key, appropriately ordering the decrypted disc image.

Abstract: A data processing apparatus includes an instruction execution section, a protection control information storage section that stores protection control information that includes first protection information, and second protection information that is independent of the first protection information, an instruction protection information storage section that stores instruction protection information for specifying a partial address space of an instruction address space in which to store instructions that are executable by the instruction execution section, a data protection information storage section that stores data protection information for specifying partial address spaces of a data address space in which to store operands to be usable by the instruction execution section, and a protection violation determination section which, when the first protection information includes a first value, makes a determination as to whether to permit the instruction execution section to access the instruction address space a

Abstract: A storage module, host, and method for securing data with application information are disclosed. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to store data and information about an application that generated the data and allow the data to be read only if information about an application attempting to read the data matches the information about the application that generated the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A method, article of manufacture, and apparatus for efficiently backing up information are disclosed. In an embodiment, this may comprise using a first space reduction method to space reduce data in a client, transmitting the first space reduced data from a client to an intermediate shared storage at a time convenient for the client, using a second space reduction method to space reduce data from the intermediate shared storage, transferring the second space reduced data to a server, and storing the data in a server storage.

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form one or more local event rings and a global event chain. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. Each local event ring involves event ring circuits and event ring segments. In one example, an event packet being communicated along a local event ring reaches an event ring circuit. The event ring circuit examines the event packet and determines whether it meets a programmable criterion. If the event packet meets the criterion, then the event packet is inserted into the global event chain. The global event chain communicates the event packet to a global event manager that logs events and maintains statistics and other information.

Abstract: A mobile device including: a storage device; a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; and a working memory including an input/output (I/O) scheduler and a device driver, the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue, the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue.

Abstract: Aspects of the present disclosure describe automatically changing an output mode of an output device from a first output mode to a latency reduction mode. An initiation signal and the output data may be received from a client device platform or a signal distributor. Upon receiving the initiation signal, the output device may change the output mode from the first output mode to the latency reduction mode. Thereafter, the output device may receive an end latency reduction mode signal. The output device may then revert back to the first output mode. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Controller and method for requesting arbitration of a queue. The controller comprises a coalescing engine for determining a number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied. The method comprises determining the number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied.

Abstract: A microcontroller system is disclosed that includes an access stealing monitor coupled to a bus that is configured to receive a first access request from the bus for a first peripheral, duplicate the first access request, transform the first access request to a second access request on a second peripheral, and transfer the second access request to the bus. In another embodiment, a first peripheral coupled to the bus is configured to receive a first access request from the bus for the first peripheral, duplicate the first access request and transform the first access request to a second access request. A second peripheral coupled to the bus and to the first peripheral is configured to receive the second access request and to respond to the second access request. Methods of access stealing in a microcontroller system are also disclosed.

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

Abstract: A data storage device includes a controller coupled to multiple groups of data storage dies, such as a meta-meta-die. The controller is configured to write data to a first meta-block if a storage size associated with a first group of data storage dies associated with a first priority is greater than or equal to a threshold storage size. The first meta-block includes a respective block of each data storage die of the first group. The controller is further configured to write the data to a second meta-block if the storage size associated with the first group is less than the threshold storage size. The second meta-block includes a respective block of each data storage die of the first group and further includes a respective block of each data storage die of the second group. Each data storage die of the second group is associated with a second priority.

Abstract: A command processor may process a command stream for execution by at least one processor, including storing data associated with a first set of one or more operations in the command stream in a trace buffer, wherein the first set of one or more operations accesses one or more memory locations in memory, and wherein the data include an indication of contents of the one or more memory locations associated with the first set of one or more operations. The command processor may interrupt the processing of the command stream. The command processor may, in response to resuming processing of the command stream subsequent to the interrupting of the processing of the command stream, replay at least a portion of the command stream, including processing a second set of one or more operations of the command stream based at least in part on the data stored in the trace buffer.

Abstract: The present disclosure relates to a method and an apparatus for allocating interruptions in a multi-core system. A method for allocating interruptions in a multi-core system according to one embodiment of the present disclosure comprises: an interrupt load extraction step of extracting interrupt loads of each interruption type; a step of extracting task loads of each core; a weighting factor determination step of determining weighting factors using a difference between task loads of the cores; a step of reflecting weighting factors to extract a converted value of the interrupt load; and an interruption allocation step of allocating interruption types to the cores such that the sums of the converted values of the interrupt loads allocated to each core and the allocated task loads are uniform. According to one embodiment of the present disclosure, interruptions can be allocated such that both task processing and interruption processing can be performed in an efficient manner.

Abstract: A multisite sensing system including two or more analyte sensors, an interface device, and a shared bus. The interface device may be configured to receive a power signal and generate power for powering the analyte sensors and to convey data signals generated by the analyte sensors. The shared bus connected to the interface device and each of the analyte sensors and configured to provide the power generated by the interface device to the analyte sensors and to provide the data signals generated by the analyte sensors to the interface device. The interface device may be an inductive element. The shared bus may be a two wire, multiplexed bus. The analyte sensors may be spatially separated for analyte sensing at least two different locations. The analyte sensors may generate data signals indicative of the presence and/or amount of the same analyte or of one or more different analytes.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.

Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.

Abstract: Methods and devices are provided for determining compliance with standards for at least one of Serial Attached SCSI and Serial Advanced Technology Attachment (SAS/SATA). The device comprises PHY layer logic operable to couple the device with another device, and a control unit. The control unit is operable to direct operations of the PHY layer logic, and to determine that the other device is a SAS/SATA device. The control unit is further operable to perform SAS/SATA protocol compliance testing on the other device to determine a degree of compliance of the other device with SAS/SATA protocol standards, and to alter subsequent communications with the other device responsive to determining that the other device is not fully compliant with SAS/SATA protocol standards.

Abstract: Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.

Abstract: A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.