Abstract: The method according to the invention deals with controlling of graphical elements of a display having a plurality of pixels with one or more processors, the method including defining by said one or more processors a graphical main shape on the display representing a total volume of a root node, defining by said one or more processors within the graphical main shape a number of graphical node shapes on the display, the number of node shapes being at least one and each node shape representing a volume of a parent node, wherein the volumes of all parent nodes sum up to the total volume, controlling by said one or more processors the pixels of the graphical main shape to visually present the graphical main shape on the display, redefining the graphical node shapes in response to receiving an input signal from an input device indicating a selection of a parent node, indicating a manipulating of a volume of a selected node shape or indicating an opening of a particular parent node.

Abstract: Configuring a graphical user interface according to a user's preferences is described herein. Systems and methods are provided for generating a dynamically varying themed interface for a user environment; defining appropriate color palettes associated within a brand definition of the user environment; and, providing one or more configuration settings for the rendering engine.

Abstract: Systems and techniques for accelerating relationship visualizations from data objects are described herein. The configuration and/or display of a relationship matrix may be automatically determined from the data objects. The relationship matrix may display relationships through gradient, hue, color, and/or saturation. The relationship matrix may be navigable and/or interactive to accelerate relationship visualizations.

Abstract: A display device includes a processing unit including a control circuit, a display panel that displays contents of a page and a horizontal scroll bar including a button image and a groove image indicating a slide range of the button image, and a touch panel that receives an operation to a displayed image. The processing unit moves a display area of the display panel in a horizontal direction based on a movement direction and a movement amount of the button image. The processing unit determines a contents end position that is a rightmost position of the contents in a band area having an upper end and a lower end respectively corresponding to an upper end and a lower end of the display area of the display panel, and controls the display panel to display the contents end position.

Abstract: A system, method and computer program product for guiding hand-drawing of diagrams including text and non-text elements on a computing device are provided. The computing device has a processor and a non-transitory computer readable medium for detecting and recognizing hand-drawing diagram element input under control of the processor. Display is performed, on an interactive display of the computing device, of a guide element associated with at least one diagram element of displayed handwriting diagram input. The guide element is configured with a depiction of the at least one diagram element in recognized form.

Abstract: The embodiments herein provide a method for performing an operation in an electronic device. The method includes displaying at least two objects. Further, the method includes identifying a gesture on the at least two objects. Further, the method includes displaying at least one content for performing at least one operation relative to the at least two objects according to a level corresponding to the gesture among a plurality of levels.

Abstract: A method for dynamically generating a personalized handwriting character font includes inputting a plurality of handwriting sequentially through an input interface. Each handwriting describes a character. Then, the positions of strokes of characters in the input interface described by the plurality of handwriting are identified. Next, font characteristics of the characters are determined according to the positions of strokes in the input interface. A personalized handwriting character font characteristic is determined according to the font characteristics. Finally, a new character font file with a personalized handwriting character font is generated according to the personalized handwriting character font characteristic.

Abstract: The present disclosure relates generally to technologies for sensor networks, machine-to-machine (M2M), machine-type communication (MTC), and Internet of things (IoT). The present disclosure may be used in intelligent services (smart home, smart building, smart city, smart car, or connected car, health-care, digital education, retail business, security and safety-related services, etc.), or the like, without limitation.

Abstract: An apparatus for generating a graphical representation of a motion input applied to one or more sensors includes a touch input display screen and a motion input capture module receptive to data corresponding to the motion input applied to and detected by the one or more sensors. A graphical user interface is generated on the touch input display screen with a view of a virtual three-dimensional space displayed thereon, and has a virtual space viewing mode and a brush stroke input mode. In the virtual space viewing mode, the view of the virtual three-dimensional space is adjustable in response to motion input. In the brush stroke input mode, a stroke path defined by a plurality of position points within the virtual three-dimensional space and derived from data corresponding to the motion input is generated.

Abstract: An electronic device is provided. The electronic device includes an input interface configured to receive a user input, a memory configured to store an application using an item, a display, and a processor. The processor is configured to obtain the user input through the input interface while an execution screen of the application is output, determine a change screen based on a variation of the user input, wherein the change screen is configured to be outputted when the user input is released, and while the user input is maintained, output a preview which includes at least part of the change screen to the display.

Abstract: A method and computing system for providing, using one or more computing devices, a synchronous communication session for a plurality of users of a social network. A first video stream of a first user of the plurality of users is rendered within a primary viewing field associated with the synchronous communication session. At least a second video stream of at least a second user of the plurality of users is rendered within the primary viewing field associated with the synchronous communication session.

Abstract: The electronic device has a touch-sensitive display, one or more processors, and memory storing one or more programs configured to be executed by the one or more processors. The one or more programs include instructions for displaying a first keyboard comprising a first set of keys corresponding to a set of characters associated with a first language and a first designated key displayed at a location and associated with a first function. In response to receiving a selection to display a second keyboard, the one or more programs include further instructions for displaying the second keyboard, comprising a second set of keys and a second designated key displayed at the location and associated with a second function different from the first. The second function toggles between keyboards. Selection of any of the second set of keys displays one or more characters corresponding to a second language different from the first.

Abstract: Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.

Abstract: An electronic system includes: a storage device, configured to receive an interface command including: an interface control unit, a first CPU, coupled to the interface control unit, configured to execute a logical block address (LBA) command, a second CPU, coupled to the interface control unit, configured to execute a key-value command, and a non-volatile storage, coupled to the volatile memory, the first CPU, and the second CPU configured to process the LBA command and the key-value command independently and concurrently; wherein: the first CPU or the second CPU are configured to compile a detailed status after completing the LBA command or the key-value command; and the interface control unit, connected to a device coupling structure, is configured to respond to the interface command by sending the detailed status to a device driver.

Abstract: The present invention provides a data storage device including a flash memory and a random access memory. The flash memory has a data mapping table arranged to record a plurality of mapping relationships between the logical addresses and the physical addresses of a plurality of pages of the flash memory. The data mapping table is divided into a plurality of data mapping sets. The random access memory has a cache area, a sequential-order table, a reverse-order table and a cache-area mapping table. The cache area stores part of the data mapping sets. The cache-area mapping table records the set indexes of the data mapping sets of the cache area. The sequential-order table records the order that the data mapping sets are read from the cache area. The reverse-order table records the opposite order that the data mapping sets are read from the cache area.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access data from a data storage memory through the first and second memory devices.

Abstract: The subject matter disclosed herein relates to out of memory error handling in a database system. A database operation can be received by an in-memory database. The database operation can be for a database object stored in a database table that can be represented as a plurality of pages that can be persisted in a page chain. The in-memory database can reserve out of memory space sufficient to load a predetermined number of pages in the page chain into memory. The in-memory database can iteratively process each page in the page chain until completion of the database operation. The iterative process can include loading the page from persistence into memory of the in-memory database, performing at least a portion of the database operation using the loaded page, and unloading the page from the memory of the in-memory database. Related apparatus, systems, techniques, and articles are also described.

Abstract: In one aspect, a storage management system of a storage controller having a set of processor nodes, in response to a request by a user to add a storage pool to the storage system, adds a set of subpools of storage, one for each processor node of the storage controller. The resultant storage capacity is the combination of the individual storage capacities of each subpool of the set of storage subpools. Accordingly, each subpool of the set is automatically assigned to a different processor node. In this manner, the user may be relieved of the task of manually assigning storage pools to processor nodes. In addition, load balancing between the processor nodes may be facilitated. Other aspects and features are described herein.

Abstract: A method, computer program product, and system maintain virtual product data (VPD) in a computer system. The method includes a processor obtaining a first indicator, which may indicate a repair has commenced in a computer system or an initial program load has commenced in the computer system, accessing VPD related to the computer system, and duplicating the VPD to create a copy of the VPD. The processor stores the copy of the VPD in at least one computing element internal to the processor or accessible to the processor via a communications network. The processor obtains a second indicator that indicates that the initial program load is complete or that the repair process is complete, compares the VPD to the copy of the VPD, and determines whether to replace at least a portion of the VPD with at least a portion of the copy of the VPD.

Abstract: A data storage device includes a controller; and a nonvolatile memory device including a plurality of memory blocks, and suitable for erasing a memory block selected from among the plurality of memory blocks, wherein the controller is suitable for managing the memory block through an erase prohibition list so that at least one predetermined erase cycle is ensured for the memory block.

Abstract: An example device includes at least one memory unit, the memory unit including a unit header and at least one data segment. Each data segment may include a data segment header area and at least one payload region. The unit header may include information related to a starting location of each data segment and a size of each data segment.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.

Abstract: In one aspect, a multiple mode data structure can be utilized by a storage management system to provide a host representation role in one mode, and represent both a host and a host port in another mode. In one embodiment, in a first mode, the data structure has an undefined host port name attribute and a defined host name attribute to represent a host identified by the defined host name attribute. In the first mode, the data structure is restricted from representing a host port in the storage management system when the host port name attribute is undefined. In a second, unrestricted mode, the multiple mode data structure can represent both a host as well as a host port when a host port name attribute is defined. In one embodiment, the multiple mode data structure can also represent a host cluster. Other aspects are described.

Abstract: A network attached storage management appliance that can be inserted into a pre-existing network. The appliance sits between an end user and the available storage and optimizes performance and storage through acceleration of data, migration of data, compression of data, deduplication of data, and expansion of storage. The device moves data between lower- and higher-performance storage, with frequently accessed data sitting in higher-performance storage and infrequently accessed data sitting in lower-performance storage.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Capacity planning in a multi-array system that includes a plurality of storage arrays, includes: receiving data representing projected capacity utilization for at least one of the plurality of storage arrays, where the projected capacity utilization is generated in dependence upon capacity utilization patterns of a plurality of other storage arrays; and presenting the projected capacity utilization.

Abstract: In an embodiment, a processor includes hardware processing cores, a cache memory, and a compression accelerator comprising a hash table memory. The compression accelerator is to: determine a hash value for input data to be compressed; read a first plurality of N location values stored in a hash table entry indexed by the hash value; perform a first set of string searches in parallel from a history buffer using the first plurality of N location values stored in the hash table entry; read a second plurality of N location values stored in a first overflow table entry indexed by a first overflow pointer included in the hash table entry; and perform a second set of string searches in parallel from the history buffer using the second plurality of N location values stored in the first overflow table entry. Other embodiments are described and claimed.

Abstract: The present invention overcomes deficiencies inherent in data compression in computer systems running the Microsoft Windows operating system, and accelerates disk read speeds.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device commonly coupled to the plurality of the plurality of first memory devices, and including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes a system main memory including first and second memories, wherein the first memory includes a cached subset of the second memory and the second memory includes a cached subset of a data storage memory; a processor suitable for executing an operating system (OS) and an application to access the data storage memory through the system main memory, wherein the system main memory is separated from the processor; a memory controller suitable for transferring data between the system main memory and the processor; and a write buffer suitable for buffering write data, based on which the second memory is updated.

Abstract: A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a system main memory including a first memory device and a second memory device, wherein each of the first and second memory devices maintains latency information thereof; a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the system main memory, wherein the system main memory is separated from the processor and the processor and the first and second memory devices are electrically coupled to one another through a common bus; and a memory controller suitable for transferring data between the system main memory and the processor.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access data storage memory through the first and second memory devices.

Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.