Abstract: A cache is sized using an ordered data structure having data elements that represent different target locations of input-output operations (IOs), and are sorted according to an access recency parameter. The cache sizing method includes continually updating the ordered data structure to arrange the data elements in the order of the access recency parameter as new IOs are issued, and setting a size of the cache based on the access recency parameters of the data elements in the ordered data structure. The ordered data structure includes a plurality of ranked ring buffers, each having a pointer that indicates a start position of the ring buffer. The updating of the ordered data structure in response to a new IO includes updating one position in at least one ring buffer and at least one pointer.

Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller electrically connected to the nonvolatile memory. The controller receives, from a host, a write command including a logical block address. The controller obtains a total amount of data written to the nonvolatile memory by the host during a time ranging from a last write to the logical block address to a current write to the logical block address, or time data associated with a time elapsing from the last write to the logical block address to the current write to the logical block address. The controller notifies the host of the total amount of data or the time data as a response to the received write command.

Abstract: A file access method and apparatus, and a storage system are provided. After receiving a file access request from a process, a first physical address space is accessed according to a preset first virtual address space and a preset first mapping relationship between the first virtual address space and the first physical address space, where the first physical address space stores a file system. After obtaining an index node of a target file from the first physical address space according to a file identifier of the target file carried in the file access request, a file page table of the target file is obtained according to file page table information. The file page table records a second physical address space in the first physical address space. The target file is accessed according to the second physical address space.

Abstract: A file access method and apparatus, and a storage system are provided. After receiving a file access request including a file identifier, first physical address space is accessed according to first virtual address space and a first mapping relationship between the first virtual address space and the first physical address space storing a file system. After obtaining, from the first physical address space, an index node of an object file indicated by the file identifier, a file page table is obtained according to information included in the index node, where the file page table records second physical address space of the object file. Then, second virtual address space is allocated to the object file. After establishing a second mapping relationship between the second physical address space and the second virtual address space, the object file in the second physical address space is accessed according to the second virtual address space.

Abstract: A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.

Abstract: The disclosed embodiments provide a system for processing data. During operation, the system obtains an attribute of a stack trace of a software program. Next, the system uses the attribute to select an address-translation instance from a set of address-translation instances for processing the stack trace. The system then provides the stack trace to the selected address-translation instance for use in translating a set of memory addresses in the stack trace into a set of symbols of instructions stored at the memory addresses.

Abstract: Several embodiments include a method of operating a cache appliance comprising a primary memory and a secondary memory. The primary memory can implement an item-wise cache and the secondary memory can implement a block cache. The cache appliance can record an access history of a data item in the item-wise cache. The cache appliance can determine, by evaluating the access history of the data item, whether to store the data item in the block cache.

Abstract: An aware cache replacement policy increases the length of in-page bursts of cache eviction memory requests and promotes bank-rotation to reduce the likelihood of memory bank-conflicts as compared to other cache replacement policies. The aware cache replacement policy increases the amount of valid data on the memory bus and reduces the impact of main memory precharge and activate times by evicting cache blocks in bursts based on temporal and spatial locality according to requesting thread and/or memory structure.

Abstract: Several embodiments include a method of operating a cache appliance comprising a primary memory implementing an item-wise cache and a secondary memory implementing a block cache. The cache appliance can emulate item-wise storage and eviction in the block cache by maintaining, in the primary memory, sampling data items from the block cache. The sampled items can enable the cache appliance to represent a spectrum of retention priorities. When storing a pending data item into the block cache, a comparison of the pending data item with the sampled items can enable the cache appliance to identify where to insert a block containing the pending data item. When evicting a block from the block cache, a comparison of a data item in the block with at least one of the sampled items can enable the cache appliance to determine whether to recycle/retain the data item.

Abstract: Disclosed are systems and methods for managing a browser cache. An example method comprises storing in a browser cache on a user device information of web pages visited by a user during one or more web browsing sessions; determining logical relationships among the web pages stored in the cache; associating the web pages with one or more clusters based on the determined logical relationships; upon detecting a usage size of the cache equal to or exceeding a threshold value, identifying information associated with the one or more clusters in the cache; determining a web page or a cluster of web pages to be deleted from the cache based on the identified information; and deleting from the cache one or more web pages based on the identified information associated with each of the one or more clusters.

Abstract: Systems comprising a processor and a dynamic random access memory (DRAM). The DRAM comprises a programmable intelligent search memory (PRISM).

Abstract: A system is described to provide protection key access control in a system whose operating system and processor were not designed to provide a protection key memory access control mechanism. Such a system can be applied to an emulator or to enable a system that executes native applications to be interoperable with a legacy system that employs protection key memory access control.

Abstract: A hard drive disk indicator processing apparatus includes first and second processors. The first processor includes first, second and third communication interfaces. The first communication interface receives at least one serial general purpose input/output signal from a motherboard. The second communication interface receives a plurality piece of hard drive disk status information for responding to a plurality of hard drive disk statuses of hard drive disks. The third communication interface outputs serial information. The second processor includes fourth and fifth communication interfaces. The fourth communication interface is coupled to the third communication interface and receives the serial information. The fifth communication interface is coupled to a plurality of hard drive disk indicators. The first processor generates the serial information according to the at least one serial general purpose input/output signal.

Abstract: An electronic apparatus includes an interface unit disposed in the housing to wirelessly communicate with a wireless device disposed inside the housing, an internal wireless device being the wireless device inside the housing, having a sub-housing a sub-housing containing a circuit board, a semiconductor chip unit mounted on the circuit board, and an internal wireless interface unit mounted on the circuit board and electrically connected to the semiconductor chip unit, and a controlling/processing unit disposed in the housing configured to control the interface unit to wirelessly communicate with the internal wireless interface unit of the internal wireless device and to transmit or receive data between the interface unit and the internal wireless device when the internal wireless device exists in the housing.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes encoding virtual GPIO signals or messages into a data packet, determining a maximum latency requirement for transmitting the data packet over the communication link, providing a command code header indicating a packet type to be used for transmitting the data packet over the communication link, and transmitting the command code header and the data packet over the communication link in a packet selected to satisfy the maximum latency requirement. A protocol for transmitting the data packet may be determined based on the maximum latency requirement and one or more attributes of protocols available for use on the communication link. In one example, the communication link includes a serial bus and the available protocols include I2C, I3C, and/or RFFE protocols.

Abstract: A host integrated circuit is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.

Abstract: Audio bus interrupts are disclosed. In one aspect, a new command (referred to herein as a Slave Interrupt Status command) is provided using a reserved Opcode within the SOUNDWIRE protocol. In response to a Ping Request by a slave, a master generates a PING command. The slave that generated the Ping Request sets a bit in a Ping Response according to the existing SOUNDWIRE protocol. However, instead of iteratively reading from each slave, the master uses the Slave Interrupt Status command to interrogate the requesting slave more thoroughly. In response to the Slave Interrupt Status command, the slave provides a more robust response that indicates interrupt requesting status of all registers within the slave that could generate an interrupt. Thus, the master is provided a complete list of which registers generate the original Ping Request and can act accordingly to address issues that generate the interrupt.

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

Abstract: An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O) adapter in a microserver chassis having a plurality of compute nodes and a shared storage resource, policy contexts prescribing storage access parameters of respective compute nodes and enforcing the respective policy contexts on I/O operations by the compute nodes, in which respect a particular I/O operation by any compute node is not executed if the respective policy context does not allow the particular I/O operation. The method further includes allocating tokens to command descriptors associated with I/O operations for accessing the shared storage resource, identifying a violation of any policy context of any compute node based on availability of the tokens, and throttling I/O operations by other compute nodes until the violation disappears.

Abstract: Generally discussed herein are devices and methods for media agnostic (MA) universal serial bus (USB) device enumeration. A device can include a transceiver and processing circuitry to perform a first enumeration process including the transceiver and processing circuitry to determine that throughput is denied based on a throughput negotiation performed in response to receiving a new device connection notification from an MA USB device attempting to communicate with the MA USB host, in response to a determination the throughput is denied, monitor the throughput available on the MA USB host to determine whether the throughput available on the MA USB host has increased, generate a throughput change notification in response to a determination the throughput available on the MA USB host has increased, and initiate a second enumeration process in response to a determination the throughput available on the MA USB host has increased.

Abstract: Disclosures are a processing device, a display device, and a multimedia system. The processing device can transmit a control command through a first wireless USB module. The display device can receive the control command through a second wireless USB module to control a multimedia player. The multimedia system can be designed in a distributed manner, and include the processing device according to the disclosure, and the display device according to the disclosure, and the control command can be transmitted wirelessly between the processing device and the display device. The multimedia system according to the embodiment of the disclosure can be designed in a distributed manner, and structured simply so that the components of the multimedia system can be connected conveniently. If the multimedia system needs to be upgraded in hardware, only the processing device or the display device will be replaced without dissembling the components in the multimedia system.

Abstract: The present disclosure describes a peripheral device. The peripheral device includes a device communication port to communicatively couple with a computer communication port on a computer. The peripheral device includes an automatic latch to mechanically secure the peripheral device to the computer by applying pressure in a direction that connects the device communication port and the computer communication port. The peripheral device includes a ground retention clip, to establish surface contact with an exterior surface of the computer to electrically ground the peripheral device.

Abstract: A method to enable a vehicle's embedded USB Host system to connect to multiple mobile devices through a USB Hub, regardless of whether the mobile devices are configured to act as USB Hosts or USB Devices, without OTG controllers or additional vehicle wiring, or inhibiting the functionality of any consumer devices connected to the same USB Hub. Preferably, the method is configured to provide that no additional cabling is required, and no hardware changes are required to be made to the HU. The method can be employed between a vehicle's embedded USB Host, USB Hub and at least one consumer accessible USB port. In the case where the consumer device is acting as a USB Host, signals between the consumer device and the vehicle's embedded USB Host are processed through a USB bridge, thereby rendering the consumer device compatible with the vehicle's embedded USB Host.

Abstract: A modular computer system includes a chassis with receiving bays, arranged in the region of a first housing side, for the reception of corresponding functional modules. Furthermore, the modular computer system includes at least one first control panel arranged on a second housing side and having control elements. The at least one control panel is coupled to connections of a first receiving bay and of a second receiving bay. At least one first subgroup of the control elements is assigned to the first receiving bay and a second subgroup of the control elements is assigned to the second receiving bay. The modular computer system is configured to transmit module-specific control data between the first subgroup of the control elements and a functional module received in the first receiving bay and between the second subgroup of the control elements and a functional module received in the second receiving bay.

Abstract: According to some aspects, a network interoperability device is provided, comprising a first interface configured to electrically couple to one or more inter-integrated circuit (I2C) devices via an I2C bus, a second interface configured to electrically couple to a data input port and a distinct data output port of a non-I2C transceiver, and a control circuit electrically coupled to the first and second interfaces and configured to control communication of an I2C frame between the I2C bus and the non-I2C transceiver.

Abstract: A PCB apparatus, a module board, and a method for function extension is disclosed. The PCB apparatus includes a substrate for PCB design, and further includes: at least one module board, integrated with a performance enhancing module; and a connector, the module board being connected to the substrate through the connector, such that the module board and the substrate perform signal transmission.

Abstract: Systems, methods, and apparatus for implementing hardware flow control between devices coupled through a serial peripheral interface. A method for transmitting information using a serial peripheral interface includes initiating an exchange of data over one or more data lines of a serial peripheral interface bus by asserting a first voltage state on a slave select line, transmitting data and clock signals over the serial peripheral interface bus while the slave select line remains at the first voltage state, refraining from transmitting data and clock signals over the serial peripheral interface bus when the slave select line transitions to a second first voltage state, receiving data at a slave device into a receive buffer while the slave select line remains at the first voltage state, and asserting the second voltage state on the slave select line when occupancy of the receive buffer reaches or exceeds a threshold occupancy level.

Abstract: In an embodiment, a Physical Layer Interface Transceiver (PHY) is configured to operate in accordance with a Universal Serial Bus 2.0 (USB2) protocol. The PHY includes a High Speed module configured to exchange data via differential data lines during High Speed mode. At least one switch is set to an open state in response to a transition of the PHY from a chirp mode to the High Speed mode to capacitively couple the differential data lines to one or more components of the High Speed module via a set of capacitors.

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

Abstract: A serial peripheral interface (SPI) module includes a transceiver including a clock line, a data line and at least one slave select line. The module also includes an interface circuit configured to monitor the slave select line and assert a fault based upon an incorrect de-assertion of the slave select line.

Abstract: A method and system for transmitting a USB signal based on an FFC are disclosed. The method includes: presetting an FFC combination between a host and a device, the FFC combination including multiple FFCs as well as a first-stage USB signal compensator and a second-stage USB signal compensator for connecting the FFCs; and when a USB signal is transmitted between the host and the device, amplifying the USB signal by the first-stage USB signal compensator, and adjusting by the second-stage USB signal compensator the amplified USB signal to satisfy the requirements of the device. Long-distance transmission of a USB signal by using an FFC is realized according to the embodiments of the present disclosure.

Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

Abstract: Chaining virtual network functions is provided using a remote direct memory access in software-defined data centers in order to minimize latency. A data packet is processed using a virtual network function of the computer. The data packet is inserted into a shared memory pool for processing via remote direct memory access by a remote computer according to a network function of the remote computer that corresponds to the network function of the computer. The data packet is sent to a target destination device via a network in response to the remote computer marking the data packet as processed in the shared memory pool.

Abstract: An example method for adaptively coalescing remote direct memory access (RDMA) acknowledgements is provided. The method includes determining one or more input/output (I/O) characteristics of RDMA packets of a plurality of queue pairs (QPs) on a per-QP basis, each QP identifying a respective RDMA connection between a respective first compute node and a respective second compute node. The method further includes determining an acknowledgement frequency for providing acknowledgements of the RDMA packets on a per-QP basis (i.e., a respective acknowledgement frequency is set for each QP) based on the determined one or more I/O characteristics for each QP.

Abstract: Provided, are a four-dimensional n n-equilibrium hyperchaotic system and analog circuit, based on the five simplest three-dimensional chaotic systems; an operational amplifier (U1), an operational amplifier (U2), and, resistor and capacitor are used to constitute an inverting adder and an inverting integrator; multipliers (U3) and (U4) are used to perform multiplication operations; an 8V DC power supply is used for constant input: the operational amplifier (U1) and operational amplifier (U2) use LF347N, and the multipliers (U3) and (U4) use AD633JN; the operational amplifier (U1) is connected to the operational amplifier (U2) and the multiplier (U3): the operational amplifier (U2) is connected to the multiplier (U4), the DC power supply, and the operational amplifier (U1); the multiplier (U3) is connected to the operational amplifier (U1); the multiplier (U4) is connected to the operational amplifier (U2); the DC power supply is connected to the operational amplifier (U2); on the basis of the five simplest th

Abstract: A novel approach provides accurate estimation of the parameter a of a Fractional Fourier Transform (FrFT). A value of a may be selected for which the Wigner Distributions (WDs) of a signal-of-interest (SOI) and interference overlap as little as possible. However, instead of computing the WD for each signal, the FrFT may be computed for each WD, recognizing that the projection of the WD of a signal onto an axis ta is the energy of the FrFT along the same axis. Since the technique computes a using the SOI and a measure of the interference separately, significant improvements can be made in the estimate, especially at low signal-to-noise ratio (SNR). Once the estimate is obtained, a reduced rank filter may be applied to remove the interference, since minimum mean-square error (MMSE) approaches will again fail when using the low sample support required of non-stationary environments. The technique is not only computationally more efficient than MMSE, but far more robust as well.

Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.

Abstract: According to some embodiments, matrix A data may be loaded into a temporary, unordered starting representation that contains coordinates and values for each element of matrix A. Z-curve ordering of matrix A may be performed to create a two-dimensional density map of matrix A by counting matrix elements that are contained in logical two-dimensional block cells of a given size. A quad-tree recursion may be executed on the two-dimensional density map structure in reduced Z-space to identify areas of different densities in the two dimensional matrix space. An adaptive tile matrix representation of input matrix A may then be created. According to some embodiments, an adaptive tile matrix multiplication operation may perform dynamic tile-granular optimization based on density estimates and a cost model.

Abstract: A system for performing tensor decomposition in a selective expansive and/or recursive manner, a tensor is decomposed into a specified number of components, and one or more tensor components are selected for further decomposition. For each selected component, the significant elements thereof are identified, and using the indices of the significant elements a sub-tensor is formed. In a subsequent iteration, each sub-tensor is decomposed into a respective specified number of components. Additional sub-tensors corresponding to the components generated in the subsequent iteration are formed, and these additional sub-tensors may be decomposed further in yet another iteration, until no additional components are selected. The mode of a sub-tensor can be decreased or increased prior to decomposition thereof. Components likely to reveal information about the data stored in the tensor can be selected for decomposition.

Abstract: Techniques to provide significance for statistical tests are described. An apparatus may comprise a data handler component to receive a real data set from a client device, the real data set to comprise data representing at least one measurable phenomenon, a statistical test component to receive a computational representation arranged to generate an approximate probability distribution for statistics of a statistical test based on a parameter vector, the statistics of the statistical test to follow a probability distribution, generate statistics for the statistical test using the real data set, generate the approximate probability distribution of the computational representation, and a significance generator component to generate a set of statistical significance values for the statistics through interpolation using the approximate probability distribution, the set of statistical significance values comprising one or more p-values. Other embodiments are described and claimed.

Abstract: A historian interface system provides a graphical representation of tags that represent attributes of a continuous process. A historian system stores the tags and metadata values describing the tags. A display device coupled to the historian system via a communication network displays graphical representations of the tags via display panels and receives selections of the tags. The historian system contextualizes selected tags based on the metadata values describing the selected tag and determines an optimal visualization scheme for the selected tags. The display device displays graphical representations of values of the tags and dynamically determines optimal grouping of the tags based on properties of the display device.

Abstract: A manner of facilitating document presentation that may be used to advantage, for example, by a presenter in a meeting room or auditorium setting. A document-presentation system includes a control server that receives a document-presentation indication, for example from a presenter device or another apparatus in a meeting room or associated with a meeting. The control server communicates with the presenter, or user, and determines the document or documents to be presented and a location from which they may be obtained. The control server then sends a presentation notice to a selected render server, which downloads and renders the document. The render server renders the document to a frame buffer in local memory, encodes the pixels read from the frame buffer, and streams the encoded pixels to an adapted display device in a selected location. The render server communicates with the user via the presenter device to start, control, and terminate the presentation.

Abstract: Embodiments of the present disclosure provide a cell configuration and presentation method, and a terminal. The method includes: in response to a cell configuration request sent by a terminal device, selecting, from a local cell style library, cell configuration parameters of a plurality of cells; and sending the selected cell configuration parameters to the terminal device, such that the terminal device draws cell images according to the cell configuration parameters. With the technical solutions of the present disclosure, configuration parameters of cells may be flexibly set on a server and cells can be flexibly drawn on a terminal device for presentation.

Abstract: Examples of the systems and methods described herein relate to methods, systems, and apparatus for automatically detecting layouts or web pages and/or extracting information from the web pages, based on the detected layouts. An example computer-implemented method includes: loading a web page; identifying one or more candidate elements on the web page according to at least one of a padding constraint, a grouping constraint, and a size constraint; determining a plurality of features for the one or more candidate elements, the features including at least one of a dimension feature, a content feature, and a background feature; providing the plurality of features as input to one or more classifiers; and receiving as output from the one or more classifiers an identification of one or more information elements on the web page, the information elements including information of interest to one or more users.

Abstract: A computer-implemented system and method of operating a web-site that provides accounts for respective users is disclosed. The method comprises: receiving an image uploaded from a user to the account of the user, wherein the image is to be incorporated into the account for presentation to other users who have been granted appropriate access to the account, and wherein the image is received as an image data file encoding the image in accordance with a standard image format; converting the image from the standard image format of the image data file into a format in which the image is encoded using a markup language, wherein the markup language is generally used for transmitting a page of content from said web-site to a browser run by a user; and incorporating the image encoded using the markup language into a page of content prior to transmission of the page of content over a telecommunications network to a browser run by a user.

Abstract: Examples disclosed herein relate to replacement text for textual content to be printed. Examples include a covert version of a document including textual content to be printed, the covert version including replacement text having, for each character of a plurality of first characters of the textual content, a corresponding second character having a different semantic meaning than the first character. The covert version also includes an encrypted representation of the textual content.

Abstract: A method for translating a webpage includes receiving an HTML package comprising one or more HTML files and one or more corresponding program integrated information (PII) files, identifying elements corresponding to the one or more HTML files to be translated into a target language, creating a mapping file corresponding to the identified elements, wherein the mapping file indicates a PII file to which each identified element corresponds as well as context information corresponding to each PII file, translating the PII files indicated by the mapping file into a target language to provide translated PII files, and replacing untranslated PII files in the HTML package with corresponding translated PII files to provide a translated package.