Abstract: The invention includes an apparatus for mounting a photovoltaic (PV) module onto a structure where the apparatus includes a base portion, a stud portion, and a coupling portion. The coupling portion includes a male portion that acts as a spring under load and a clip portion that penetrates the PV module frame to create a grounding bond. The apparatus includes a lower jaw, shaped to pry open a groove, and a key portion that can compress to allow for tolerances. The invention further includes a clip with one or more tabs and one or more teeth. The invention further includes a replacement roof tile which includes a support structure with a horizontal flange, a vertical component, a horizontal component, a flashing with an upper surface and a lower surface, and a tile-shaped metal surface having a curvilinear shape that reflects the shapes of adjacent tiles.

Abstract: A solar device alignment system enabling greater adjustment of solar devices during installation is provided. The alignment system enables both translational and rotational adjustments in multiple degrees of freedom, allowing solar device installers to make greater adjustments to allow greater tolerances in installing solar devices and limit the need for extensive and expensive surveying and/or redesign of the installation to account for those tolerances.

Abstract: The disclosed technology describes methods and devices for generating electricity and heat using a parabolic solar panel which employs photo-voltaic and photo-thermal technology. Embodiments include forming a flexible substrate into a parabola. A plurality of flexible photo-voltaic cells is disposed in a grid pattern over the interior surface of the parabola. Photo-reflective mirrors are disposed on the parabola's interior surface in areas not occupied by photo-voltaic cells. A copper pipe is positioned to coincide with the parabola's focal line, so that light rays reflected off the parabola are focused on the copper pipe. Inflow and outflow tubes are attached to opposite ends of the copper pipe. Water or other heat absorbing liquid is circulated through the copper pipe where the liquid absorbs thermal energy of the sunrays reflected from the photo-reflective mirrors. The liquid can be directed to a device which converts the liquid's thermal energy to electricity.

Abstract: A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width. The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.

Abstract: Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.

Abstract: A CMOS cascode amplifier comprises a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal. The CMOS cascode amplifier further comprises a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit. In addition, the CMOS cascode amplifier comprises a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches.

Abstract: The exemplary embodiments include methods, computer readable media, and devices for calibrating a non-linear power detector of a radio frequency device based upon measurements of the non-linear power detector output and the associated power amplifier output level, and a set of data points that characterize a nominal non-linear power detector. The set of data points that characterize the nominal non-linear power detector is stored in a calibration system memory as nominal power detector output data. The measured non-linear power detector outputs, power amplifier output levels, and the nominal power detector output data is used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data are used to develop a calibrated power detector output data set that is stored in the non-linear power detector.

Abstract: Embodiments of the present invention provide a power amplifier, a transceiver, and a base station. The power amplifier includes: a signal control unit, configured to generate a mode control signal and an auxiliary power amplifier control signal; a signal processing unit, configured to separately process an envelope signal and a radio-frequency signal; an envelope modulator, configured to output a fixed voltage or output an amplified envelope signal under the control of the mode control signal; a primary power amplifier, configured to perform amplification processing on the received radio-frequency signal that is input from the signal processing unit; and at least one auxiliary power amplifier, configured to operate or be disabled under the control of the auxiliary power amplifier control signal, and when in an operating state, perform amplification processing on the received radio-frequency signal that is input from the signal processing unit.

Abstract: A controller may be configured to sequentially apply a plurality of switch configurations of a power converter in order to operate the power converter as a differential output converter to switch a polarity of the output voltage, such that: during a charging phase of the power converter, a power inductor is coupled between one of a first terminal and a second terminal of the power source and one of a first terminal and a second terminal of the output load, during a transfer phase of the power converter, at least one of the plurality of switches is activated in order to couple the power inductor between the second terminal of the power source and one of the first terminal of the output load and the second terminal of the output load, wherein the output voltage is a differential voltage between the first terminal and the second terminal.

Abstract: An apparatus that amplifies a signal, includes an amplifier configured to amplify the signal. The apparatus further includes a current supplier configured to supply a periodically variable current to the amplifier.

Abstract: Power amplification system with adjustable common base bias. A power amplification system can include a first transistor having a base coupled to a radio-frequency input. The power amplification can further include a second transistor having an emitter coupled to a collector of the first transistor and having a collector coupled to a radio-frequency output. The power amplification system can include a biasing component configured to apply a fixed biasing signal to the base of the first transistor and to apply an adjustable biasing signal to the base of the second transistor.

Abstract: A Low Voltage Differential Signaling (LVDS) compliant receiver includes a differential amplifier having inputs and outputs. A first input coupling capacitor and second input coupling capacitor are electrically coupled to each of the first differential input and the second differential input, respectively. The receiver also includes a first and a second regenerative feedback latching mechanism, and the first regenerative feedback latching mechanism is electrically coupled between the first input coupling capacitor and the first differential output. The second regenerative feedback latching mechanism is electrically coupled between the second input coupling capacitor and the second differential output.

Abstract: Compression control through power amplifier load adjustment. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a power amplifier bias controller including a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.

Abstract: A bandpass filter that provides a wide gain control range is provided. The bandpass filter performs channel filtering and gain control while maintaining the bandpass characteristic of the bandpass filter. The bandpass filter enables gain control for a wide signal amplitude range while maintaining performance characteristics, such as an out-of-band attenuation ratio capable of high linearity and good pass-band flatness.

Abstract: Aspects of this disclosure relate to systems and methods of performing dynamic impedance tuning. Certain aspects may be performed by or include a dynamic impedance matching network. The dynamic impedance matching network can determine a desired output power for a power amplifier, true power information for the power amplifier, and an output power delivered to a load by the power amplifier. In addition, the dynamic impedance matching network can determine whether the output power satisfies the true power information. Responsive to this determination, the dynamic impedance matching network may modify a load line impedance for the power amplifier using an impedance tuning network.

Abstract: Aspects of this disclosure relate to a mode linearization switch circuit that can adjust an effective impedance provided to an output of an amplifier. In an embodiment, an apparatus includes an amplifier configured to amplify a radio frequency (RF) signal and a mode linearization switch circuit electrically coupled to an output of the amplifier. The mode linearization switch circuit can include a capacitor, a switch in series with the capacitor, and a series LC circuit in parallel with the switch.

Abstract: A chopper stabilzed amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.

Abstract: An electronic amplifier has a feedback circuit with a transconductance amplifier.

Abstract: Methods, media and apparatus for smoothing a time-varying level of a signal. A method includes estimating a time-varying probability density of a short-term level of the signal and smoothing a level of the signal by using the probability density. The signal may be an audio signal. The short-term level and the smoothed level may be time series, each having current and previous time indices. Here, before the smoothing, computing a probability of the smoothed level at the previous time index may occur. Before the smoothing, calculating smoothing parameters using the probability density may occur. Calculating the smoothing parameters may include calculating the smoothing parameters using the smoothed level at the previous time index, the short-term level at the current time index and the probability of the smoothed level at the previous time index. Calculating the smoothing parameters may include calculating the smoothing parameters using breadth of the estimated probability density.

Abstract: In some embodiments, a method for processing an audio signal in an audio processing apparatus is disclosed. The method includes receiving an audio signal and a parameter, the parameter indicating a location of an auditory event boundary. An audio portion between consecutive auditory event boundaries constitutes an auditory event. The method further includes applying a modification to the audio signal based in part on an occurrence of the auditory event. The parameter may be generated by monitoring a characteristic of the audio signal and identifying a change in the characteristic.

Abstract: Adjustment of volume level of a mobile device, by the mobile device without direct or manual user-input, based on one or more contextual parameters detected by the mobile device, such as ambient noise level. A query or other techniques may be used for the adjustment to be ignored. The system may be trained over time by modifying the one or more contextual parameters due to detecting events or sequences of events, such as a user ignoring attenuation in a particular situation.

Abstract: An object of the present invention is to realize a loop through circuit, in an active connector, securely having a preferable mismatching attenuation characteristic and having a preferable signal transmission characteristic, with respect to an input port, an output port, and an internal port, without providing a special circuit outside the connector. A connector base part has the input port inputting an external signal, the output port outputting a loop through signal, and the internal port outputting a signal into a device. First and second matching circuits, an equalizer circuit, a dividing circuit, and a driving circuit are stored in the connector base part. The matching circuit is supplied with an external signal input from the input port. The dividing circuit divides a signal to be input to generate first and second divided signals, and outputs them to the internal port and the output port. The equalizer circuit compensates for a frequency characteristic and/or loss of a signal to be input.

Abstract: In an impedance conversion circuit, a first coil element and a third coil element are arranged coaxially adjacent to each other, and a second coil element and a fourth coil element are arranged coaxially adjacent to each other. By arranging the first and third coil elements in close proximity and arranging the second coil element and the fourth coil element in close proximity in a layering direction, the first coil element is mainly magnetically coupled with the third coil element, and the second coil element is mainly magnetically coupling with the fourth coil element. The first coil element is connected in parallel to the second coil element, and the third coil element is connected in series to the fourth coil element.

Abstract: An embodiment of the present invention provides a method for limiting tuning of a matching network having variable reactive elements coupled to a variable load impedance to at least reduce an undesirable effect caused by an RF signal. Other embodiments are disclosed.

Abstract: An impedance matching device is presented. The device includes an input terminal configured to receive a radio frequency signal, and an output terminal configured to couple to an amplifier. The device includes an impedance prematch network coupled to the input terminal and the output terminal. The impedance prematch network includes a first inductor, such as a first wire bond. The device includes a resonator structure including a second inductor, such as a wire bond, inductively coupled to the first inductor.

Abstract: The disclosure relates to a circuit comprising a balun portion, a balanced side impedance transforming element and an unbalanced side impedance transforming element. The balun portion at least partly transforms the signal between a balanced signal input/output terminal and an unbalanced signal input/output terminal. The impedance transforming elements at least partly alter the impedance presented at the balanced and unbalanced side of the balun. In addition at least one matching transmission element is provided. By separating the role of impedance transformation from balun signal conversion, the useful bandwidth of the circuit can be improved in comparison to a balun that provides both signal conversion and impedance transformation functions.

Abstract: RF multiplexer circuitry includes a first signal path coupled between a first intermediate node and a common node, a second signal path coupled between a second intermediate node and the common node, first resonator circuitry coupled between the first signal path and ground, and second resonator circuitry coupled between the second signal path and ground. The first resonator circuitry is configured to allow signals within a first frequency pass band to pass between the first intermediate node and the common node, while attenuating signals outside of the first frequency pass band. The first resonator circuitry includes a first LC resonator. The second resonator circuitry is configured to allow signals within a second frequency pass band to pass between the second intermediate node and the common node, while attenuating signals outside of the second frequency pass band.

Abstract: Embodiments of resonator circuits and modulating resonators and are described generally herein. One or more acoustic wave resonators may be coupled in series or parallel to generate tunable filters. One or more acoustic wave resonances may be modulated by one or more capacitors or tunable capacitors. One or more acoustic wave modules may also be switchable in a filter. Other embodiments may be described and claimed.

Abstract: A laterally coupled resonator filter device includes a bottom electrode, a piezoelectric layer disposed on the bottom electrode, and a top contour electrode disposed on the piezoelectric layer. The top contour electrode includes first and second top comb electrodes. The first top comb electrode include a first top bus bar and multiple first top fingers extending in a first direction from the first top bus bar. The second top comb electrode includes a second top bus bar and multiple second top fingers extending in a second direction from the second top bus bar, the second direction being substantially opposite to the first direction such that the first and second top fingers form a top interleaving pattern providing an acoustic filter having an apodized shape.

Abstract: A capacitive coupled resonator device includes a substrate, a bottom electrode, a piezoelectric layer, a top electrode, and at least one support frame positioned between the piezoelectric layer and the top electrode and/or positioned between the piezoelectric layer and the bottom electrode. The top electrode includes a first top comb electrode having a first top bus bar and first top fingers extending in a first direction from the first top bus bar, and a second top comb electrode having a second top bus bar and second top fingers extending in a second direction from the second top bus bar, the second direction being substantially opposite to the first direction such that the first and second top fingers form a top interleaving pattern. The at least one support frame includes air-gaps separating at least one of the top electrode and the bottom electrode from the piezoelectric layer, respectively.

Abstract: A surface acoustic wave device includes: comb electrodes that are provided on a piezoelectric substrate, respectively has a plurality of electrode fingers, a plurality of dummy electrode fingers and a bus bar, edges of the electrode fingers of one of the comb electrodes facing the dummy electrode fingers of the other; and an added film that is provided at least under the bus bar of the comb electrodes and under the electrode fingers and the dummy electrode fingers in a first region and is not provided in a crossing region where the electrode fingers of the one of the comb electrodes and the electrode fingers of the other cross each other, the first region being a region between front edges of the dummy electrodes and edges of the dummy electrodes connected to the bus bar and extending in an alignment direction of the electrode fingers.

Abstract: RF circuitry, which includes a first acoustic RF resonator (ARFR), a first compensating ARFR, and a second compensating ARFR, is disclosed. The first compensating ARFR is coupled between a first inductive element and a first end of the first ARFR. The second compensating ARFR is coupled between a second inductive element and a second end of the first ARFR. The first inductive element and the second inductive element are negatively coupled to one another. The first compensating ARFR, the second compensating ARFR, the first inductive element, and the second inductive element at least partially compensate for a parallel capacitance of the first ARFR.

Abstract: The ABB blocks 332, 334, 336, and 318 are configured to process the I/Q signals corresponding to the first or the second HB independently or the I/Q signals corresponding to the LB in cooperation by two. In detail, the first ABB I block 332 and the first ABB Q block 334 operate independently in the 3G/4G mode but they are configured to process the I signal (or Q signal) of the LB in the 2G mode. Likewise, the second ABB Q block 336 and the second ABB I block 318 operate independently in the 3G/4G mode but they are configured to process the Q signal (or I signal) of the LB in the 2G mode. The first ABB I/Q blocks 332 and 334 and the second ABB I/Q blocks 336 and 318 are arranged symmetrically to processing the I/Q signals cooperatively in the 2G mode.

Abstract: Methods for generating a look-up table relating a plurality of complex reflection coefficients to a plurality of matched states for a tunable matching network. Typical steps include measuring a plurality of complex reflection coefficients resulting from a plurality of impedance loads while the tunable matching network is in a predetermined state, determining a plurality of matched states for the plurality of impedance loads, with a matched state determined for each of the plurality of impedance loads and providing the determined matched states as a look-up table. A further step is interpolating the measured complex reflection coefficients and the determined matching states into a set of complex reflection coefficients with predetermined step sizes.

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract: Systems, methods, and other embodiments associated with a continuous-time analog delay device are described. According to one embodiment, a device includes a first terminal connected to an input line to receive an input signal. The device includes a first differential pair of transistors comprising a first transistor and a second transistor, wherein a gate of the second transistor is connected to the first terminal. The device includes a second differential pair of transistors comprising a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to the first terminal. The device includes a first load connected to a drain of the third transistor. The device includes a second load connected to a drain of the fourth transistor. The device includes at least one capacitor connected in parallel between the first load and the second load.

Abstract: A resonant matching circuit (310) for matching a resonant frequency of a wireless power transfer system to a frequency of a power signal comprises a switch (311) connected in parallel with a resonant element (302) of the wireless power transfer system; and a controller (312) connected to the switch (311) and configured to detect a zero-voltage level crossing of a signal flowing through the resonant element (302) and to close the switch (311) for a predefined amount of time upon detection of the zero-voltage level crossing, wherein closing the switch (311) for the predefined amount of time adds any one of an inductive value and a capacitive value to the resonant frequency of a wireless power transfer system.

Abstract: A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.

Abstract: Redundant inverters with multiple inverter stages enable lower operating voltages to be used. For example, the use of multiple inverter stages produces a strong “0” or a strong “1” output signal. The strong output signal facilitates self-oscillation of a ring oscillator at lower voltages.

Abstract: Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.

Abstract: A device includes a first and second inverters each having a signal input, signal output, high voltage supply terminal, and low voltage supply terminal. The signal input of the first inverter is coupled to the signal output of the second inverter, and the signal input of the second inverter is coupled to the signal output of the first inverter. A first transistor has a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to the high voltage supply terminal of the first inverter, and a control terminal coupled to a first node. A second transistor has a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to the high voltage supply terminal of the second inverter, and a control terminal coupled to a second node. First and second bit lines are capacitively coupled to the first and second nodes.

Abstract: Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary.

Abstract: A low voltage AC power controller uses a line coupled capacitor AC to DC converter circuit to obtain energy from AC line power supplied to an AC load and may be used with an external high voltage AC switching device to control power supplied to the AC load. The line coupled capacitor AC to DC converter circuit provides a low power device that senses characteristics of the power supplied to the load and can communicate sensed information and/or receive control information related to the power supplied to the load.

Abstract: In accordance with an embodiment, a method of operating a switching transistor includes turning-off the switching transistor by transferring charge from a gate-drain capacitance of the switching transistor to a charge storage device, and turning-on the switching transistor by transferring charge from the charge storage device to a gate of the switching transistor. Turning off the switching transistor includes hard-switching and turning-on the switching transistor includes soft-switching.

Abstract: A semiconductor device includes: a diode-integrated IGBT element in a same semiconductor substrate having a diode element and an IGBT element driven by a drive signal towards a gate; a sense element having a diode sense element with a current proportional to a current through the diode element and an IGBT sense element with a current proportional to a current through the IGBT element; a switch element connected to a first current pathway through the diode sense element and to a second current pathway different from the first current pathway. The switch element is turned off to control the second current pathway to be discontinuous with the first current pathway when no current flows through the diode sense element, and is turned on to control the second current pathway to be continuous with the first current pathway and apply a current when a current flows through the diode sense element.

Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

Abstract: A drive circuit includes a first output node for connection to the control electrode of the semiconductor switch, a voltage supply circuit, and a first switching stage connected to the voltage supply and a second switching stage connected to the voltage supply. A first resistor network is connected between the first switching stage and the first output node. A second resistor network is connected between the second switching stage and the first output node. A control logic is designed to generate control signals for the guiding of the first switching stage and the second switching stage in such a way that in a first operating mode of the semiconductor switch the semiconductor switch is driven only via the first resistor network, and in a second operating mode of the semiconductor switch the semiconductor switch is driven only via the second resistor network or both resistor networks.

Abstract: The present invention is provided to easily manufacture an IPD as any of a high-side switch and a low-side switch. A level shifting circuit is coupled to an input terminal, a first terminal, and a grounding terminal. Drive power of the level shifting circuit is supplied from the first terminal. An output signal of the level shifting circuit is input to a driver circuit. The driver circuit is coupled to the first terminal and a second terminal. Drive power of the driver circuit is supplied from the first terminal. A transistor has a gate electrode coupled to the driver circuit, a source coupled to the second terminal, and a drain coupled to a third terminal.

Abstract: An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.