Abstract: The application discusses a computer implemented method and apparatus for performing audio equalization in an audio receiver device, such as an integrated receiver/decoder or set top box, or integrated TV, connected to one or more audio playback devices, such as a television unit, computer screen and speakers, amplifier or home theater equipment. The method and apparatus use an equalization process which compares audio signals received in different audio formats (e.g. MPEG-1 Layer II, AC-3 2.0, AC-3 5.1 and HE-AAC) with one another, allowing a correction gain factor to be determined for equalizing the perceived loudness of the signals when played-back at a connected playback device. The correction gain factor is then applied in the audio receiver device before output.

Abstract: A method, a computer program product, and a computer system for selecting songs using a heart rate change, a blood pressure change, and a facial expression of a listener. A computer receives a song from a music source selected by a listener and determines whether the song is appropriate. The computer starts to play the song, in response to determining that the song is appropriate. A camera connected to the computer detects a facial expression of the listener. The computer determines whether the facial expression is positive. In response to determining that the facial expression is positive, the computer the song in full. The camera connected to the computer detects a heart rate change and a blood pressure change of the listener. The computer tags the song with updated information.

Abstract: The Harmonic Tracking Equalizer (HTEq) is an apparatus for and method of carrying out harmonic tracking equalization processing of an electrical signal, and apparatuses for and methods of controlling such equalization processing of the signal to dynamically sense the time-varying spectrum of an input signal and closely match a user desired audio signal spectrum while preserving the original dynamic range of the signal. The harmonically (sub-harmonically) tracked equalization is according to a user specified spectral request specified by a control interface that allows a user to request an amount of equalization to be applied to the signal. This apparatus is intended to process audio signals; though, it has general application to waveforms of other source and higher frequency content.

Abstract: A watch type mobile terminal and controlling method thereof are disclosed, by which the watch type mobile terminal can be controlled through voice. The present disclosure includes a touch input unit configured to receive a touch input, a wireless communication unit configured to perform a wireless communication, a sensing unit configured to sense a movement of the mobile terminal, a microphone configured to receive a sound, and a controller is configured to activate the microphone when a preset first gesture input is detected, if a user voice is received via the microphone while the touch input unit is touched, control data to be transmitted to a target indicated by the user voice, and if the user voice is received via the microphone while the touch input unit is not touched, control a function indicated by the user voice to be executed on the mobile terminal.

Abstract: A floating point multiply add circuit 24 includes a multiplier 26 and an adder 28. The input operands A, B and C together with the result value all have a normal exponent value range, such as a range consistent with the IEEE Standard 754. The product value which is passed from the multiplier 26 to the adder 28 as an extended exponent value range that extents lower than the normal exponent value range. Shifters 48, 50 within the adder can take account of the extended exponent value range of the product as necessary in order to bring the result value back into the normal exponent value range.

Abstract: An apparatus includes input circuitry that splits an input value into first bit-groups. First memory arrays are each populated with first random numbers, receive from the input circuitry a first bit-group, and retrieve and output a first random number from a first address indicated by the received first bit-group. Distribution circuitry splits each first random number output by the first memory arrays into second bit-groups, and distributes the second bit-groups. Second memory arrays are each populated with second random numbers, receive via the distribution circuitry a second bit-group from each first memory array, concatenate the received second bit-groups so as to form an address indicator, and retrieve and output a second random number from a second address indicated by the address indicator. Output circuitry combines the second random numbers output by the second memory arrays into an output random number that depends on the input value.

Abstract: The software development tool (701) forms part of a software development kit (700). The software development tool (701) receives as input object files (606) and library files (607) and subjects the object file instructions and data definitions of the object files and the library files to re-sequencing to generate new object files and the links between them which are semantically equivalent to the input object files and library files and which are used to generate an optimized executable. The software development tool (701) is capable of automatically generating an executable, without requiring any modification of the source code, which is optimized to execute more deterministically and with respect to execution time; reduced processor and memory requirements; reduced off-chip memory accesses; reduced memory latency.

Abstract: Examples of the disclosure provide for receiving a data set at a design surface from a data source, and inferring a first data type from the data set. A first control type is generated for the inferred first data type. A second data type is inferred from the data set and a second control type is generated for the inferred second data type, with the first control type and the second control type being different. A layout is generated for an application document that includes the first control type and the second control type.

Abstract: Computation can be encoded in a lightweight and optionally typed data representation. The data representation can be specified in a prefix-based notation potentially including nested function-argument pairs. Further, the data representation can comprise optional static type information associated with at least a portion of computation. Still further, the data representation can be programming language and platform independent or surfaced in a particular programming language or platform.

Abstract: The claimed subject matter provides a system and/or method that facilitates creating a portion of an industrial process. An interface component can receive a first portion of data associated with a first programming language and a second portion of data associated with a second programming language, wherein the first programming language is independent and disparate of the second programming language. An editor component can create at least one of a portion of an industrial process or a portion of a mixed language object by enabling the combination of the first portion of data and the second portion of data independent of the respective programming languages.

Abstract: A uniform strategy for the general problem of providing custom editors and initialization strings for beans (all “dynabeans” inherit from a common bean class that incorporates this strategy. This is then extended to allow the initialization strings to be stored in a relational database. The database function is an extension of the function provided by the VisualAge Persistence Builder (using some of the EADP extensions). An important advantage of this approach is that many changes to the application can now be handled by adjusting the database version of the bean definition, without a need to touch the underlying code. This will reduce down time for the application, and also improve application stability.

Abstract: A tool that outputs workflows for target computing devices receives user input selecting one or more Application Programming Interfaces (APIs), a plurality of workflow activities, each of which define actions that are to be performed by the target computing device, and an application framework. Based on these selections, the tool compiles the workflow activities for execution on the target computing device based on the first application framework selected by the user, and generates a workflow activity package to comprise the compiled plurality of workflow activities. If the selected application framework is not compatible with the execution environment at the target device, the tool allows the user to select a different application framework to replace the initially selected application framework, and to re-compile the workflow activities based on the newly selected application framework.

Abstract: A method and apparatus for updating a web-based user interface. The method comprises generating a user interface for a host application, accessing the user interface in a web browser, and modify the user interface within the web browser during run-time of the application. The apparatus comprises a user interface, a user interface updater, a web browser, and a host application. The web browser provides a way to display, access, and modify the user interface for communicating with the host application. The user interface updater generates the user interface and modifies the user interface in response to command information received from the web browser.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using an imports scanner to maintain a compilation cache. One of the methods includes receiving an original set of source code files to be compiled for a compilation target. Each file in in the original set having an entry point is added to a reduced set of source code files. Each unscanned file in the reduced set of source code files is scanned for import statements until no unscanned files in the reduced set of source code remain. Each file identified by an import statement is added to the reduced set of source code files. If the reduced set of files is not represented by an entry in a compilation cache, the compilation target is generated using only the reduced set of source code files instead of the original set of source code files.

Abstract: The type environment of a program can be modeled as a graph. In the graph, a node can represent a code element including but not limited to a function, a class, an object, a variable, an expression, a script, a global, a primitive, a module, an interface, an enumerated list, an array, an alias for a type, a parameter, a property, a type, a method, a function expression, a call signature, an index signature, an object type, or a function type. An edge in the graph can represent a relationship between code elements. When the type of a code element changes, the graph can be changed to model the revised source code. Computations concerning effects of a type change are delayed until information concerning the affected code element is requested.

Abstract: Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers.

Abstract: A method, computer system and computer program for optimizing the processing of a character string during execution of the program by using characteristic information that indicates a characteristic of the character string and is associated with the character string. The method includes the steps of determining, on the basis of a characteristic of a first character string and operation for the first character string, a characteristic information of at least one of the first character string and a second character string obtained as a result of the operation, and associating the characteristic information with the at least one character string.

Abstract: A method for allocating an identifier (ID) of a software component is disclosed. The method includes generating information on software components by a Device Management (DM) server, generating a download package including the information on software components by the DM server, transmitting the download package from the DM server to a DM client, executing the download package by the DM client, and allocating an ID to each software component based on the information on software components if the download package is executed by the DM client.

Abstract: An information processing apparatus in which an application operates, comprises: a framework that causes a first application and a second application for extending the first application to operate; and installation control unit configured to control installation of an application into the framework, wherein the installation control unit holds data of the second application in a first storage area in a case of receiving an instruction to install the second application, and installs the second application into the framework using the data of the second application held in the first storage area, in a case of receiving an instruction to activate the second application after receiving the instruction to install the second application.

Abstract: The present invention is an installation script generation engine. An application component distribution system can include a repository of semantic models for interdependent ones of application components. A mapping of individual listings in the semantic models to target platform specific installation instructions further can be included. Finally, a script generation engine can be configured to produce a target specific set of instructions for a specified application component based upon a mapping of at least one of the semantic models in the repository. Notably, each of the semantic models can include a listing of component relationships, target platform requirements and platform neutral installation instructions. Moreover, the component relationships can include at least one component relationship selected from the group consisting of a containment relationship, a usage relationship, a contradiction relationship, and an equivalence relationship.

Abstract: There is provided a method and system to automatically provide software and/or firmware updates to the electronic devices, particularly mobile devices used by consumers such as portable health-care data interchange devices. There is also provided a method and system of updating software in electronic devices without requiring a wired data interface to affect changes. There is also provided a method and system for tracking the configuration of electronic devices that are sold to and configured by particular consumers, especially consumers/patients using electronic devices related to health care. Further, there are also provided a methods and systems for integrating the purchase, and ordering, and software configuration of electronic devices.

Abstract: Systems and methods for requesting computer software program logic by a client computing device from a server are provided. The method at the server comprises receiving a request for the computer software program logic from the client device along with a first list comprising details about multiple modules running on the client device; determining a second list comprising details about multiple modules required to deploy the computer software program logic on the client device; checking whether the modules of the second list need to be substituted based on their availability or suitability; updating the second list; checking whether the client device has permission rights for accessing the modules of the updated second list; and sending an object comprising the modules of the updated second list to the client device, the updated second list comprising details about the modules required for deployment of logic on the client device.

Abstract: Technologies are described herein for deploying an update to hosts in a heterogeneous host fleet. One or more relevant host attributes for hosts in the host fleet are identified. Hosts in the fleet of hosts are classified into groups based on the identified relevant host attributes. A pilot host set is built by selecting one or more hosts from one or more of the groups according to a pilot host selection criteria. The update is deployed to the hosts included in the pilot host set as a test deployment. If the test deployment is successful, the update is deployed to the remaining hosts in the fleet of hosts; otherwise, the deployment is modified to continue the deployment to a subset of the host or to cancel the deployment and to restore the hosts in the pilot host set to their previous states. An analysis may be conducted based on the deployment data to provide recommendations for future deployments.

Abstract: Examples disclosed herein provide systems, methods, and software to attach updated applications to computing devices. In one instance, a method of attaching updated applications to a computing device includes identifying an application update for an application stored on the computing device, and determining an updated application volume containing an updated version of the application. The method further includes mounting the updated application volume to the computing device, and overlaying the updated version of the application with the application stored on the computing device.

Abstract: Embodiments of the present invention provide an application upgrade method and an apparatus. The application upgrade method includes: receiving an application deployment request; determining a deployment package of a to-be-deployed application; determining that a version of a first platform node is below a version requirement of a node template of the to-be-deployment application for a first platform node template; acquiring a first platform node upgrade package that meets the version requirement of the node template of the to-be-deployed application for the first platform node template; upgrading the first platform node indicated by an identifier of the first platform node by using the first platform node upgrade package; determining an identifier of a to-be-upgraded application node; and upgrading the application node indicated by the identifier of the to-be-upgraded application node by using the deployment package of the to-be-deployed application.

Abstract: A method and associated system for patching virtual machines in L redundancy groups in accordance with a patching schedule. The patching schedule is generated by scheduling, in W sequential time windows, P patches applicable to the virtual machines. Each redundancy group includes virtual machines and independently belongs to a respective software application x of X software applications, wherein P?1, L?1, Rm?1, and X?1. The L redundancy groups collectively comprise at least 2 virtual machines. The scheduling determines xwmk for T tuples (w, m, k) defined by (w=1, . . . , W) and (m=1, . . . , L) and (k=1, . . . , Rm), by maximizing an objective function subject to constraints. Determining xwmk includes setting xwmk=1 if virtual machine k in redundancy group m is to be patched in time window w or setting xwmk=0 otherwise.

Abstract: A system for managing a code load for a storage system is disclosed. The system can include instantiating a code load. The code load can include a first update for a first component and a second update for a second component. The system can include monitoring the operational state of the first and second components in response to instantiating the code load. The system can also include determining to perform the first update in response to a triggering event. The system can also include performing the first update in response to determining to perform the first update.

Abstract: An install request including a hierarchy of a complex computer environment is received, wherein the hierarchy comprises a first component needed on the first computer and one or more other components needed in the complex computer environment. One or more other computers on which to install the one or more components is determined. Responsive to determining the one or more other computer on which to install the one or more other components, installation of the one or more other components on the one or more other computers is initiated.

Abstract: An upgrade is performed for a complex programmable logical device (CPLD), the method comprising: splitting a serial vector format (SVF) file into a first SVF sub-file and a second SVF sub-file; generating a first Versa Module Europa (VME) bus file according to the first SVF sub-file; generating a second VME bus file according to the second SVF sub-file; and backing up register information and a pin signal of the CPLD. The method further comprises upgrading a program of the CPLD using the first SVF sub-file and the first VME bus file. The method further comprises using the second SVF sub-file and the second VME bus file to release the pin of the CPLD after the register information and the pin signal of the CPLD are restored by the first SVF sub-file and the first VME bus file.

Abstract: Method for generation of a live update including compiling original source code into a first intermediate representation (IR) code; compiling modified source code into second IR code; analyzing and comparing the first and second IR codes to identify variables and functions that were changed generating a part of final IR code with all the original variables and functions; generating an additional part of final IR code with new code for modified portions of the changed original functions, added functions and variables, and marking it for compilation into special code/data sections; and compiling a new object code and a final executable binary based on the final IR. The final executable object code includes the original code and data from original application binary, and a live update code and data from additional part of final IR generated. The live update code and data refer to original code and data where needed via standard object code relocation information.

Abstract: A method of implementing inter-component function calls. The method comprises generating a lower tier indirection data structure comprising an entry indicating a location in memory of a function within a first software component, a higher tier indirection data structure comprising an entry indicating a location in memory of the lower tier indirection data structure, and a configuration data structure comprising an entry defining an active version of the first software component. The method further comprises implementing executable computer program code for an inter-component function call by referencing entries within the configuration data structure, the higher tier indirection data structure and the lower tier indirection data structure.

Abstract: Systems and methods for enhancing fixed-point operations, floating-point operations, or a combination thereof for programs implemented on an integrated circuit (IC) are provided. Portions of these operations may be shared among the operations. Accordingly, the embodiments described herein enhance these fixed-point operations, floating-point operations, or a combination thereof based upon these portions of the operations that may be shared.

Abstract: An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: an arithmetic logic unit (ALU) to perform a plurality of mathematical operations using one or more source operands; instruction check logic to evaluate the source operands for a current mathematical instruction and to determine, based on the evaluation, whether to execute a default sequence of operations including executing the current mathematical instruction by the ALU or to jump to an alternate sequence of operations adapted to provide a result for the mathematical instruction having particular types of source operands more efficiently than the default sequence of operations.

Abstract: A processing device to provide vectorization of conditional loops includes vector physical registers to store a source vector having a first plurality of n data fields, and a destination vector comprising a second plurality of data fields corresponding to the first plurality of data fields, wherein each of the second plurality of data fields corresponds to a mask value in a vector conditions mask. The processing device includes a decode stage to decode a first processor instruction specifying a vector expand operation and a data partition size, and execution units to set elements of the source vector to n count values, obtain a decisions vector, generate the vector conditions mask according to the decisions vector, and copy data from consecutive vector elements in the source vector, into unmasked vector elements of the destination vector, without copying data from the source vector into masked vector elements of the destination vector.

Abstract: A data processing apparatus includes a comparison unit configured to perform an element comparison process performing a comparison of a first data element at a first index in the first vector with a second data element at a second index in the second vector. A hazard vector generation unit is configured to populate a hazard vector at an index determined by the first index with a value determined by the second index. The comparison unit performs the element comparison process by iteratively comparing data elements of the first vector with each element of a subset of the second vector. It then determines the subset of the second vector as those data elements at indices in the second vector which are less than a current index of the first vector and which are greater than previously determined values of the second index for which the match condition was true.

Abstract: Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

Abstract: Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Abstract: The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the integrated circuit. In this manner, the original design of the integrated circuit may be altered.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode instruction and a execution unit to execute instructions, the execution unit being associated with a capture logic to periodically capture operating heuristics of the execution unit, a detection logic coupled to the execution unit to evaluate the captured operating heuristics to determine whether there is a need to adjust an operating point of the execution unit, and a control logic coupled to the detection logic and the execution unit to adjust the operating point of the execution unit based on the evaluation of the operating heuristics.

Abstract: A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.

Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.

Abstract: An instruction set architecture (ISA) includes instructions for selectively indicating last-use architected operands having values that will not be accessed again, wherein architected operands are made active or inactive after an instruction specified last-use by an instruction, wherein the architected operands are made active by performing a write operation to an inactive operand, wherein the activation/deactivation may be performed by the instruction having the last-use of the operand or another (prefix) instruction.

Abstract: A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to a next instruction following the synchronization instruction in the instruction stream to be executed by the first workitem. A second workitem is run on the processor after the yielding.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: In an example, there is disclosed a digital signal processor having a register containing a modular integer configured for use as a thread offset counter. In a multi-stage, pipelined loop, which may be implemented in microcode, the main body of the loop has only one repeating stage. On each stage, the operation executed by each thread of the single repeating stage is identified by the sum of a fixed integer and the thread offset counter. After each pass through the loop, the thread offset counter is incremented, thus maintaining pipelined operation of the single repeating stage.

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Abstract: A display apparatus and method for bending a display panel automatically during booting are provided. According to an exemplary embodiment, the display apparatus may include a display module; an input unit configured to receive a command from a user; a storage configured to store a booting sequence; a driver configured to change a curvature of the display module; and a processor configured to, in response to a power-on command being received through the input unit, control the driver to bend the display module, while performing booting according to the booting sequence.

Abstract: Hiding logical processors from an operating system (OS) of a computer is described. In an example, a method of hiding at least one logical processor in a computer having a plurality of logical processors includes: initializing the plurality of logical processors by executing a pre-boot routine in system firmware; identifying at least one logical processor of the plurality of logical processors to be hidden from an operating system (OS) of the computer to provide at least one hidden logical processor and at least one visible logical processor; placing each of the at least one hidden logical processor into a system management mode (SMM) by executing a park routine in the system firmware; and booting the OS of the computer to use the at least one visible logical processor.

Abstract: In a method for improving the performance of a computer system by releasing computer resources, a list P of programs installed on a computer system is determined. All relevant extension points EP of the computer system are searched for registered entries. A list A of automatically starting programs is generated by assigning the registered entries at the relevant extension points EP to the installed programs, respectively. The list A of the automatically starting programs is compared with a list S of system-required programs and a list V of used programs. Programs that are not system-required and programs that have not been used for a longer period of time are deactivated and computer resources that have been used by the deactivated programs are released. The deactivation of programs can be done by the user or automatically and can be cancelled when necessary.