Patents Issued in August 3, 2017
  • Publication number: 20170221527
    Abstract: In the context of a hard disk drive (HDD), an adhesive leak channel structural feature is positioned in an area at which an electrical feed-through is adhered with an adhesive to an enclosure base, where the leak channel feature inhibits the leakage of gas through the adhesive. Embodiments include providing the leak channel feature on the base and/or on the feed-through. Embodiments may further include application of an electrodeposition coating to the base in an area at which the adhesive is in contact.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 3, 2017
    Inventors: Seong-Hun Choe, Kimihiko Sudo, Yuta Onobu, Takehito Nagata, Hajime Eguchi, Kyosuke Yoshida, Naoshi Mizumoto
  • Publication number: 20170221528
    Abstract: In a compact three-dimensional memory (3D-MC), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20170221529
    Abstract: The above-substrate decoding stage of a compact three-dimensional memory (3D-Mc) could be an intra-level decoding stage, an inter-level decoding stage, or a combination thereof. For the intra-level decoding stage, contact vias can be shared by address-lines in the same memory level; for the inter-level decoding stage, contact vias can be shared by address-lines from different memory levels.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventor: Guobiao ZHANG
  • Publication number: 20170221530
    Abstract: The required technical result aimed to raise a speed of device response is achieved in the device, which includes a group of operative memory blocks, a data acquisition block, memory block and marginal state assessment block, where operative memory blocks group outputs are connected with data acquisition block inputs, which output is connected, with marginal state assessment block input, which output is connected with the memory block input, and first and second outputs of marginal state assessment block are connected, respectively, with first and second inputs of the memory block.
    Type: Application
    Filed: July 25, 2016
    Publication date: August 3, 2017
    Inventors: Viktor Vasilyevich DAVYDOV, Petr Mikhailovich EROKHIN
  • Publication number: 20170221531
    Abstract: A reference current generating circuit includes a positive temperature coefficient current source configured to generate a first current, a value of which increases with an increase of an ambient temperature thereof, a negative temperature coefficient current source configured to generate a second current, a value of which decreases with the increase of the ambient temperature thereof, a first current adjustment circuit configured to adjust the first current in accordance with a first adjustment setting value, to thereby generate a positive temperature characteristic current, a second current adjustment circuit configured to adjust the second current in accordance with a second adjustment setting value, to thereby generate a negative temperature characteristic current, and a current amplifier configured to amplify a combined current of the positive temperature characteristic current and the negative temperature characteristic current, to thereby generate a reference current.
    Type: Application
    Filed: January 26, 2017
    Publication date: August 3, 2017
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Tetsuya ONO
  • Publication number: 20170221532
    Abstract: Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Inventors: Ted Pekny, Jeff Yu
  • Publication number: 20170221533
    Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Publication number: 20170221534
    Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Inventor: Kyo-min SOHN
  • Publication number: 20170221535
    Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.
    Type: Application
    Filed: May 19, 2016
    Publication date: August 3, 2017
    Inventors: Kun-Chih Chen, Hsiao-An Chuang
  • Publication number: 20170221536
    Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Publication number: 20170221537
    Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Jun Pin Tan, Kiun Kiet Jong, Lai Pheng Tan
  • Publication number: 20170221538
    Abstract: A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.
    Type: Application
    Filed: December 22, 2016
    Publication date: August 3, 2017
    Inventor: CHAN KYUNG KIM
  • Publication number: 20170221539
    Abstract: An electronic device including an inverter includes a pull-up driving unit configured to drive an output node with a high voltage in response to an input signal; a path switching unit coupled in a path between the pull-up driving unit and the output node according to a direction of a first current flowing between the pull-up driving unit and the output node and operable to selectively switch on or off the path; a pull-down driving unit coupled to the output node to supply a low voltage in response to the input signal; a path blocking unit coupled in a path between the pull-down driving unit and the output node to block the path; and a bypass unit coupled to form a bypass path between the pull-down driving unit and the output node.
    Type: Application
    Filed: April 15, 2017
    Publication date: August 3, 2017
    Inventor: Ji-Ho Park
  • Publication number: 20170221540
    Abstract: A method and apparatus for controlled switching of a magnetoresistive random access memory device is disclosed herein. The method includes delivering a current to a magnetoresistive random access memory device, wherein the MRAM device is in a first state, measuring a voltage drop across the magnetoresistive random access memory device in real-time with a resistance detector, wherein a voltage drop beyond a threshold voltage equates to switching from a first state to a second state, the first state different from the second state, determining whether the MRAM device has switched from the first state to the second state, and stopping the current delivered to the magnetoresistive random access memory device.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Daniel BEDAU, Patrick M. BRAGANCA, Kurt Allan RUBIN
  • Publication number: 20170221541
    Abstract: A magnetic memory device may include a bit line, a plurality of source lines, a plurality of normal cells coupled between the bit line and the plurality of source lines, and each including a magnetic resistance element and a switching element coupled in series to the magnetic resistance element and switched by a word line signal, a dummy cell coupled to the bit line, and a spin-hall effect material layer between the bit line and the magnetic resistance element. The magnetic resistance element may write data according to a first current that flows through the dummy cell and flows in a direction parallel to the magnetic resistance element, and a second current that flows through the magnetic resistance element.
    Type: Application
    Filed: January 9, 2017
    Publication date: August 3, 2017
    Inventors: Kangwook JO, Jongil HONG, Hongil YOON
  • Publication number: 20170221542
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 3, 2017
    Inventors: Scott James Derner, Christopher John Kawamura
  • Publication number: 20170221543
    Abstract: A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: Doo-young KIM, Sung-hoon KIM
  • Publication number: 20170221544
    Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
    Type: Application
    Filed: August 25, 2016
    Publication date: August 3, 2017
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Publication number: 20170221545
    Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
    Type: Application
    Filed: April 12, 2017
    Publication date: August 3, 2017
    Applicant: SK hynix Inc.
    Inventors: Chang Hyun KIM, Min Chang KIM, Do Yun LEE, Yong Woo LEE, Jae Jin LEE, Hun Sam JUNG, Hoe Kwon JUNG
  • Publication number: 20170221546
    Abstract: A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.
    Type: Application
    Filed: January 24, 2017
    Publication date: August 3, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yanggyoon Loh, Hoyoung Song, Sangwoong Shin
  • Publication number: 20170221547
    Abstract: A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically.
    Type: Application
    Filed: January 24, 2017
    Publication date: August 3, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Hikaru Tamura
  • Publication number: 20170221548
    Abstract: An embodiment static random access memory (SRAM) array includes a first SRAM mini array having a first plurality of functional SRAM cells in a first column of the SRAM array. Each of the first plurality of functional SRAM cells share a first bit line (BL). The SRAM array further includes a second SRAM mini array having a second plurality of functional SRAM cells in the first column. Each of the second plurality of functional SRAM cells share a second BL independently controlled from the first BL. The SRAM array further includes and a SRAM dummy array between the first SRAM mini array and the second SRAM mini array. The SRAM dummy array includes a plurality of SRAM array abut dummy cells in the first column. A first endpoint of the first BL and a second endpoint of the second BL are disposed in the SRAM dummy array.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 3, 2017
    Inventor: Jhon Jhy Liaw
  • Publication number: 20170221549
    Abstract: A semiconductor storage device includes, a memory array, a plurality of memory cells provided in rows and columns, and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors, transfer transistors, and load elements.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: Yoshisato Yokoyama, Yuichiro Ishii
  • Publication number: 20170221550
    Abstract: Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Abdulkadir U. Diril, Adam T. Moerschell, Anthony P. DeLaurier
  • Publication number: 20170221551
    Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 3, 2017
    Inventors: Chulmin JUNG, Fahad AHMED, Sei Seung YOON, Keejong KIM
  • Publication number: 20170221552
    Abstract: An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 3, 2017
    Inventor: Jhon Jhy Liaw
  • Publication number: 20170221553
    Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.
    Type: Application
    Filed: January 25, 2017
    Publication date: August 3, 2017
    Inventors: Takahiko ISHIZU, Hikaru TAMURA
  • Publication number: 20170221554
    Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.
    Type: Application
    Filed: January 27, 2017
    Publication date: August 3, 2017
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yeop BAECK, Tae-Hyung KIM, Daeyoung MOON, Dong-Wook SEO, Inhak LEE, Hyunsu CHOI, Taejoong SONG, Jae-Seung CHOI, Jung-Myung KANG, Hoon KIM, Jisu YU, Sun-Yung JANG
  • Publication number: 20170221555
    Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.
    Type: Application
    Filed: April 14, 2017
    Publication date: August 3, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Carlos H. DIAZ, Chih-Hao WANG, Jean-Pierre COLINGE, Ta-Pen GUO
  • Publication number: 20170221556
    Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Inventors: Kenneth Louie, Man Mui
  • Publication number: 20170221557
    Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.
    Type: Application
    Filed: April 14, 2017
    Publication date: August 3, 2017
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
  • Publication number: 20170221558
    Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 3, 2017
    Inventors: Miao Hu, Ning Ge, John Paul Strachan, R. Stanley Williams
  • Publication number: 20170221559
    Abstract: A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.
    Type: Application
    Filed: August 4, 2016
    Publication date: August 3, 2017
    Inventors: Yangyin Chen, Christopher J. Petti, Kun Hou
  • Publication number: 20170221560
    Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 3, 2017
    Inventors: Miao HU, John Paul STRACHAN, Ning GE, Jianhua YANG
  • Publication number: 20170221561
    Abstract: Memories having a plurality of resistive storage elements in a shared resistance variable material, a plurality of select devices coupled to the plurality of resistive storage elements in a one-to-one relationship and sense circuitry coupled to the plurality of select devices.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Andrea Redaelli
  • Publication number: 20170221562
    Abstract: One example includes a resistive random access memory (RRAM) system. The system includes a resistive memory element to store a binary state based on a resistance of the resistive memory element. The system also includes an RRAM write circuit to generate a current through the resistive memory element to provide a write voltage across the resistive memory element to set the resistance of the resistive memory element. The system further includes a write shutoff circuit to monitor a change in the write voltage as a function of time to deactivate the RRAM write circuit in response to a change in the binary state of the resistive memory element.
    Type: Application
    Filed: April 15, 2015
    Publication date: August 3, 2017
    Inventor: Brent Buchanan
  • Publication number: 20170221563
    Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.
    Type: Application
    Filed: July 22, 2015
    Publication date: August 3, 2017
    Inventors: Yasuhiro Taniguchi, Yutaka Shinagawa, Hideo Kasai, Ryotaro Sakurai, Tatsuro Toya, Yasuhiko Kawashima, Kosuke Okuyama
  • Publication number: 20170221564
    Abstract: A semiconductor memory device includes a first block that includes a first set of word lines, a second block that includes a second set of word lines and is adjacent to the first block in a first direction, a first transistor group adjacent to the first and second blocks in a second direction crossing the first direction, and a second transistor group adjacent to the first transistor group in the second direction. Each of the word lines in the first set is electrically connected to a transistor in the first transistor group, and each of the word lines in the second set is electrically connected to a transistor in the first transistor group.
    Type: Application
    Filed: August 10, 2016
    Publication date: August 3, 2017
    Inventors: Nobuaki OKADA, Toshiki HISADA
  • Publication number: 20170221565
    Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventor: Ramin Ghodsi
  • Publication number: 20170221566
    Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Boon Bing NG, Hang Ru GOY
  • Publication number: 20170221567
    Abstract: A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspected qualification is connected with a plurality of page buffer/sensing circuits 170 via wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuit 170 includes a transistor Q2 in which a reference current Iref flows through a transistor Q1 when the programming verification is unqualified. The determination circuit 200 includes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.
    Type: Application
    Filed: June 15, 2016
    Publication date: August 3, 2017
    Inventors: Kazuki Yamauchi, Naoaki Sudo
  • Publication number: 20170221568
    Abstract: A disclosed example determines programmed states of a plurality of memory cells based on a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cells; determines, based on the programmed states, first ones of the memory cells that do not satisfy a target threshold voltage; and performs the programming pass on the first ones of the memory cells.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventors: Feng Pan, Ramin Ghodsi
  • Publication number: 20170221569
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Application
    Filed: March 10, 2016
    Publication date: August 3, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki AKAMINE, Masanobu SHIRAKAWA, Tokumasa HARA
  • Publication number: 20170221570
    Abstract: A nonvolatile memory device includes a memory block including a plurality of memory cells which are coupled to a plurality of word lines; and a control unit configured to perform a read operation in response to a read command for target memory cells which are coupled to a target word line, wherein the control unit performs the read operation by applying a read bias voltage to the target word line, applying a first pass bias to a monitoring word line, applying a second pass bias to one or more adjacent word lines adjacent to the target word line, and applying a third pass bias to remaining word lines.
    Type: Application
    Filed: June 22, 2016
    Publication date: August 3, 2017
    Inventor: Ji Man HONG
  • Publication number: 20170221571
    Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.
    Type: Application
    Filed: July 20, 2016
    Publication date: August 3, 2017
    Inventor: Byoung In JOO
  • Publication number: 20170221572
    Abstract: A low voltage detection circuit includes a first detection block configured to detect a level of an external voltage according to a reference voltage, and output a pre-detection signal; and a second detection block configured to generate a low voltage detection signal of a beginning level regardless of a variation in a level of the pre-detection signal when the level of the pre-detection signal is detected as the beginning level.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 3, 2017
    Inventor: Hyun Chul LEE
  • Publication number: 20170221573
    Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Neil Richard Darragh, Sergey Anatolievich Gorobets, Liam Michael Parker
  • Publication number: 20170221574
    Abstract: A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.
    Type: Application
    Filed: November 17, 2016
    Publication date: August 3, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-seong KIM, Cheol-ha Lee
  • Publication number: 20170221575
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: Chen-Yi HUANG, Jiaqi YANG, Cheng-Tai HUANG
  • Publication number: 20170221576
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: Chen-Yi HUANG, Jiaqi YANG, Cheng-Tai HUANG