Patents Issued in August 17, 2017
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Publication number: 20170237395Abstract: A solar power system may comprise a back sheet that comprises an interconnect circuit coupling a plurality of cell tiles. A tiled solar cell, comprising a solar cell and encapsulating and glass layers, is inserted into the cell tiles of the hack sheet. Each solar cell is individually addressable through the use of the interconnect circuit. Moreover, the interconnect circuit of the back sheet is programmable and allows for dynamic interconnect routing between solar cells.Type: ApplicationFiled: December 19, 2016Publication date: August 17, 2017Inventor: Nagendra Srinivas Cherukupalli
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Publication number: 20170237396Abstract: A method for detecting a defect in a multi-junction solar cell is presented. The multi-junction solar cell comprises at least two vertically stacked p-n junctions. The method comprises exciting a first p-n junction of the at least two vertically stacked p-n junctions by illuminating the solar cell with excitation light in a first excitation wavelength range, detecting photoluminescence light emitted by photoluminescence of the first p-n junction, and generating a spatially resolved first photoluminescence image of the photoluminescence light emitted by the first p-n junction. Further, a computer program product and an apparatus for detecting a defect in a multi-junction solar cell are presented.Type: ApplicationFiled: February 16, 2017Publication date: August 17, 2017Inventors: Claus Zimmermann, Helmut Nesswetter, Martin Rutzinger
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Publication number: 20170237397Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Inventors: Anandaroop Chakrabarti, Mark Ferriss, Bodhisatwa Sadhu
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Publication number: 20170237398Abstract: A system for entraining an oscillator ensemble is disclosed that includes a plurality of oscillators in an entrained phase pattern. The system includes an entrainment device operatively coupled to each non-linear oscillator of the oscillator ensemble, and the entrainment control device is configured to deliver a 2?-periodic control signal v(?) to all oscillators of the plurality of oscillators to induce the entrained phase pattern.Type: ApplicationFiled: February 17, 2017Publication date: August 17, 2017Inventors: Jr-Shin Li, Anatoly Zlotnik
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Publication number: 20170237399Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may have a first diode and a second diode connected as anti-parallel diodes and physically adjacent to each other in a substrate. The second circuit may have a third diode and a fourth diode connected as anti-parallel diodes and physically adjacent to each other in the substrate. The first circuit and the second circuit may be configured to mix two input signals to generate an output signal. A polarity of every other physically neighboring diode may be reversed.Type: ApplicationFiled: January 10, 2017Publication date: August 17, 2017Inventors: Emmanuelle R.O. Convert, Simon J. Mahon, James T. Harvey
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Publication number: 20170237400Abstract: The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: Kazuo Watanabe, Satoshi Tanaka, Norio Hayashi, Kazuma Sugiura
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Publication number: 20170237401Abstract: An amplifier arrangement comprises N amplifier stages, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a first cascade of quarter wavelength transmission line segments coupled to receive a first set of amplifier stages, and at least a second cascade of quarter wavelength transmission line segments coupled to receive a second set of amplifier stages. The first cascade and second cascade are connected to a common node, for example in parallel to an output node, or in parallel to an intermediate node.Type: ApplicationFiled: March 19, 2014Publication date: August 17, 2017Inventor: Richard Hellberg
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Publication number: 20170237402Abstract: An RF amplifier to increase a gain using a transformer is provided. The amplifier includes: a first transistor configured to generate a current by amplifying and converting an input voltage; a second transistor configured to amplify the generated current; and a first transformer configured to feed an emitter current of the second transistor back to a gate. Accordingly, Gm of the transistor is boosted using the transformer, such that a high gain can be obtained with a low current. Therefore, a problem of a gain reduction caused by a parasitic capacitor at a high frequency can be solved.Type: ApplicationFiled: December 27, 2016Publication date: August 17, 2017Inventors: Ki Jin KIM, Kwang Ho AHAN
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Publication number: 20170237403Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.Type: ApplicationFiled: March 6, 2017Publication date: August 17, 2017Inventors: James Wang, Yuh-Min Lin, Kun-You Lin
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Publication number: 20170237404Abstract: RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The first RF LNA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal.Type: ApplicationFiled: May 5, 2017Publication date: August 17, 2017Inventors: George Maxim, Dirk Robert Walter Leipold, Baker Scott
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Publication number: 20170237405Abstract: Mechanisms for controlling an audio level of an HDMI audio system are provided, the mechanisms comprising: causing audio data to be presented by an HDMI audio system at a current system volume level; receiving a requested volume level from a second screen device; and controlling a system volume level by: (a) determining the current system volume level; (b) determining a change in volume based on a difference between the requested volume level and the current system volume level; (c) determining a direction in which to cause the system volume level to change; (d) sending a volume control message to the system using a consumer electronic control bus connected to the system indicating whether to increase or decrease the system volume level based on the determined direction of system volume change; and (e) repeating (a)-(d) until the current system volume level reaches a predetermined value.Type: ApplicationFiled: April 28, 2017Publication date: August 17, 2017Inventor: Eric Jason Roberts
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Publication number: 20170237406Abstract: An elastic wave device includes IDT electrodes on a first main surface of a piezoelectric substrate and a heat dissipating film on a second main surface and including a pair of opposing main surfaces and side surfaces connecting the pair of main surfaces. At least a portion of the side surfaces of the heat dissipating film is located in an inner side portion relative to the outer circumference of the second main surface of the piezoelectric substrate on an arbitrary cross section along a direction connecting the pair of main surfaces of the heat dissipating film.Type: ApplicationFiled: May 4, 2017Publication date: August 17, 2017Inventors: Daisuke SEKIYA, Taku KIKUCHI, Hiroshi TANAKA
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Publication number: 20170237407Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.Type: ApplicationFiled: May 2, 2017Publication date: August 17, 2017Applicant: Short Circuit Technologies LLCInventors: Masoud Babaie, Robert Bogdan Staszewski
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Publication number: 20170237408Abstract: A resonator includes a resonating portion including a first electrode, a second electrode, and a piezoelectric layer positioned between the first electrode and the second electrode; and a frame provided at an outer edge of the resonating portion, at least a portion of the frame covering an outer end portion of the second electrode.Type: ApplicationFiled: September 21, 2016Publication date: August 17, 2017Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sung HAN, Dae Ho KIM, Ran Hee SHIN, Hwa Sun LEE, Chang Hyun LIM, Tae Kyung LEE, Sung Sun KIM
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Publication number: 20170237409Abstract: An acoustic resonator includes: a substrate; a resonance part mounted on the substrate and including resonance part electrodes, the resonance part being configured to generate acoustic waves; a cavity disposed between the resonance part and the substrate; a frame part disposed on at least one electrode among the resonance part electrodes, and being configured to reflect the acoustic waves; and a connection electrode configured to connect the at least one electrode to an external electrode, and having a thickness less than a thickness of the at least one electrode.Type: ApplicationFiled: September 23, 2016Publication date: August 17, 2017Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Won HAN, Moon Chul LEE, Jae Chang LEE, Sang Uk SON, Tae Hun LEE
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Publication number: 20170237410Abstract: An acoustic wave filter device includes a base comprising an acoustic wave filter part formed on one surface thereof and including a bonding part formed to surround the acoustic wave filter part, and a cap including a depression groove formed therein and a bonding counterpart formed to correspond to the bonding part. The depression groove is positioned over the acoustic wave filter part. The bonding part and the bonding counterpart receive a voltage to deform and bond the bonding part and the bonding counterpart to each other.Type: ApplicationFiled: September 21, 2016Publication date: August 17, 2017Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Yun Sung KANG, Ji Hye NAM, Kwang Su KIM, Pil Joong KANG, Jeong Il LEE
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Publication number: 20170237411Abstract: An acoustic wave filter includes a substrate having voids formed therein; a first resonator disposed on one or more of the voids, and a second resonator disposed on other of the voids. A first trimming layer is provided in the first resonator, and a second trimming layer is provided in the second resonator. The second trimming layer is formed of a material having an etching rate for a given etchant different from that of the first trimming layer.Type: ApplicationFiled: October 5, 2016Publication date: August 17, 2017Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Won Kyu JEUNG
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Publication number: 20170237412Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.Type: ApplicationFiled: December 16, 2016Publication date: August 17, 2017Inventor: Vikas Sharma
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Publication number: 20170237413Abstract: An oscillation circuit includes a delay circuit that includes a first inverter having an input terminal connected to a first node, a delay adjustment circuit including first and second current supply paths through which the first node is charged in response to an output signal of the delay circuit. During charging of the first node, a current with positive temperature characteristics is supplied to the first node through the first current supply path, and a current with negative temperature characteristics is supplied to the first node through the second current supply path.Type: ApplicationFiled: August 31, 2016Publication date: August 17, 2017Inventor: Chen Kong TEH
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Publication number: 20170237414Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: MIN SU KIM, JONG WOO KIM, JI KYUM KIM
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Publication number: 20170237415Abstract: In an embodiment, a buffer circuit may includes a current source circuit, a self-bias generation circuit, a signal input circuit, and a first current sink circuit. The current source circuit may apply current to a first node and a second node in response to a self-bias voltage. The self-bias generation circuit may generate the self-bias voltage which has a voltage level between voltage levels of the first and second nodes. The signal input circuit may control the voltage levels of the first node and the second node in response to a first input signal and a second input signal. The first current sink circuit may control an amount of current flowing from the signal input circuit to a ground terminal in response to an enable signal and the self-bias voltage.Type: ApplicationFiled: June 23, 2016Publication date: August 17, 2017Inventor: Yeonsu JANG
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Publication number: 20170237416Abstract: A semiconductor device includes an amplifier, a slew rate regulating circuit, a detection circuit, and a control circuit. The amplifier is configured to amplify an input signal. The slew rate regulating circuit is configured to regulate the slew rate of the input signal. The detection circuit is configured to detect the slew rate of the input signal along a signal path of the input signal between the slew rate regulating circuit and the amplifier. The control circuit is configured to control the slew rate regulating circuit based on a detection result of the detection circuit.Type: ApplicationFiled: August 31, 2016Publication date: August 17, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yusuke NIKI
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Publication number: 20170237417Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.Type: ApplicationFiled: November 30, 2016Publication date: August 17, 2017Inventors: Jianhua Lu, Peter Bacon, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
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Publication number: 20170237418Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.Type: ApplicationFiled: November 30, 2016Publication date: August 17, 2017Inventors: Jianhua Lu, Peter Bacon, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
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Publication number: 20170237419Abstract: Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.Type: ApplicationFiled: February 16, 2016Publication date: August 17, 2017Applicant: ANALOG DEVICES, INC.Inventor: MARTIN CLARA
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Publication number: 20170237420Abstract: The present invention relates to a system and a method for pulse width modulation and demodulation of a continuous input signal, which system is configured to receive a continuous input to an analog modulator, which system comprises a demodulator generating a continuous output signal. It is the object of the pending patent application to use an analog modulator for transmitting the signal from the input stage over to an output stage. A further object of the pending patent application is to preserve the signal integrity in regard to precision and to minimize both non-linearities and distortion side effects.Type: ApplicationFiled: July 1, 2015Publication date: August 17, 2017Applicant: PR ELECTRONICS A/SInventors: Stig Alnøe Lindemann, Dan Vinge Madsen
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Publication number: 20170237421Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.Type: ApplicationFiled: February 24, 2016Publication date: August 17, 2017Applicant: STMicroelectronics (Beijing) R&D Co. LtdInventor: Zhenghao Cui
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Publication number: 20170237422Abstract: Voltage surge is prevented when the output from a driver of a driving circuit performs a hard shutdown. In this manner, the elements in the driving circuit are prevented from being damaged by the voltage surge. A driving circuit includes a level shift circuit configured to convert an input signal from a preceding-stage circuit into an output signal having a higher voltage than the input signal, and a controller configured to determine whether a switch element is to perform a soft shutdown based on a state signal indicating a state of the preceding-stage circuit. Here, the driving circuit is configured to drive the switch element.Type: ApplicationFiled: April 28, 2017Publication date: August 17, 2017Inventor: Masashi AKAHANE
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Publication number: 20170237423Abstract: An absorptive switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common terminal and one or more ports, any of which may be selectively coupled to the common terminal by closing an associated path switch; non-selected, unused ports are isolated from the common terminal by opening an associated path switch. Between each path switch and a port are associated shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated absorptive switch module. Each absorptive switch module includes a resistor coupled in parallel with a switch. The combination of the resistor and the switch of the absorptive switch module is placed in series with a corresponding signal path from each port to the common terminal, rather than in a shunt configuration.Type: ApplicationFiled: December 13, 2016Publication date: August 17, 2017Inventor: Peter Bacon
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Publication number: 20170237424Abstract: A switch bias control circuit includes a level shifter and voltage regulator circuitry configured to receive a voltage reference signal, provide a first voltage output at a first node and provide a second voltage output at a second node, the first node and the second node being at least partially isolated from one another. coupling circuitry couples the first node to the level shifter and couples the second node to a negative voltage generator.Type: ApplicationFiled: February 10, 2017Publication date: August 17, 2017Inventors: Leo John WILZ, Jonathan Christian CRANDALL, David Steven RIPLEY, James Phillip YOUNG
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Publication number: 20170237425Abstract: Semiconductor switches in portable transceivers switch between outgoing and incoming radio frequency signal paths. The isolation can be limited by the capacitive coupling between the switch input and the switch output. Ultra-high isolation can be achieved by adding a coupled transmission line to the semiconductor switch. The coupled transmission line introduces inductive coupling, which cancels at least a part of the capacitive coupling between the switch input and the switch output.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: Yu Zhu, Oleksiy Klimashov, Dylan Charles Bartle
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Publication number: 20170237426Abstract: Devices and methods for generating an internal reset signal are explained. A first circuit (11) generates a first reset signal (r1), and a second circuit (12) generates a second reset signal (r2). The first reset signal (r1) and the second reset signal (r2) are linked to form a reset signal (r) with which a further circuit part (14) can be reset.Type: ApplicationFiled: January 18, 2017Publication date: August 17, 2017Inventor: Dieter Draxelmayr
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Publication number: 20170237427Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.Type: ApplicationFiled: September 24, 2016Publication date: August 17, 2017Inventors: Daniele Zella, Vanni Poletto, Mauro Foppiani
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Publication number: 20170237428Abstract: A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and ?V1 when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source VDD and a control low power source VNEG. The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or ?V1 if IN is high when EN is high. Only single type VT transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.Type: ApplicationFiled: February 14, 2017Publication date: August 17, 2017Inventors: Fei XU, Bai Yen NGUYEN, Jinling WANG, Benjamin Shui Chor LAU
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Publication number: 20170237429Abstract: A photocoupler isolation switch circuit is disclosed. The circuit includes a power chip and a voltage driving chip including a photocoupler device having a light emitting device and a photosensitive device. A first output terminal of the power chip connects to a first terminal of the light emitting device, and a second terminal of the light emitting device connects to ground; a second output terminal of the power chip connects to a first terminal of the photosensitive device and outputs a driving voltage, a second terminal of the photosensitive device connects to an output terminal of the photocoupler device; the photocoupler device controls a working status of the light emitting device according to a control voltage, the photosensitive device is turned on or off according to the working status; the driving voltage is outputted through the output terminal of the photocoupler device when the light emitting device is turned on.Type: ApplicationFiled: September 9, 2015Publication date: August 17, 2017Applicant: Shenzhen China Star Optoelectronics TechnologyInventor: Fengcheng XU
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Publication number: 20170237430Abstract: A capacitive touch device is described. The device comprises a substrate and a plurality of co-planar capacitive touch switches and conductive tracks connected to the capacitive touch switches disposed directly on a face of the substrate. The capacitive touch switches include first and second capacitive touch switches which are adjacent, separated by a channel and which are electrically isolated from each other. The capacitive touch switches include third and fourth capacitive touch switches which are electrically isolated from the first and second capacitive touch switches, but which are electrically connected to each other by a conductive track which runs through the channel.Type: ApplicationFiled: October 15, 2015Publication date: August 17, 2017Inventor: Kate Stone
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Publication number: 20170237431Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.Type: ApplicationFiled: February 2, 2017Publication date: August 17, 2017Inventors: James A. McCALL, Kuljit S. BAINS
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Publication number: 20170237432Abstract: A radio-frequency switch includes a first field-effect transistor disposed between a first node and a second node, the first field-effect transistor having a source, a drain, a gate, and a body. The switch further includes a coupling path connected between the body of the first field-effect transistor and the gate of the first field-effect transistor, the coupling path including a diode. The switch further includes an adjustable impedance network connected between the body of the first field-effect transistor and a ground reference, the adjustable impedance network being configured to reduce radio-frequency distortion in the first field-effect transistor.Type: ApplicationFiled: February 10, 2017Publication date: August 17, 2017Inventors: Ambarish ROY, Guillaume Alexandre BLIN
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Publication number: 20170237433Abstract: A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and/or to compensate for parasitic resistance.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Applicant: Altera CorporationInventors: Kok Siang Tan, Tim Tri Hoang
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Publication number: 20170237434Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.Type: ApplicationFiled: February 16, 2016Publication date: August 17, 2017Inventors: Qi YE, Animesh DATTA, Venkatasubramanian NARAYANAN, Venugopal BOYNAPALLI
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Publication number: 20170237435Abstract: Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.Type: ApplicationFiled: April 12, 2017Publication date: August 17, 2017Applicant: Micron Technology, Inc.Inventor: Satoshi Yamanaka
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Publication number: 20170237436Abstract: A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.Type: ApplicationFiled: December 17, 2014Publication date: August 17, 2017Applicant: Mitsubishi Electric CorporationInventors: Kazuya HOKAZONO, Akihisa YAMAMOTO, Dong WANG
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Publication number: 20170237437Abstract: Structure for a level shifter circuit is provided that includes a native transistor. The level shifter circuit includes transistors that are configured as an inverter and the native transistor configured to remain on or in a subthreshold region. The level shifter circuit is configured to receive a first input signal that ranges between ground and a first voltage and output an output signal that ranges from ground to a second voltage greater than the first voltage. The structure reduces an area required by the level shifter circuit and consumes a low amount of standby current.Type: ApplicationFiled: February 12, 2016Publication date: August 17, 2017Inventor: Jeffrey CHIN
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Publication number: 20170237438Abstract: Voltage level shifters are devices that resolve mixed voltage incompatibility between different parts of a system that operate in multiple voltage domains. Voltage level shifters are typically also an important circuit component and are used e.g. in between a core circuit and an I/O (input/output) circuit. However, a voltage level shifter, when it switches between two levels, may generate voltage undershoots at intermediate internal nodes by capacitive coupling. These voltage undershoots cause an increased crosscurrent at the voltage level shifter which increases the overall power consumption and an increased delay in propagating the signals (i.e. voltage level shifters may be relatively slow in switching).Type: ApplicationFiled: February 2, 2017Publication date: August 17, 2017Inventor: Hartmud Terletzki
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Publication number: 20170237439Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.Type: ApplicationFiled: May 4, 2017Publication date: August 17, 2017Applicant: University of South FloridaInventors: Swaroop Ghosh, Kenneth Ramclam
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Publication number: 20170237440Abstract: The present invention discloses a processor comprising three-dimensional memory (3D-M) array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and a 3D-M-based look-up table (3DM-LUT). The ALC performs arithmetic operations on the LUT data, while the 3DM-LUT is stored in at least one 3D-M array.Type: ApplicationFiled: April 13, 2017Publication date: August 17, 2017Applicant: HangZhou HaiCun Information Technology Co., Ltd.Inventors: Guobiao ZHANG, Chen SHEN
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Publication number: 20170237441Abstract: An oscillator circuit (100) comprises a crystal oscillator (10) arranged to generate an oscillation signal, a bias current generator (20) arranged to supply a bias current to the crystal oscillator (10), and a feedback stage (30) arranged to generate a feedback signal in response to an amplitude of the oscillation signal reaching an amplitude threshold. The bias current generator (20) is arranged to: in response to a supply of power to the oscillator circuit (100) being switched on, generate the bias current at an increasing level commencing from a first level; in response to the feedback signal, terminate the increasing; and during subsequent oscillation of the crystal oscillator (10), supply the bias current at a second level dependent on a final level of the bias current reached when the increasing is terminated.Type: ApplicationFiled: June 2, 2014Publication date: August 17, 2017Inventors: Janne Peltonen, Christian Elgaard, Anna-Karin Stenman
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Publication number: 20170237442Abstract: A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.Type: ApplicationFiled: June 23, 2016Publication date: August 17, 2017Inventors: Kyung Hoon KIM, Myeong Jae PARK, Woo Yeol SHIN, Sung Eun LEE, Han Kyu CHI, Jae Won HAN
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Publication number: 20170237443Abstract: A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.Type: ApplicationFiled: October 1, 2015Publication date: August 17, 2017Inventors: SHINGO SETO, SATOSHI SUDA
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Publication number: 20170237444Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.Type: ApplicationFiled: February 16, 2017Publication date: August 17, 2017Inventors: Fangxing Wei, Setul M. Shah, Michael J. ALLEN, Khushal N. Chandan