Abstract: A magnetic recording system for preventing data loss resulting magnetic oscillator current. The magnetic recording system includes a magnetic write head with a magnetic write pole, a magnetic oscillator near the magnetic write pole, and a write coil for magnetizing the write pole. Circuitry is connected with the magnetic write coil to supply a current to the write coil and connected with the magnetic oscillator to supply a current to the magnetic oscillator. The circuitry is configured to ensure that the current to the magnetic oscillator does not inadvertently magnetize the write pole after the magnetic write pole has demagnetized.

Abstract: In one general embodiment, a method includes determining a sampling interval for an interpolator using at least one parameter. The method further includes applying the sampling interval to the interpolator in response to determining the sampling interval. In another general embodiment, an apparatus includes an interpolator and a controller. The controller is configured to determine a sampling interval for the interpolator using at least one parameter. The controller is also configured to apply the sampling interval to the interpolator in response to determining the sampling interval.

Abstract: A tape apparatus includes a tape drive and a processor. The tape drive is configured to perform data reading and data writing on a magnetic tape in which a plurality of tracks are formed. The processor is configured to control the tape drive to perform data reading and data writing on the plurality of tracks in a first segment among a plurality of segments obtained by dividing the magnetic tape in a running direction. The processor is configured to reserve a first track of the plurality of tracks as a copy target upon determining that an abnormality occurs in the first segment on the first track. The processor is configured to instruct the tape drive to copy data recorded in the first segment on the first track to a second segment on the first track at a predetermined timing. The second segment is adjacent to the first segment.

Abstract: A novel process and system for flexibly adding supplemental digital program content such as, for example, transactional advertising content, games, polls, contests, interactive music videos, and e-commerce content generally and the like, into pre-prepared digital media files, such as an MP3 audio file or the like, for playback by digital playback apparatus, wherein the pre-prepared media file is modified by embedding therein executable code representing such supplemental program content, and enabling the playback apparatus to decode and execute the presentation of the supplemental program material as an addition to the playback of the pre-prepared media file content.

Abstract: Disclosed are systems and methods for improving interactions with and between computers in content generating, searching, hosting and/or providing systems supported by or configured with personal computing devices, servers and/or platforms. The systems interact to identify and retrieve data within or across platforms, which can be used to improve the quality of data used in processing interactions between or among processors in such systems. The disclosed systems and methods provide systems and methods for automatically extracting and creating an animated Graphics Interchange Format (GIF) file from a media file. The disclosed systems and methods identify a number of GIF candidates from a video file, and based on analysis of each candidate's attributes, features and/or qualities, as well as determinations related to an optimal playback setting for the content of each GIF candidate, at least one GIF candidate is automatically provided to a user for rendering.

Abstract: Disclosed herein are methods and systems for new analytic pathways for collecting information regarding video playback by human (and automated) users. This is achieved in part by placing certain elements (Vixels) within the code of a video file prior to it being uploaded by a user who shares the video. Whenever and wherever the video is played, whether it is streamed once, downloaded and played several times thereafter, or played for a mass audience, the analytic pathway is triggered each and every time the video file is played because the elements triggering the collection of analytics exist in the video file itself. By embedding Vixels into video files at or before upload, the analytics mechanisms are triggered by the embedded Vixel regardless of how, where, when, and by whom the video is played back, forming the framework for a simpler and more accurate analytics network.

Abstract: Provided are a method and device for adjusting playback progress of a video file. The method includes: receiving text information to be searched; searching, in a caption file of the video file, for caption content matching the text information, wherein the caption file is acquired from the video file or generated according to the video file; and determining playback time point corresponding to the caption content according to the found caption content, and adjusting the playback progress of the video file according to the playback time point. According to the technical solution provided in the disclosure, accurate positioning of a clip which a user expects to replay is achieved, and the operation is simple and convenient.

Abstract: A method for video browsing includes comparing a current image frame with a previous image frame prior to the current image frame in a video to obtain target block information, identifying the current image frame as a keyframe if the target block information satisfies a predetermined condition, and playing the keyframe.

Abstract: A gas-charging head for charging a device with gas includes a body and at least one valve mounted on the body. The body includes a plurality of channels in communication with an interior space of the device operable to permit a flow of gas therethrough. At least one valve mounted on the body is in communication with a channel of the plurality of channels. The body and a portion of a channel are operable as a valve manifold for the valve. In another embodiment, a system for charging the device with gas that includes a proportional-integral-differential (PID) controller is provided. In yet another embodiment, a method of charging the device with a gas is also provided. The device may be a hard-disk drive, and the gas may be helium without limitation thereto.

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract: A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

Abstract: Systems and methods for managing open tabs of an application are provided. In some aspects, a page is presented in a first tab from among multiple tabs open in an application at a computing device. That a content of the page presented in the first tab is different from a default content of the page stored at a web server is determined. Contents of the multiple tabs are retained in a random access memory (RAM). A request is received to reduce an amount of the RAM used by the application. The content of the page presented in the first tab is stored. In response to the request to reduce the amount of the RAM used by the application, a content presented in a second tab from among the plurality of tabs is removed from the RAM.

Abstract: Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves applying a first voltage with a first polarity to a plurality of the memory cells. The method involves applying a second voltage with a second polarity to one or more of the plurality of memory cells. The method involves detecting electrical responses of the one or more memory cells to the first voltage and the second voltage. The method also involves determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.

Abstract: A method for providing a magnetic junction usable in a magnetic device and a magnetic junction are described. A reference layer, a crystalline MgO tunneling barrier layer and a free layer are provided. The crystalline MgO tunneling barrier layer is continuous, has a (001) orientation and has a thickness of not more than eleven Angstroms and not less than two Angstroms. The crystalline MgO tunneling barrier layer is between the free layer and the reference layer. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: According to one embodiment, the magnetic memory device includes a first magnetoresistive element and a second magnetoresistive element which are adjacent to each other. Each of the first and second magnetoresistive elements includes a first magnetic layer, a first non-magnetic later on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer. Furthermore, the magnetic memory device further includes a fourth magnetic layer being in contact with the first and second magnetoresistive elements or in contact with conductive layers on the first and second magnetoresistive elements.

Abstract: A multi-bit magnetic random access memory (MRAM) cell including a magnetic tunnel junction including: a first magnetic storage layer, a second magnetic storage layer, a magnetic sense layer, a first spacer layer between the first magnetic storage layer and the magnetic sense layer, and a second spacer layer between the second magnetic storage layer and the sense layer. The first and second storage magnetization are switchable between m directions to store data corresponding to one of m2 logic states, with m>2. The present disclosure further concerns a method for writing and reading to the MRAM cell and to memory devices including multi-bit MRAM cells.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense amplifier. The memory cell includes a resistance change element. The reference voltage generating circuit generates a reference adjustment voltage. The first transistor provides a reference current in accordance with the reference adjustment voltage. The sense amplifier compares a cell current flowing through the memory cell with the reference current flowing through the first transistor.

Abstract: Improved STT MRAM midpoint reference cell configurations are provided. In one aspect, a STT MRAM midpoint reference cell includes: a plurality of word lines having at least one write reference word line and at least one read reference word line; a plurality of bit lines perpendicular to the word lines; at least one source line perpendicular to the bit lines; at least one first magnetic tunnel junction in series with i) a first field effect transistor gated by the write reference word line and ii) a second field effect transistor gated by the read reference word line; and at least one second magnetic tunnel junction in series with iii) a third field effect transistor gated by the write reference word line and iv) a fourth field effect transistor gated by the read reference word line. A method of operating a STT MRAM midpoint reference cell is also provided.

Abstract: Integrated circuits with memory cells and methods of programming the memory cells are provided. In an exemplary embodiment, a method of programming a memory cell includes determining a memory cell temperature for a memory cell within an integrated circuit. A pulse number is determined, where the pulse number is the number of electrical pulses at a set voltage required to program the memory cell at the memory cell temperature. The memory cell is programmed with a write operation, where the write operation includes the pulse number of electrical pulses.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Abstract: A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.

Abstract: A DRAM circuit includes an array having a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line. The second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated. A redundant refresh circuit is configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated; and a row decoder is configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line.

Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Abstract: A memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.

Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

Abstract: A nonvolatile memory module including a plurality of memory chips and a module controller on a printed circuit board (PCB) may be provided. Each of the plurality of memory chips may include a plurality of nonvolatile memory cell array layers stacked on a substrate in a three dimensional structure. The module controller may control operations of the plurality of memory chips. The module controller may operate each of the plurality of nonvolatile memory cell array layers included in each of the plurality of memory chips in one of a memory mode, in which a corresponding nonvolatile memory cell array layer is used as a working memory area that temporarily stores data for an operation of the nonvolatile memory module, and a storage mode, in which the corresponding nonvolatile memory cell array layer is used as a storage area that preserves data.

Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

Abstract: The disclosed technology provides enables incremental step pulse programming (ISPP) operations with variable pulse step height control. In particular, a storage device is configured to select a pulse step height for an ISPP operation of one or more memory cells of a storage device based on a write frequency of data programmed via the ISPP operation. The storage device saves the data by applying a series of electrical pulses to the one or more memory cells, each subsequent pulse increasing in magnitude by the selected pulse step height.

Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory controller includes a storage module configured to store data indicating threshold voltage shift read parameters and corresponding index values. The nonvolatile memory controller includes a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device, and a read circuit configured to determine whether a usage characteristic meets a usage characteristic threshold. When a usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent reads of the nonvolatile memory device using a threshold voltage shift read instruction identified using one or more of the threshold voltage shift read parameters.

Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.

Abstract: A storage device includes a flash memory and a memory controller. The flash memory includes a plurality of memory blocks. The memory controller is configured to determine a fast cycle weight corresponding to a reuse period of a selected memory block among the plurality of memory blocks, and to manage wear leveling of the selected memory block using the fast cycle weight.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.

Abstract: A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at least one memory module having a first pin unit connected to the main IC, and a second group of memory modules including at least one memory module having a second pin unit connected to the main IC. The groups of memory modules and the main IC are arrayed in a first direction on a substrate, and the second group of memory modules is offset with respect to the first group of memory modules in a second direction that is perpendicular to the first direction so as to have a position relative to the main IC in the second direction that is different from that of the first group of memory modules.

Abstract: A memory includes a plurality of replacement word lines interspersed among the plurality of word lines. The memory also includes a word line control circuit configured to apply different voltages to different word lines of the plurality of word lines based on positions of the word lines, and to replace a defective word line of the plurality of word lines with a replacement word line.

Abstract: A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.

Abstract: Fuel bundles for a nuclear reactor are disclosed, and in some embodiments include a first fuel element including thorium dioxide; a second fuel element including uranium having a first fissile content; and a third fuel element including uranium having a second fissile content different from the first fissile content. Nuclear reactors using such fuel bundles are also disclosed, including pressurized heavy water nuclear reactors. The uranium having the different fissile contents can include combinations of natural uranium, depleted uranium, recycled uranium, slightly enriched uranium, and low enriched uranium.

Abstract: A process for controlling the dissolution of a metal in an acid bath is described. The metal may comprise aluminum and the acid bath may contain a metal catalyst that causes the metal to dissolve. In order to control the rate of dissolution, the metal can be contacted with a cathodic member. In one embodiment, the process can be completely stopped even without removing the metal from the acid bath. The cathodic member provides anodic protection to the metal. In one embodiment, the cathodic member is made from a nickel-chromium-based alloy.

Abstract: Illustrative embodiments provide methods and systems for migrating fuel assemblies in a nuclear fission reactor, methods of operating a nuclear fission traveling wave reactor, methods of controlling a nuclear fission traveling wave reactor, systems for controlling a nuclear fission traveling wave reactor, computer software program products for controlling a nuclear fission traveling wave reactor, and nuclear fission traveling wave reactors with systems for migrating fuel assemblies.

Abstract: A method and system for the thermoelectric conversion of nuclear reactor generated heat including upon a nuclear reactor system shutdown event, thermoelectrically converting nuclear reactor generated heat to electrical energy and supplying the electrical energy to a mechanical pump of the nuclear reactor system.

Abstract: Provided is a method of treating radioactive liquid waste which reduces the amount of radioactive waste to be generated and is capable of removing a radioactive nuclide from radioactive liquid waste to the extent that the concentration thereof is less than or equal to the measurement lower limit using a simple apparatus configuration. A filtration device is connected to a colloid removal device by a connection pipe. An adsorption tower positioned at the highest stream of an adsorption device is connected to the colloid removal device by a connection pipe. The colloid removal device includes an electrostatic filter. Respective adsorption towers in the adsorption device are sequentially connected by a pipe. A discharge pipe is connected to the adsorption tower positioned at the lowest stream of the adsorption device. Radioactive liquid waste, containing particles having a particle diameter of 1 ?m or greater, negatively charged colloids, and a radioactive nuclide, is supplied to the filtration device.