Patents Issued in November 2, 2017
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Publication number: 20170315881Abstract: Presented herein are methods, non-transitory computer readable media, and devices for efficiently repairing tree databases with variable-length records. Methods for repairing tree databases with variable-length records are disclosed which include: iterating the tree database, detecting at least one recoverable leaf block, reducing the at least one recoverable leaf block to its legally formatted contents, and writing the at least one recoverable leaf block back into the tree database; processing the at least one recoverable leaf block to ensure the at least one recoverable leaf block represents a disjoint region within a record space within the tree database; and rebuilding branch blocks as necessary to provide a lookup and organizational index for the at least one recoverable leaf block.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventor: Richard P. JERNIGAN, IV
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Publication number: 20170315882Abstract: Systems and methods for replicating object-based operations generated based on file system commands are disclosed. In an aspect, an object storage backed file system (OSFS) translates each of multiple file system commands into a respective transaction group of one or more object-based operations. A transaction identifier is assigned to the object-based operations in each of the transaction groups. An OSFS cache records the transaction groups to an intent log that buffers the transaction groups prior to commitment of the object-based operations to a backend object store. The OSFS cache determines for each of the transaction groups, whether the transaction group modifies a file system namespace.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Ghassan Abdallah Yammine, Derek William Beard
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Publication number: 20170315883Abstract: A data storage system has at least two universal nodes each having CPU resources, memory resources, network interface resources, and a storage virtualizer. A system controller communicates with all of the nodes. Each storage virtualizer in each universal node is allocated by the system controller a number of storage provider resources that it manages. The system controller maintains a map for dependency of virtual appliances to storage providers, and the storage virtualizer provides storage to its dependent virtual appliances either locally or through a network protocol (N_IOC, S_IOC) to another universal node. The storage virtualizer manages storage providers and is tolerant to fault conditions. The storage virtualizer can migrate from any one universal node to any other universal node.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Applicant: MPSTOR LIMITEDInventor: William OPPERMANN
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Publication number: 20170315884Abstract: A controller monitors access frequencies of address ranges mapped to a data storage array. Based on the monitoring, the controller identifies frequently accessed ones of the address ranges that have lower associated wear, for example, those that are read more often than written. In response to the identifying, the controller initiates copying of a dataset associated with the identified address ranges from the data storage array to a spare storage device while refraining from copying other data from the data storage array onto the spare storage device. The controller directs read input/output operations (IOPs) targeting the identified address ranges to be serviced by access to the spare storage device. In response to a failure of a failed storage device among the plurality of primary storage devices, the controller rebuilds contents of the failed storage device on the spare storage device in place of the dataset associated with the identified address ranges.Type: ApplicationFiled: June 26, 2017Publication date: November 2, 2017Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Andrew D. WALLS
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Publication number: 20170315885Abstract: The method and system of the present invention provides an improved technique for processing email during an unplanned outage. Email messages are redirected from the primary server to a secondary server during an unplanned outage such as, for example, a natural disaster. A notification message is sent to users alerting them that their email messages are available on the secondary server by, for example, Internet access. After the termination of the unplanned outage, email messages received during the unplanned outage are synchronized into the users standard email application.Type: ApplicationFiled: July 20, 2017Publication date: November 2, 2017Applicant: MessageOne, Inc.Inventors: Samy Mahmoud Aboel-Nil, Satin Mirchandani, Michael Nonemacher, Igor Postelnik, Michael I. Rosenfelt, Chris Scharff
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Publication number: 20170315886Abstract: Disclosed are various embodiments for distributing data items. A plurality of nodes forms a distributed data store. A new master candidate is determined through an election among the plurality of nodes. Before performing a failover from a failed master to the new master candidate, a consensus is reached among a locality-based failover quorum of the nodes. The quorum excludes any of the nodes that are in a failover quorum ineligibility mode.Type: ApplicationFiled: July 14, 2017Publication date: November 2, 2017Inventors: MICHAEL T. HELMICK, JAKUB KULESZA, STEFANO STEFANI, DAVID A. LUTZ
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Publication number: 20170315887Abstract: A rework re-timer with forward error correction handling is disclosed. An example first intermediate transceiver includes a first interface to communicatively couple the first intermediate transceiver with a first computing device, a second interface to communicatively couple the first intermediate transceiver to a second intermediate transceiver configured to be communicatively coupled with a second computing device, an auto-negotiation controller to: terminate a first auto-negotiation with the first computing device before the first auto-negotiation is completed, transmit, to the second transceiver, first capabilities of the first computing device determined during the first auto-negotiation, and perform a second auto-negotiation with the first computing device utilizing the first capabilities of the first computing device and second capabilities of the second computing device received from the second transceiver.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: David M. Olson, John Wastlick, Jason Jung, Kevin B. Leigh
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Publication number: 20170315888Abstract: Systems and techniques for recovering a storage array are disclosed. These systems and techniques include determining a size corresponding to a storage stripe of the storage array. Pieces assigned to the storage stripe are identified. A storage configuration corresponding to the pieces assigned to the storage stripe is detected. Ordinal information and parity information are determined corresponding to the pieces assigned to the storage stripe. The size determined corresponding to the storage stripe, identification of the pieces assigned to the storage stripe, the storage configuration, the ordinal information, and the parity information is stored in a data store to reconstruct lost or corrupted metadata corresponding to the storage array.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Joseph Blount, William P. Delaney, Charles Binford, Joseph Moore, Randolph Sterns
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Publication number: 20170315889Abstract: In one embodiment, a solid state drive (SSD) with power loss protection (PLP) includes a SSD controller, a secondary controller and a power circuit configured to supply power to the SSD from a power source during normal operation and backup power from a backup power source in response to a loss of power supplied by the power source. In the event of a loss of power, the secondary controller is configured to track the holdup time, or duration of time for which the primary controller can operate on backup power. In one embodiment, the holdup time tracked by the secondary controller is stored in a non-volatile memory in communication with the secondary controller.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Christopher Delaney, Leland Thompson, John Hamilton, Gordon Waidhofer, Ali Aiouaz
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Publication number: 20170315890Abstract: A method, a computing device, and a non-transitory machine-readable medium for replacing an unreadable sector in a storage system is provided. In some embodiments, the method includes identifying a sector from a plurality of sectors in a physical memory of a storage device in a storage system as an unreadable sector. An unreadable sector is a sector that includes data that had been corrupted and cannot be recovered from data in the storage system. In some embodiments, the unreadable sector is recovered by receiving a copy of a sector identified as the unreadable sector from a cloud storage, where the copy of the sector stores readable data and the cloud storage is a separate storage from the storage system. The method then includes replacing the unreadable sector with the copy at the sector at a memory location in the physical memory occupied by the unreadable sector.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Mahmoud K. Jibbe, Keith Holt
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Publication number: 20170315891Abstract: A storage device including: a nonvolatile memory device including a plurality of nonvolatile memory cells, a partial storage area and an overprovision storage area; and a controller configured to control the nonvolatile memory device, wherein when the controller detects a fault of the nonvolatile memory device, the controller negates the partial storage area, reassigns the overprovision storage area, which corresponds to a size of a user area, among the partial storage area, determines a device fail if the overprovision storage area is less than an overprovision threshold after the reassigning of the partial storage area, and determines a recovery success if the overprovision storage area is equal to or greater than the overprovision threshold after the reassigning of the partial storage area.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: JI HYUNG PARK, HyunJung Shin, Isaac Baek, Jeonguk Kang, Minseok Ko
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Publication number: 20170315892Abstract: A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock signal, a second input terminal coupled to the memory device for receiving the notification signal, a select terminal for receiving a selection signal, and an output terminal for outputting a memory clock signal to the memory device. The memory clock signal is one of the external clock signal and the notification signal. The built-in self-test circuit is for outputting a control signal required by the memory device to perform the read operation or the write operation and check whether the memory device functions normally.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventor: Hsin-Wen Chen
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System and method for using data tags to track and manage tasks to provide object-to-object services
Publication number: 20170315893Abstract: The present invention relates to a method and system that use data tags to track tasks in applications to provide Object-to-Object (OTO) services. A first application data tag is issued by a data tag server as in an OTO service platform in response to an initiation of a first application by a first initiator. The first data tag specifies at least one first task for fulfilling a first service. The first application data tag is scanned by a first user terminal by a first participant. A first action data tag is issued by the data tag server. A first dynamically variable task data tag is issued by the data tag server to track the first task in the first action. The first dynamically variable task data tag is updated to record the completion of the first task in the first action when the first task is completed.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventor: Lidong Qu -
Publication number: 20170315894Abstract: A virtual machine may allow execution of applications decoupled from physical hardware. The virtual machine may be executed by the physical hardware in a data center. A system can monitor and assess performance and reliability of the virtual machine based on device records of network components of the data center that are supporting operation of the virtual machine.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventors: Andrew Babakhan, Jeffrey Zhou, Neale Rowe, Peter Leung
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Publication number: 20170315895Abstract: An embodiment of the invention may include a method, computer program product and computer system for a cable removal system. The embodiment may include a computing device that determines whether a user is contacting a network cable. The network cable is physical connection between a first device and a second device. The first device includes at least one network port. The embodiment may include a computing device determining whether an information transmission across the network cable can be rerouted based on determining that the user is contacting the network cable. The embodiment may include a computing device rerouting information transmission based on determining that the information transmission across the network cable can be rerouted. The embodiment may include a computing device alerting the user that there is no information transmission across the network cable based on rerouting the information transmission.Type: ApplicationFiled: May 2, 2016Publication date: November 2, 2017Inventors: Daniel S. Critchley, Gordon D. Hutchison, Gareth P. Jones, Jonathan W. L. Short
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Publication number: 20170315896Abstract: A module health system includes a module health circuit comprising a hardware register that is set to a first value in response to the system starting, an application register that is set to the first value in response to the system starting and a watchdog timer register that is set to the first value in response to the system starting. The system further includes a power on self-test that determines whether the system has passed a plurality of tests and that selectively sets the hardware register to a second value based on the determination, an external software application that determines whether a safety critical system is healthy and selectively sets the application register based on the determination, a watchdog timer application that selectively sets the watchdog timer register, a central processing unit that determines whether to de-assert a module health signal.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Pasi Jukka Petteri VAANANEN, Martin Peter John CORNES, Shlomo PRI-TAL
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Publication number: 20170315897Abstract: Generating a performance policy for a server. A plurality of system metrics of a first server is monitored, and a benchmark for the plurality of system metrics based on the monitored plurality of system metrics is stored. The benchmark indicates desirable system metrics of the first server. An operating policy for a second server is generated from the stored benchmark. The operating policy includes desirable system metrics of the second server based on the desirable system metrics of the first server.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Michael D. Brooks, James A. Harrison, Robert C. Jones, Philip R. Lee, Catherine M. Moxey, Mayur Raja
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Publication number: 20170315898Abstract: Method, computer program product, and system for dynamic tracing, including monitoring a log file, wherein the log file comprises events, wherein an event comprises an event code and an event time stamp, receiving a ranking and rating table (“table”), wherein the table comprises one or more error codes and a ranking for each of the one or more error codes, matching the event code with an error code of the one or more error codes, calculating a rating for the error code, comparing the calculated rating to a rating threshold, enabling an information capture level based on the rating threshold of the calculated rating, in response to enabling the information capture level, copying events from the log file into an abbreviated log file, wherein the copied events include the error code for the calculated rating, creating an alert indicating a changed information capture level, and resetting the dynamic tracing.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Javed Iqbal Abdul, Jose Peter
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Publication number: 20170315899Abstract: Method, computer program product, and system for dynamic tracing, including monitoring a log file, wherein the log file comprises events, wherein an event comprises an event code and an event time stamp, receiving a ranking and rating table (“table”), wherein the table comprises one or more error codes and a ranking for each of the one or more error codes, matching the event code with an error code of the one or more error codes, calculating a rating for the error code, comparing the calculated rating to a rating threshold, enabling an information capture level based on the rating threshold of the calculated rating, in response to enabling the information capture level, copying events from the log file into an abbreviated log file, wherein the copied events include the error code for the calculated rating, creating an alert indicating a changed information capture level, and resetting the dynamic tracing.Type: ApplicationFiled: July 26, 2017Publication date: November 2, 2017Inventors: Javed Iqbal Abdul, Jose Peter
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Publication number: 20170315900Abstract: Application management based on data correlations is disclosed. One example is a system including a data processor, a data element generator, a matrix generator, a data analysis module, a performance module, and a load test manager. The data processor accesses test data based on an application under load testing. The data element generator generates a plurality of transactional data elements based on the test data, each data element comprising at least three data components. The matrix generator generates a covariance matrix based on the data components. The data analysis module determines an eigenvector associated with the covariance matrix, and identifies a correlation between a sub-plurality of the at least three data components based on coefficients of the eigenvector. The performance module determines, based on the correlation, performance metrics for the application under load testing. The load test manager manages, based on the performance metrics, the application under load testing.Type: ApplicationFiled: November 24, 2014Publication date: November 2, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Elad BENEDICT, Ohad ASSULIN, Efrat EGOZI LEVI
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Publication number: 20170315901Abstract: A method, a device and a medium for managing an application program are provided. The method includes: type information of a first application program running on a foreground of a terminal is acquired; and the first application program is prevented from being debugged by other application programs if the type information of the first application program is preset type information.Type: ApplicationFiled: December 14, 2016Publication date: November 2, 2017Inventors: Yufei WANG, Chenxi WANG, Ming LIU
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Publication number: 20170315902Abstract: A method and system for testing the end-to-end performance of cloud based applications. Real workload is created for the cloud based applications using synthetic users. The load and length of demand may be adjusted to address different models allowing the measurement and analysis of user performance metrics under desired conditions. Web applications and other cloud services may be tested from multiple cloud-based concurrent geographic locations in the world. The method may include generating controlled and complex web load from multiple concurrent geographic locations. The method may also include splitting traffic among multiple geographic locations. The method may also include processing test results and generating performance metrics per location as well as comparing locations. The method may also be applicable to cloud services such as mobile apps and API endpoints.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Applicant: Cloudy Days, Inc. dba NouvolaInventors: Paola Moretto, Paola Rossaro, Shawn MacArthur
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Publication number: 20170315903Abstract: Systems and methods automatically detect violations of coding rules of a coding standard in computer programming code. The systems and methods may mark the locations in the code where the violations are found. The coding rules may be mapped to code verification checks that check for undesired runtime behavior in the code. The systems and methods may identify the code verification check mapped to a given violation detected in the code. The systems and methods may apply that check to the code. If the check proves that the undesired runtime behavior will not occur, the violation may be marked as justified. If the check proves that the undesired runtime behavior will occur, the violation may be marked as not justified.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Stefan David, Patrick Munier, Alexandre De Barros, Bernd J. Kanamueller, Peter S. Szpak
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Publication number: 20170315904Abstract: Systems and methods for performing integration testing of an Information Technology (IT) infrastructure are disclosed. In one embodiment, the method comprises receiving one or more infrastructure parameters from at least one data source. The method further comprises identifying at least one infrastructure element by analyzing the one or more infrastructure parameters. The method further comprises determining an infrastructure landscape by performing at least one validation operation on the at least one infrastructure element. The infrastructure landscape indicates a topology of the at least one infrastructure element in the IT infrastructure. The method further comprises selecting one or more agnostic test cases from a test case repository based on the infrastructure landscape. The method further comprises executing the one or more agnostic test cases to perform integration testing of the IT infrastructure.Type: ApplicationFiled: June 13, 2016Publication date: November 2, 2017Inventors: Prasad Tharippala, Arpitha Honne Gowda, Chinmay Manjunath, Ramprasad Jandhyala
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Publication number: 20170315905Abstract: A method for automatically validating data against a predefined data specification, includes: a) acquiring data to be validated (2), the data including a plurality of test objects, b) acquiring a test database (4) including a plurality of test files each defining a test scenario, c) acquiring a predefined data specification (6) against which the test objects must be validated, d) automatically generating a plurality of test scripts (8), from the acquired test files and using relevant data from the test objects of the acquired predefined data specification, e) for each generated test script, executing the test script (10) on the test objects, and f) automatically generating a test report (12) including a result of each executed test case.Type: ApplicationFiled: April 19, 2017Publication date: November 2, 2017Inventors: Abhijeet CHOUDHURY, Mallikarjun BASAVARAJAPPA, Anita MENON, Pran SHEOKAND
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Publication number: 20170315906Abstract: The present invention concerns a method for allocating a space of predetermined size in a memory (2) of a smart card (1), characterized in that it comprises steps of: deterministic preselection (100) in the memory (2), of at least one free zone having a size larger than the predetermined size, selection, (104) in a preselected free zone of a sub-zone having a size equal to the predetermined size, the selection of the sub-zone being variable for one same preselected free zone, use (106) of the selected sub-zone as allocated memory space.Type: ApplicationFiled: April 26, 2017Publication date: November 2, 2017Inventor: Pascal François Paul DUMAS
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Publication number: 20170315907Abstract: Systems and methods for virtual machine based huge page balloon support are provided. A guest operating system (OS) receives a request from a hypervisor for guest memory to be made available to a host operating system (OS). The guest OS further receives a huge page size of a host page and a quantity of requested guest memory. The guest OS then allocates unused guest memory and transmits at least one address of the allocated guest memory to the hypervisor, where the allocated guest memory is a contiguous block of memory that is at least the size of the huge page size and aligned to the size of the huge page size.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventor: Michael Tsirkin
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Publication number: 20170315908Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.Type: ApplicationFiled: April 25, 2017Publication date: November 2, 2017Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
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Publication number: 20170315909Abstract: A method for accessing a flash memory module is provide. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.Type: ApplicationFiled: April 26, 2017Publication date: November 2, 2017Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
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Publication number: 20170315910Abstract: An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.Type: ApplicationFiled: July 10, 2017Publication date: November 2, 2017Inventors: Dan F Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer
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Publication number: 20170315911Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventor: Stuart Allen Berke
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Publication number: 20170315912Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Joseph Wright, Erik Michael Schlanger, Eric DeVolder
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Publication number: 20170315913Abstract: A system and method for improving the management of data input and output (I/O) operations for Shingled Magnetic Recording (SMR) devices in a network storage system is disclosed. The storage system includes a storage controller that receives a series of write requests for data blocks to be written to non-sequential addresses within a pool of SMR devices. The storage controller writes the data blocks from the series of write requests to a corresponding sequence of data clusters allocated within a first data cache of the storage controller for a thinly provisioned volume of the pool of SMR devices. Upon determining that a current utilization of the first data cache's data storage capacity exceeds a threshold, the sequence of data clusters including the data blocks from the first data cache are transferred to sequential physical addresses within the SMR devices.Type: ApplicationFiled: March 15, 2017Publication date: November 2, 2017Inventors: Mahmoud K. Jibbe, Keith Holt, Scott Terrill
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Publication number: 20170315914Abstract: A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing write requests in an order based on information in the read queue. When the write queue is under the low watermark, the method includes stopping the draining of the write queue and again processing the read requests in the read queue.Type: ApplicationFiled: October 31, 2014Publication date: November 2, 2017Inventors: Naveen Muralimanohar, Rajeev Balasubramonian
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Publication number: 20170315915Abstract: The described embodiments include a computing device that has two or more levels of memory, each level of memory having different performance characteristics. During operation, the computing device receives a request to lease an available block of memory in a specified level of memory for storing an object. When a block of memory is available for leasing in the specified level of memory, the computing device stores the object in the block of memory in the specified level of memory. The computing device also commences the lease for the block of memory by setting an indicator for the block of memory to indicate that the block of memory is leased. During the lease (i.e., until the lease is terminated), the object is kept in the block of memory.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventor: Mitesh Meswani
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Publication number: 20170315916Abstract: The present invention provide a directory management method including: receiving, by a first NC, a first data access request sent by a first processor on a local node; if the first NC determines that a first directory does not include a directory entry corresponding to a first access address and the first directory does not include an idle directory entry, clearing, by the first NC, directory content of a directory entry from the first directory; writing, by the first NC, directory content corresponding to the first data access request to the cleared directory entry; and if the first NC determines that a first snoop request is received, sending, by the first NC, a first snoop message to the processor on the local node.Type: ApplicationFiled: April 28, 2017Publication date: November 2, 2017Inventors: Yongbo Cheng, Kejia Lan, Chenghong He
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Publication number: 20170315917Abstract: Metadata history is collected for operations performed by an application as directed by a user. In a subsequent interaction by the user with the application, interaction metadata for the interaction is matched to a pattern in the metadata history. An operation identified in the pattern is processed as a background process and results from processing the operation are pre-staged in cache of the device being operated by the user. When the user requests the operation during the subsequent interaction with the application, the pre-staged results from the cache are provided to the user.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Leo Yamamoto, Lakshmanan Chinnaveerappan, Eric Wang
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Publication number: 20170315918Abstract: A method for storing objects in a storage, wherein the storage has a predetermined capacity, includes providing an expected popularity and an uncertainty of the expected popularity for each of the objects, and selecting a set of the objects for storing in the storage, wherein the set of is selected on the basis of the expected popularity, the uncertainty and the capacity of the storage.Type: ApplicationFiled: November 10, 2015Publication date: November 2, 2017Inventors: Sofia Nikitaki, Mohamed Ahmed, Saverio Niccolini
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Publication number: 20170315919Abstract: A technique for operating a lower level cache memory of a data processing system includes receiving an operation that is associated with a first thread. Logical partition (LPAR) information for the operation is used to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: GUY L. GUTHRIE, HUGH SHEN, DEREK E. WILLIAMS
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Publication number: 20170315920Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
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Publication number: 20170315921Abstract: A a set associative cache memory, comprising: an array of storage elements arranged as N ways; an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory; wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs, wherein the MAT is received by the cache memory; a mapping that, for each MAT of the plurality of predetermined MATs, associates the MAT with a subset of one or more ways of the N ways; wherein for each memory access of the memory accesses, the allocation unit allocates into a way of the subset of one or more ways that the mapping associates with the MAT of the memory access; and wherein the mapping is dynamically updatable during operation of the cache memory.Type: ApplicationFiled: December 14, 2014Publication date: November 2, 2017Inventors: RODNEY E. HOOKER, DOUGLAS R. REED, JOHN MICHAEL GREER, COLIN EDDY
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Publication number: 20170315922Abstract: A technique for operating a lower level cache memory of a data processing system includes receiving, by a store queue controller, an operation that is associated with a first thread. The store queue controller uses level one (L1) cache memory miss information for the operation to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Guy L. GUTHRIE, Hugh SHEN, Derek E. WILLIAMS
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Publication number: 20170315923Abstract: Exemplary methods, apparatuses, and systems receive from a client a request to access data from a client. Whether metadata for the data is stored in a first caching layer is determined. In response to the metadata for the data not being stored in the first caching layer, it is determined if the data is stored in the second caching layer. In response to determining that the data is stored in the second caching layer, the data is retrieved from the second caching layer. In response to determining that the data is not stored in the second caching layer, writing of the data to the second caching layer is bypassed. The retrieved data is sent to the client.Type: ApplicationFiled: September 8, 2016Publication date: November 2, 2017Inventors: SANKARAN SIVATHANU, SAI INABATTINI
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Publication number: 20170315924Abstract: A method, a computing device, and a non-transitory machine-readable medium for allocating memory to data structures that map a first address space to a second is provided. In some embodiments, the method includes identifying, by a storage system, a pool of memory resources to allocate among a plurality of address maps. Each of the plurality of address maps includes at least one entry that maps an address in a first address space to an address in a second address space. An activity metric is determined for each of the plurality of address maps, and a portion of the pool of memory is allocated to each of the plurality of address maps based on the respective activity metric. The allocating of the portion of the memory pool to a first map may be performed in response to a merge operation being performed on the first map.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Joseph Blount, William P. Delaney, Charles Binford, Joseph Moore, Randolph Sterns
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Publication number: 20170315925Abstract: A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.Type: ApplicationFiled: June 16, 2016Publication date: November 2, 2017Inventor: Chih-Kang Yeh
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Publication number: 20170315926Abstract: Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page tables by virtual machine (VM) guest software through the manipulation of extended page tables. The system may include a translation look-aside buffer (TLB) to maintain a policy to lock one or more guest linear addresses (GLAs) to one or more allowable guest physical addresses (GPAs); a page walk processor to update the TLB based on the guest page tables; and a page table edit control (PTEC) module to: identify entries of the guest page tables that map GLAs associated with the policy to a first GPA; verify that the mapping conforms to the policy; and place the guest page table into one of a plurality of restricted accessibility states based on the verification, the restricted accessibility applied to the VM guests and to the page walk processor.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Applicant: INTEL CORPORATIONInventors: MICHAEL LEMAY, DAVID M. DURHAM, ANDREW V. ANDERSON, GILBERT NEIGER, RAVI L. SAHITA
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Publication number: 20170315927Abstract: Methods and apparatus obtain one or more system page table entries that represent virtual system (e.g., memory) page to physical system page translations. A number of the obtained system page table entries that can be encoded in each of a plurality of translation lookaside buffer (TLB) entry encoding formats are determined. The method and apparatus may select one of the TLB entry encoding formats that encode a number of the obtained system page table entries. The method and apparatus may encode a number of obtained system page table entries in the TLB entry encoding format selected into a compressed encoding format TLB entry. The method and apparatus may associate the compressed encoding format TLB entry with an encoding format indication of the encoding format selected. The method and apparatus may decode a compressed encoding format TLB entry based on a determined TLB entry encoding format.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gabriel H. Loh, Jimshed Mirza
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Publication number: 20170315928Abstract: Exemplary embodiments relate to cache replacement schemes. Incoming data may be sorted into buckets. When it comes time to replace information in the cache, an entire bucket may be eliminated or replaced at once. By sorting incoming data into the buckets and performing cache replacement on a bucket-by-bucket basis, cache fragmentation is reduced. Moreover, the buckets may be scored based on characteristics of the data in the buckets (e.g., whether a data item is cold archived, whether a customer has pinned the data item, or whether the customer has requested early eviction of the data item). By accounting for these metrics when the cache score is calculated, cache usage and hit rates may be improved. According to exemplary embodiments, scoring may be applied to entire buckets, or may be applied to individual cache items (e.g., for use as a cache replacement metric in a cache eviction scheme).Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Vinay Hangud, Sharad Jain, Sudhindra Prasad Tirupati Nagaraj
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Publication number: 20170315929Abstract: A page replacement algorithm is provided. An idle range of memory pages is determined based, at least in part, on indications of references to memory pages in the idle range of memory pages, wherein the idle range of memory pages is a set of one or more memory pages. A first memory page is identified in the idle range of memory page for paging out of memory. The first memory page is identified based, at least in part, on indications of modifications to the memory pages. The first memory page is paged out of memory.Type: ApplicationFiled: July 21, 2017Publication date: November 2, 2017Inventors: Mengze Liao, Jiang Yu
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Publication number: 20170315930Abstract: Exemplary embodiments relate to cache replacement schemes. Incoming data may be sorted into buckets. When it comes time to replace information in the cache, an entire bucket may be eliminated or replaced at once. By sorting incoming data into the buckets and performing cache replacement on a bucket-by-bucket basis, cache fragmentation is reduced. Moreover, the buckets may be scored based on characteristics of the data in the buckets (e.g., whether a data item is cold archived, whether a customer has pinned the data item, or whether the customer has requested early eviction of the data item). By accounting for these metrics when the cache score is calculated, cache usage and hit rates may be improved. According to exemplary embodiments, scoring may be applied to entire buckets, or may be applied to individual cache items (e.g., for use as a cache replacement metric in a cache eviction scheme).Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Vinay Hangud, Sharad Jain, Sudhindra Prasad Tirupati Nagaraj