Patents Issued in January 2, 2018
  • Patent number: 9857977
    Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Kevin E. Sallese
  • Patent number: 9857978
    Abstract: A memory system includes a memory in which stored data is periodically rewritten by a refresh command, and a memory controller. The memory has an input/output (“I/O”) terminal, and the memory controller is communicatively coupled by a channel to the I/O terminal. The memory transmits a plurality of commands over the channel to the memory. The memory controller estimates a first total energy consumed based on the plurality of commands during a first sampling period, determines a temperature of the memory based on the first total energy consumed in the first sampling period, determines a first refresh cycle rate corresponding to the first temperature of the memory and transmits a refresh command to the memory based on the first refresh cycle rate.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 2, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Jason Griffin
  • Patent number: 9857979
    Abstract: A computer determines whether a page boundary of a page has been crossed by a function. Based on the computer determining that the page boundary has been crossed by the function, the computer generates a hardware exception. The computer resets one or more of a change bit and a reference bit for the page.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Asha Kiran Bondalakunta, Raghavan Devanathan, Muthulakshmi Pearl Srinivasan
  • Patent number: 9857980
    Abstract: Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: January 2, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lei Liu, Chengyong Wu, Xiaobing Feng
  • Patent number: 9857981
    Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 2, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Lin Li, Yunxing Dong, Zhiqiang Hui
  • Patent number: 9857982
    Abstract: A storage system includes data storage devices, bus conductors, and mobile reader/writer devices. Each of the storage devices is positioned between insulators, is at one of a plurality of locations on one of one or more shelf assemblies, and comprises a processor coupled to a memory and an interface device. One of the bus conductors is adjacent each of the insulators. Each of the reader/writer devices includes a transport apparatus, a processor and a memory. The transport apparatus is configured to move one of the reader/writer devices to one or more of the locations when engaged. The processor is coupled to the transport apparatus and the memory and is configured to execute machine executable code to: engage the transport apparatus to position one of the reader/writer devices to one of the locations in response to a received operation; couple power to one of the storage devices; and execute the operation.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 2, 2018
    Assignee: NetApp, Inc.
    Inventors: David Slik, Peter Corbett
  • Patent number: 9857983
    Abstract: A flash translation layer table rebuilding method for a solid state drive is provided. The solid state drive includes a non-volatile memory and a buffering circuit. Firstly, a flash translation layer table is loaded from the non-volatile memory to the buffering circuit. In case that an abnormal shutdown event occurs, plural blocks of the non-volatile memory to be read are determined according to a specified block programming serial number of the flash translation layer table. Then, a read sequence of reading the plural blocks is determined according to a block programming serial number or an auxiliary serial number corresponding to the block. The contents of the blocks are read according to the read sequence. A mapping relationship between plural physical allocation addresses and plural logical block addresses of the flash translation layer table is updated.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 2, 2018
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Liang-You Lin, Yu-Chuang Peng, Ya-Ping Pan, Ho-An Lin
  • Patent number: 9857984
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: January 2, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 9857985
    Abstract: A mechanism is provided for providing information about fragmentation of a file on a sequential access medium by a computer system is disclosed. An actual time for reading the file recorded on the sequential access medium is estimated based on a physical position of the file. A total length of the file on the sequential access medium is calculated based on a physical length of each data piece constituting the file. An expected time for reading the file by assuming that the file is rewritten continuously is estimated based on the total length of the file. Information about the fragmentation of the file is then provided based on the actual time and the expected time.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Sosuke Matsui, Shinsuke Mitsuma, Tsuyoshi Miyamura, Noriko Yamamoto
  • Patent number: 9857986
    Abstract: In at least one embodiment, a controller of a non-volatile memory array including a plurality of subdivisions stores write data within the non-volatile memory array utilizing a plurality of block stripes of differing numbers of blocks, where all of the blocks within each block stripe are drawn from different ones of the plurality of subdivisions. The controller builds new block stripes for storing write data from blocks selected based on estimated remaining endurances of blocks in each of the plurality of subdivisions.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Jason Ma, Roman A. Pletka, Lincoln T. Simmons, Sasa Tomic
  • Patent number: 9857987
    Abstract: A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on the server system are received from a set of accelerator systems. A set of data is prefetched from a memory system residing at the server system for at least one prefetch request in the set of prefetch requests. The set of data satisfies the at least one prefetch request. The set of data that has been prefetched is sent to at least one accelerator system, in the set of accelerator systems, associated with the at least one prefetch request.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Yuk Lung Chan, Rajaram B. Krishnamurthy, Carl Joseph Parris
  • Patent number: 9857988
    Abstract: According to the present disclosure is provided a device and method for mapping management in a flash memory based on partitioning the memory to a main address space and a substitute space, each partition comprising locations in the memory that are denoted by at least three statues according to which locations are mapped from the main space to the substitute space while responsively modifying the statuses.
    Type: Grant
    Filed: July 10, 2016
    Date of Patent: January 2, 2018
    Assignee: WINBOND ELECTRONICS CORPORAITON
    Inventor: Uri Kaluzhny
  • Patent number: 9857989
    Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
  • Patent number: 9857990
    Abstract: Described herein are several embodiments of systems and processes to decrease startup time for subsystems of a storage system. According to some embodiments, subsystem memory is allocated using memory-mapped files.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 2, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: David Krakov, Roman Vainbrand, Tal Ben-Moshe, Eli Dorfman, Vladislav Weinbaum, Noa Cohen
  • Patent number: 9857991
    Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takafumi Ito
  • Patent number: 9857992
    Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Kiran Pangal, Ravi J. Kumar
  • Patent number: 9857993
    Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B.Chinnakkonda Vidyapoornachary
  • Patent number: 9857994
    Abstract: A storage controller that performs control for storing in memory areas of a storage device, data that is grouped into redundant data in blocks each having a given data size. The storage controller includes a memory unit configured to store therein group information created by grouping performed such that logical addresses for a writing destination identified from a data writing request are correlated with the blocks; and a control unit configured to count in response to a data reading request, number of times of reading from a group including logical addresses for a reading destination identified from the reading request, based on the group information, and issues any one among a reading request that includes the logical addresses for the reading destination and a reading request that includes logical addresses for a memory destination of redundant data corresponding to data of the logical addresses for the reading destination.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: January 2, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Hironori Saito
  • Patent number: 9857995
    Abstract: A data storage device is disclosed comprising a volatile memory, a primary and a secondary non-volatile memory (NVM), and control circuitry coupled to the volatile memory and the primary and secondary NVM and configured to write first data to the volatile memory, write the first data from the volatile memory to the secondary NVM before writing the first data to the primary NVM, attempt to write the first data to the primary NVM, wherein, during the attempt to write the first data to the primary NVM, after a portion of the first data has been successfully written to the primary NVM, a corresponding portion of the first data is released from the secondary NVM.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 2, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: James N. Malina, Totok Sulistiomono Sujanto, Li Dong
  • Patent number: 9857996
    Abstract: Method and system are provided for predictive point-in-time copy for storage systems. The method may include: recording a frequency of writes to an area of a storage volume; and prioritizing areas for having point-in-time copies carried out based on the write frequency to an area, wherein areas in the storage volume having a high write frequency are prioritized before areas with a lower write frequency. An area may be of a coarser granularity than a region tracked for the point-in-time copy. The method may include: recording the frequency of writes to an area in a given period; and prioritizing areas by their frequency of writes in the given period immediately prior to the point-in-time copy.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventor: John P. Wilkinson
  • Patent number: 9857997
    Abstract: Provided are a computer program product, system, and method for replicating tracks from a first storage to a second and third storages. A determination is made of a track in the first storage to transfer to the second storage as part of a point-in-time copy relationship and of a stride of tracks including the target track. The stride of tracks including the target track is staged from the first storage to a cache according to the point-in-time copy relationship. The staged stride is destaged from the cache to the second storage. The stride in the cache is transferred to the third storage as part of a mirror copy relationship. The stride of tracks in the cache is demoted in response to destaging the stride of the tracks in the cache to the second storage and transferring the stride of tracks in the cache to the third storage.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Brian D. Hatfield, Gail A. Spear
  • Patent number: 9857998
    Abstract: A system includes non-volatile memory storing firmware and an embedded baseboard management controller (BMC). The BMC includes a BMC volatile memory and a BMC processor coupled to the BMC volatile memory and the non-volatile memory. The BMC processor performs a first method wherein the firmware is obtained from the non-volatile memory, instrumented, and stored on a host computer volatile memory. Also in the first method, separate copies of vital debug information about the instrumented firmware are stored on the BMC volatile memory and the host computer volatile memory. The system further includes a host computer housing the embedded BMC, the host computer volatile memory, and a host computer processor coupled to the host computer volatile memory. The host computer processor performs a second method wherein the instrumented firmware is obtained from the host computer volatile memory and executed.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vijay F. G. Lobo, Devender Rao Marri
  • Patent number: 9857999
    Abstract: Systems and methods are disclosed for estimating charge loss in solid-state memory devices using electrical sensors. A data storage device includes a solid-state non-volatile memory comprising a plurality of memory cells, a sensor configured to hold an electric charge, and a controller. The controller is configured to charge the sensor to a first charge level at a first point in time, determine a second charge level of the sensor at a second point in time, after a time period from the first point in time, and refresh data stored in the memory cells based at least in part on the determined second charge level.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 2, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dale Charles Main, Dean Mitcham Jenkins
  • Patent number: 9858000
    Abstract: A sustained status accelerating method for a storage device includes: controlling the storage device to receive a sustained status command from the outside; and controlling the storage device to enter the sustained status using a sustained valid page count (SVPC) table in response to the sustained status command so that each of a plurality of blocks constituting the storage device has a value greater than a predetermined valid page count. The SVPC table includes a valid page count with respect to each of the blocks in the storage device.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Gon Kim, Sangyong Lee, Dongbin Park, Chanik Park
  • Patent number: 9858001
    Abstract: A system and method for hijacking inodes based on replication operations received in an arbitrary order is used to assist a data replication operation from a source storage system to a destination storage system. The source storage system generates a set of replication operations as part of a replication process and transmits the replication operations in an arbitrary order. After receiving a replication operation, the system determines whether the operation is inconsistent with a corresponding destination inode. If an inconsistency exists, the system hijacks the destination inode by replacing the destination inode's metadata with data determined based on the replication operation. The system may also delete metadata from the inode and/or initialize metadata to default values if the metadata was not replaced based on the replication operation. The system then waits for a second replication operation that contains the remaining metadata and replaces the metadata based on the second replication operation.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: January 2, 2018
    Assignee: NETAPP, INC.
    Inventors: Devang K. Shah, Alan S. Driscoll
  • Patent number: 9858002
    Abstract: Systems and methods are disclosed for open block stability scanning. When a solid state memory block remains in an open state, where the block is only partially filled with written data, for a prolonged period of time, a circuit may perform a scan on the block to determine the stability of the stored data. When the scan indicates that the data is below a stability threshold, the data may be refreshed by reading the data and writing it to a new location. When the scan indicates that the data is above a stability threshold, the circuit may extend the time period in which the block may remain in the open state.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: January 2, 2018
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Patent number: 9858003
    Abstract: A storage system includes a host configured to transmit a write command and store write data in a buffer thereof, and a storage device. The storage device includes a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of sectors and each of the sectors logically divided into at least a lower page and an upper page for data storage, and a controller configured carry out a write operation to write the write data in the nonvolatile memory in response to the write command, and return a notice to the host acknowledging that the write operation is successful. When a portion of the write data are written in a lower page of a sector of a block and an upper page of the sector remains unwritten after the write operation, the host maintains the portion of the write data in the buffer even after receiving the notice.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Hashimoto, Takumi Abe
  • Patent number: 9858004
    Abstract: A method of generating one or more host key sets for one or more host devices may comprise: generating one or more node key sets for one or more ancestor nodes in a data structure; generating one or more node key sets for one or more leaf nodes in the data structure by using the one or more node key sets of the one or more ancestor nodes; and/or generating the one or more host key sets for the one or more leaf nodes by reusing the generated one or more node key sets of the one or more ancestor nodes and the node key sets of the one or more leaf nodes.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Banmeet Singh
  • Patent number: 9858005
    Abstract: Various embodiments are provided for managing a storage network system. The storage network system includes a plurality of zones. Each of the plurality of zones includes at least one storage network device. A link-down event associated with one of the storage network devices is detected. One of a plurality of zones is identified where the link-down event occurred, and a broadcast signal is transmitted in the storage network giving notice of the detected link-down event. A determination of whether alternative storage network devices in the identified one of the plurality of zones where the link-down event occurred are in a link-down state, where at least a zone table and a routing table is used for the determining. In response to all of the storage network devices being in the link-down state, the identified one of the plurality of zones where the link-down event occurred is placed in a down state.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitsutoshi Jinno, Hiroyuki Miyoshi, Hiroyuki Tanaka, Yoshihiko Terashita
  • Patent number: 9858006
    Abstract: A memory device can be used with a shared routing resource that provides access to the memory device. The memory device can include a random access memory (RAM) circuit that includes a plurality of ports configured to provide access to the RAM circuit by the shared routing resource. A memory partition register circuit can be configured to store a plurality of addresses specifying respective context partitions within the RAM circuit. A plurality of pointer register circuits that can each be associated with a corresponding port of the plurality of ports and can be configured to store a respective set of pointers that specify a location in the RAM circuit relative to a respective context partition. Addressing logic that can be configured to provide access to the RAM circuit using the respective set of pointers for each port.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: January 2, 2018
    Assignee: XILINX, INC.
    Inventor: Ephrem C. Wu
  • Patent number: 9858007
    Abstract: A controller includes a virtual memory mapped to device-side Peripheral component interconnect express address space includes virtual buffers allocation for each data transfer. Each virtual buffer is associated with a scatter/gather list entry in a host memory. The controller executes direct transfers between Peripheral component interconnect express devices and host memory without introducing address mapping dependencies between the host and device domains.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 2, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventor: Robert L. Sheffield
  • Patent number: 9858008
    Abstract: A system, method and program product for transferring contiguous blocks of data between a host storage and a flash memory. A method is disclosed that includes: receiving from a host at a flash controller a host command that specifies a contiguous set of LBAs and specifies a corresponding sub-section of an LBA to PBA mapping table; fetching the sub-section of the LBA to PBA mapping table from the host and storing the sub-section in a sub-mapping table; and for each LBA in the contiguous set of LBAs, performing a look-up into the sub-mapping table to retrieve a corresponding PBA and using the corresponding PBA to effectuate a data transfer between the host and flash memory from the flash controller.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 2, 2018
    Assignee: ScaleFlux
    Inventors: Yang Liu, Hao Zhong, Fei Sun, Tong Zhang
  • Patent number: 9858009
    Abstract: Data that is initially stored in Single Level Cell (SLC) blocks is subsequently copied (folded) to a Multi Level Cell (MLC) block where the data is stored in MLC format, the data copied in a minimum unit of a fold-set, the MLC block including a plurality of separately-selectable sets of NAND strings, data of an individual fold-set copied exclusively to two or more word lines of an individual separately-selectable set of NAND strings in the MLC block.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: January 2, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Abhijeet Bhalerao, Mrinal Kochar, Dennis S. Ea, Mikhail Palityka, Aaron Lee, Yew Yin Ng, Ivan Baran
  • Patent number: 9858010
    Abstract: A method for writing a plurality of files that reduces average seek time includes receiving data of the plutality of files requested to be written to a tape from an application of a host, dividing a group of the received plurality of files into segments with specified sizes, and writing a series of the plurality of respective segments of the group of the plurality of files in sequence in a specified order, the respective segments having the specified sizes, wherein when writing the segments in the specified order, a left end portion of the tape is postioned and respective top segments of the files are first collectively written thereto. A tape drive system in which the method for writing is implemented reduces an average time required for seek of a plurality of image files.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Masayuki Iwanaga, Yutaka Oishi
  • Patent number: 9858011
    Abstract: Using a quorum of fully updated replicas to designate a leader replica. A quorum of fully updated replicas designate a leader replica through “prepared” messages, allowing for restoration of failed replicas without a split-brain condition.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vita Bortnikov, Shlomit I. Shachor, Ilya Shnayderman
  • Patent number: 9858012
    Abstract: A read/write ratio for each of a plurality of data segments classified in a hot category as hot data segments is determined. Each of the plurality of hot data segments is ordered by the read/write ratio in a descending order. Each of a plurality of available SSD devices is ordered by a remaining life expectancy in an ascending order. Those of the plurality of hot data segments are matched with those of the plurality of hot data segments with those of the plurality of available SSD devices such that a hot data segment having a higher read/write ratio is provided to an SSD device having a smaller remaining life expectancy than another hot data segment having a lower read/write ratio.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philip M. Dudas, Paul A. Jennas, II, Larry Juarez, David Montgomery, Jason L. Peipelman, Joshua M. Rhoades, Todd C. Sorenson
  • Patent number: 9858013
    Abstract: A computer-executable method, computer program product, and system for managing metadata within a distributed data storage system, including a compute node in communication with a data storage array, the computer-executable method, computer program product, and system comprising receiving a data I/O from an application executing within the distributed data storage system, and creating a first storage system within the compute node, wherein the first storage system is enabled to manage metadata related to the data I/O, and processing the data I/O using the first storage system.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 2, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Shashwat Srivastav, Sriram Sankaran, Vishrut Shah, Qi Zhang, Jun Luo, Chen Wang, Huapeng Yuan, Karthik Navaneethakrishnan, Jie Song, Wei Yin
  • Patent number: 9858014
    Abstract: A method of operating a memory system includes managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device, and controlling operations directed to the plurality of memory groups in response to the program order information.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun Kim
  • Patent number: 9858015
    Abstract: Solid-state storage management for a system, the management including establishing, externally to a solid-state storage board, a correspondence between a first logical address and a first physical address on solid-state storage devices located on the solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses. The correspondence between the first logical address and the first physical address is accepted by the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in a location on a solid-state memory device that is accessible by an address translator module, the address translator module and the solid-state memory device located on the solid-state storage board.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan
  • Patent number: 9858016
    Abstract: In one example of the disclosure, a request for an authorization token is received via a network from a first computing device having authorization, to utilize functionality at a second computing device. The token is to provide for a third computing device a limited authorization to utilize the functionality. The token is sent to the third device. Subject data and the token are received from the third device. Validity of the token is confirmed. The subject data is sent to the second device for the second device to utilize the functionality in association with the subject data, with security accountability traceable to the first device.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: January 2, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kapaleeswaran Viswanathan, Jitendra Kumar
  • Patent number: 9858017
    Abstract: Systems and methods are provided for indicating capabilities of a printer. One embodiment is a system that includes a memory storing instructions for operating a Graphical User Interface (GUI), and a controller that presents the GUI based on the instructions. A control of the GUI includes a list of entries that each correspond with a potential printer capability. Responsive to detecting new text entered into a text field, the GUI displays an add button. In response to detecting a cursor over an entry in the list: the GUI displays a select button for selecting the entry to indicate actual capabilities of a specific printer. In response to detecting that a user has clicked on one of the select buttons to indicate an actual capability of the printer, the GUI selects a corresponding entry for the select button in combination with other entries to indicate the actual capabilities of the printer.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 2, 2018
    Assignee: Ricoh Company, Ltd.
    Inventors: Lance Jones, Maryamossadat Nematollahi Mahani, Calin Muresan
  • Patent number: 9858018
    Abstract: An image forming system capable of executing a print job including a first job and a second job, the image forming system includes: an image forming apparatus configured to print an image on a sheet based on the first job, and thereafter, print an image on a sheet based on the second job; a sheet conveyance apparatus configured to insert the sheet that has been printed by the first job into the sheet that has been printed by the second job; an input unit configured to be used to input a time period in which execution of user operation related to the sheet conveyance apparatus is possible; and a control unit configured to print the job so as to finish the first job within the time period that has been input by the input unit.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: January 2, 2018
    Assignee: Konica Minolta, Inc.
    Inventors: Kenji Taki, Hiroyuki Arai, Fusako Ozawa, Syunji Shimokawa
  • Patent number: 9858019
    Abstract: An image forming apparatus includes a memory and a warning unit. The memory stores information indicating a past document that has been processed for printing in the past and a past print setting that is a print setting used when the past document has been processed for printing in association with each other. The warning unit outputs a warning to a user in a case where a present document that is presently processed for printing is identical or similar to the past document, and a present print setting that is a print setting set for the present document is different from the past print setting for the past document.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: January 2, 2018
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroyoshi Nakayama, Yoshihiro Chida, Masatake Kawabe, Ryohei Iwasaki
  • Patent number: 9858020
    Abstract: The invention relates to a printing system for printing a plurality of print jobs, the printing system having a receiving unit for receiving the print jobs, a controller for controlling a scheduling process and a printing process of the print jobs, a print unit for printing the print jobs, a plurality of supply holders for holding supply material for printing, and a user interface for communicating to the operator scheduled supply operator actions. Each of the scheduled supply operator actions is linked to one of the plurality of supply holders. The controller has an establishing unit for establishing a time period of unattended printing of the printing system, and a determination unit for determining scheduled supply operator actions per holder needed to be done before the time period of unattended printing starts. The user interface displays the established time period of unattended printing and the determined supply operator actions per holder.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: January 2, 2018
    Assignee: OCÉ-TECHNOLOGIES B.V.
    Inventors: Jurgen Westerhoff, Antonius M. Gerrits, Vijay A. Kalloe
  • Patent number: 9858021
    Abstract: Example apparatus and methods are disclosed for monitoring and controlling networked printing devices. A computing device can capture a printing device identifier of a printing device, where the printing device can be communicatively coupled to at least the computing device via a local network. The computing device can send a request to unlock the printing device. The computing device can receive an indication that the printing device is unlocked. After receiving the indication that the printing device is unlocked, the computing device can send a job request requesting execution of a job on the printing device, where the job request can include identification information associated with the computing device and the printing device identifier. The computing device can send job accounting information related to usage of the printing device related at least to the executed job request.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: January 2, 2018
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Oleksandr Osadchyy, Tai Yu Chen
  • Patent number: 9858022
    Abstract: In a case where a first information including an execution request of a specific function via a first type of interface is received, a function executing device may execute a change process for changing an interface for communicating with a terminal device from the first type of interface to a second type of interface in a case where a state of the function executing device is determined as a non-error state. The function executing device may not execute the change process in a case where the state of the function executing device is determined as an error state. The specific function may include a communication process for communicating object data with the terminal device. The function executing device may execute the specific function including the communication process via the second type of interface in a case where the change process is being executed.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: January 2, 2018
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takanobu Suzuki, Hirotaka Asakura, Munehisa Matsuda, Satoshi Tanaka
  • Patent number: 9858023
    Abstract: Systems, devices and methods are provided for training a user to control a gimbal in an environment. The systems and methods provide a simulation environment to control a gimbal in a virtual environment. The virtual environment closely resembles a real control environment. A controller may be used to transmit simulation commands and receive simulated data for visual display.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 2, 2018
    Assignee: SZ DJI TECHNOLOGY CO., LTD
    Inventors: Ye Tao, Zihan Chen, Zhiyuan Zhang, Weifeng Liu, Chaobin Chen
  • Patent number: 9858024
    Abstract: A candidate companion screen device is located by a primary display device as being in the same room as the primary device using sonic signaling, and in response ancillary content related to content being shown on the primary display device is provided to the companion screen device. The ancillary content may be provided from the Internet based on information in the content being presented on the primary display device by, e.g., providing a link to a website to the companion device.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: January 2, 2018
    Assignee: Sony Corporation
    Inventor: Brant Candelore
  • Patent number: 9858025
    Abstract: A method for controlling a combined display in an electronic device includes: performing connection to at least one sub-electronic device; receiving an image from the at least one sub-electronic device; and identifying relative position information of the at least one sub-electronic device with respect to the electronic device by using the image; and configuring the combined display in cooperation with the at least one sub-electronic device by using the relative position information.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-Seok Yang, Jin-Wan An, Chul-Hyung Yang, Yong-Gil Han, Sung-Jun Kim
  • Patent number: 9858026
    Abstract: A display system having a projector and a projection plate and adapted to project an image from the projector toward the projection plate to thereby display the image includes a proximity detection section adapted to detect a proximity of another display system, which has a projector and a projection plate, and is adapted to project an image from the projector toward the projection plate to thereby display the image, and a control section adapted to make the image, which is displayed on either one of the projection plate and the projection plate of the another display system, be displayed on the other of the projection plate and the projection plate of the another display system in a case in which the proximity detection section detects the proximity of the another display system.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: January 2, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Naoya Nishimura