Patents Issued in January 18, 2018
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Publication number: 20180018099Abstract: Systems and methods for performing hierarchical storage operations on electronic data in a computer network are provided. In one embodiment, the present invention may store electronic data from a network device to a network attached storage (NAS) device pursuant to certain storage criteria. The data stored on the NAS may be migrated to a secondary storage and a stub file having a pointer pointing to the secondary storage may be put at the location the data was previously stored on the NAS. The stub file may redirect the network device to the secondary storage if a read request for the data is received from the network device.Type: ApplicationFiled: May 26, 2017Publication date: January 18, 2018Inventors: Anand PRAHLAD, Jeremy Alan SCHWARTZ
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Publication number: 20180018100Abstract: In general, techniques are described for compressing an indirection table. A device comprising a processor and a memory may be configured to perform the techniques. The processor may be configured to form a plurality of physical containers, each of the plurality of physical containers representative of a plurality of physical block addresses, wherein each of the plurality of physical containers corresponds to one or more logical block address. The memory may be configured to store an indirection table that maps the logical block addresses to the plurality of physical containers. The processor may be further configured to perform run-length encoding of the plurality of physical containers to compress the indirection table.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Inventors: Stephanie Louise Aho, David Robison Hall, John Helmy Shaker Marcos
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Publication number: 20180018101Abstract: A method for write aggregation using a host memory buffer includes fetching write commands and data specified by the write commands from a host over a bus to a non-volatile memory system coupled to the host. Writing the data specified by the write commands from the non-volatile memory system over the bus to the host. The method further includes aggregating the data specified by the write commands in a host memory buffer maintained in memory of the host. The method further includes determining whether the data in the host memory buffer has aggregated to a threshold amount. The method further includes, in response to determining that the data has aggregated to the threshold amount, reading the data from the host memory buffer to the non-volatile memory system and writing the data to non-volatile memory in the non-volatile memory system.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Inventors: Shay Benisty, Tal Sharifie
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Publication number: 20180018102Abstract: Disclosed aspects include management of a set of blocks in a storage system. A set of write requests is initiated to the set of blocks. In response to the set of write requests, a set of expiration metadata for the set of blocks is established. Based on the set of expiration metadata, an expiration event is detected. In response to detecting the expiration event, an expiration operation on the set of blocks is processed.Type: ApplicationFiled: October 5, 2017Publication date: January 18, 2018Inventors: Thomas W. Bish, Nikhil Khandelwal, Gregory E. McBride, David C. Reed, Richard A. Welp
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Publication number: 20180018103Abstract: Disclosed aspects include management of a set of blocks in a storage system. A set of write requests is initiated to the set of blocks. In response to the set of write requests, a set of expiration metadata for the set of blocks is established. Based on the set of expiration metadata, an expiration event is detected. In response to detecting the expiration event, an expiration operation on the set of blocks is processed.Type: ApplicationFiled: October 5, 2017Publication date: January 18, 2018Inventors: Thomas W. Bish, Nikhil Khandelwal, Gregory E. McBride, David C. Reed, Richard A. Welp
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Publication number: 20180018104Abstract: Methods and apparatus of dynamically determining a variable reset latency time based on a data pattern of the data to be written into memory is disclosed. A memory controller determines a variable reset latency time for a plurality of memory cells depending on the bit values to be written into the plurality of memory cells in response to a write request having corresponding bit values. A write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells. The memory controller writes the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Inventors: Amin Farmahini Farahani, Benjamin Y. Cho, Nuwan Jayasena
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Publication number: 20180018105Abstract: In one form, a memory controller has a memory channel controller including a command queue and an arbiter. The command queue stores memory access requests including a sub-channel number in a virtual controller mode. The arbiter is coupled to the command queue to select memory access commands from the command queue according to predetermined criteria. In the virtual controller mode, the arbiter selects from among the memory access requests in each sub-channel independently using the predetermined criteria, and sends selected memory access requests to a corresponding one of a plurality of sub-channels. In another form, a data processing system includes a plurality of memory channels and such a memory controller coupled to the plurality of sub-channels.Type: ApplicationFiled: August 31, 2016Publication date: January 18, 2018Applicant: Advanced Micro Devices, Inc.Inventors: James R. Magro, Kedarnath Balakrishnan
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Publication number: 20180018106Abstract: A nonvolatile memory device includes a target memory area; a control unit configured to apply a program pulse one or more times to the target memory area in response to a program command, until program verification passes; and a status storage unit configured to store a program status information for the target memory area, wherein the control unit is supplied with a first operation voltage, and the status storage unit is supplied with a second operation voltage.Type: ApplicationFiled: October 28, 2016Publication date: January 18, 2018Inventor: Sok Kyu LEE
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Publication number: 20180018107Abstract: A computer-implemented method includes identifying a storage migration. The storage migration is associated with a storage area network. The storage migration has a storage migration rate associated therewith. The method includes identifying an input/output throughput. The input/output throughput is associated with the storage area network. The input/output throughput stores a throughput rate for the storage area network. The method includes identifying a service level agreement rate for the input/output throughput. The method includes identifying a non-essential workload. The non-essential workload stores a non-essential workload rate associated therewith. The non-essential workload includes that portion of said input/output throughput that is for one or more background processes. The method includes determining an analyzed rate based on the throughput rate, the service level agreement rate, and the non-essential workload rate.Type: ApplicationFiled: October 9, 2017Publication date: January 18, 2018Inventors: John V. Delaney, Anthony M. Hunt, Maeve M. O'Reilly, Daniel P. Toulan, Clea A. Zolotow
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Publication number: 20180018108Abstract: Systems, devices and methods for the assessment and mitigation of risk associated with the potential loss of data stored by an IHS (Information Handling System). The risk assessment incorporates contextual and behavioral data provided by the IHS where the data describes file operations by the IHS, the physical use of the IHS, system information that describes the platform of the IHS and hardware installed on the IHS and data backup procedures implemented by the IHS. Based on the data associated with an IHS, a scoring algorithm determines a behavioral risk of loss that reflects the use of the IHS and a contextual risk of loss that reflects user input to individual files, thus indicating the time required to recreate a file. The backup procedures implemented by the IHS are then evaluated in light of the determined risk assessment. Backup procedure recommendations that mitigate the identified risks are provided to the IHS.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Applicant: Dell Products, L.P.Inventors: Marc Hammons, Michael Gatson, Yuan-Chang Lo, Philip Seibert, Todd Swierk
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Publication number: 20180018109Abstract: Backing up virtual machine operating system data on sequential-access data storage systems is provided. A virtual machine boots into an operating system using operating system data that is provided to the virtual machine from a random access storage unit. The random access storage unit stores the operating system data as a first plurality of blocks. The operating system data is recorded in a sequential order as it is provided to the virtual machine. The operative system data is recorded in a record file. Sequential boot data is recorded on a sequential backup system based, at least in part, on the record file. The sequential boot data is a copy of the operating system data that represent the operating system as a second plurality of blocks based, at least in part, on the sequential order of the operating system data provided to the virtual machine.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Inventors: Christian Mueller, Dominic Mueller-Wicke, Eirini Petraki
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Publication number: 20180018110Abstract: A method, a computer program product, and a computer system for backing up data in a backup storage space. A computer receives a request for backing up a second data file, wherein the second data file is created from a first data file. The computer determines whether a third data file satisfies one or more of predetermined conditions for backup; wherein the third data file is generated when the second data file is created from the first data file and the third data file comprises information for creating the second data file from the first data file. In response to determining that the third data file satisfies the one or more of the predetermined conditions for backup, the computer backs up the third data file, without backing up the second data file.Type: ApplicationFiled: July 14, 2016Publication date: January 18, 2018Inventors: Tohru Hasegawa, Hiroshi Itagaki, Sosuke Matsui, Shinsuke Mitsuma, Tsuyoshi Miyamura, Noriko Yamamoto
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Publication number: 20180018111Abstract: A memory system may include: a memory device including a plurality of memory dies, each die including a plurality of memory blocks, each block including a plurality of pages; and a controller suitable for performing a command operation for the memory device and storing segments of user data and metadata for the command operation in a super memory block including memory blocks of memory dies included in a first memory die group and a second memory die group among the plurality of memory dies.Type: ApplicationFiled: February 22, 2017Publication date: January 18, 2018Inventor: Eu-Joon BYUN
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Publication number: 20180018112Abstract: A memory system may include: a memory device including a plurality of memory blocks, each of the memory blocks including a plurality of pages; and a controller suitable for: storing user data corresponding to a write command, in the memory blocks; storing map data corresponding to the stored user data, in the memory blocks; determining entropies indicating amounts of the map data updated in the memory blocks which correspond to the stored user data; and selecting source memory blocks among the memory blocks, which correspond to the entropies.Type: ApplicationFiled: February 22, 2017Publication date: January 18, 2018Inventor: Jong-Min LEE
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Publication number: 20180018113Abstract: A storage device relating to one aspect of the present invention has a storage controller and multiple memory devices. The memory devices manage capacity equivalent to the size of a memory space provided to the storage controller among regions of a non-volatile storage medium as logical capacity and manage the remaining regions as reserve capacity. When a device controller determines that a portion of the memory regions in the non-volatile storage medium is in an unusable state, the device controller notifies the storage controller of the size of the memory regions in the unusable state. On the basis of a policy set by the memory device, the storage controller determines the reduction amount of the logical capacity and the reserve capacity and notifies the memory device of the determined reduction amount of the logical capacity.Type: ApplicationFiled: May 13, 2015Publication date: January 18, 2018Inventors: Hideyuki KOSEKI, Masahiro ARAI
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Publication number: 20180018114Abstract: An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.Type: ApplicationFiled: May 18, 2017Publication date: January 18, 2018Inventors: Jing-Zhe XU, Jung-Hyun KWON, Sung-Eun LEE, Jae-Sun LEE, Sang-Gu JO
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Publication number: 20180018115Abstract: A storage apparatus includes a library apparatus comprising a plurality of removable media contained therein, and a control apparatus configured to control accesses to the plurality of removable media on a file-by-file basis. The control apparatus may include a memory, and a processor connected to the memory. The processor may be configured to cause the library apparatus to execute a migration process of data between removable media on a file-by-file basis; in response to an access request being received while the migration process is being executed, determine whether or not the access request targets an executing removable medium in which the migration process is being executed; when the access request targets the executing removable medium, control to suspend the migration process; and after the migration process is suspended, access an access-target file recorded in the removable medium targeted by the access request.Type: ApplicationFiled: June 2, 2017Publication date: January 18, 2018Applicant: FUJITSU LIMITEDInventor: Masaki Ikegame
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Publication number: 20180018116Abstract: Containerization of a block storage service. A scheduler component of a block storage service is initiated in a first container via a containerization technology. A log volume maintained by a host operating system is mounted to the first container to allow the scheduler component access to the log volume. An application programming interface (API) component of the block storage service is initiated in a second container via the containerization technology. The log volume is mounted to the second container to allow the API component access to the log volume of the host operating system. A volume component of the block storage service is initiated in a third container via the containerization technology. A device volume is mounted to the third container to allow the volume component access to the device volume of the host operating system.Type: ApplicationFiled: July 13, 2017Publication date: January 18, 2018Inventor: Ryan Hallisey
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Publication number: 20180018117Abstract: A wrist-worn device monitors movements of a user with a flexible circuit member. The flexible circuit member is fault tolerant. It may contain extra and/or redundant traces as well as the ability to store data on RAM if the flash memory fails or if some or all trace connections between the processor and flash memory fail. Data stored on the RAM may or may not contain less fidelity. Lower fidelity data may be used to alleviate issues arising if the RAM has less storage capacity than the flash memory.Type: ApplicationFiled: September 26, 2017Publication date: January 18, 2018Inventors: Jason Haensly, Mike Lapinsky, Greg McKeag, James Zipperer
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Publication number: 20180018118Abstract: In one embodiment, a method for power management includes receiving one or more state signals, each of the one or more state signals indicating whether a respective sub-block of a memory controller is idle or active, and determining whether to place the memory controller in an idle state or an active state based on the one or more state signals. The method also includes eating pulses of an input clock signal to produce a reduced-frequency clock signal if a determination is made to place the memory controller in the idle state, wherein the reduced-frequency clock signal is output to the memory controller. The method further includes passing the input clock signal to the memory controller if a determination is made to place the memory controller in the active state.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Inventors: Sharath Raghava, Jhy-ping Shaw, Vinodh Cuppu, Paul Min
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Publication number: 20180018119Abstract: A memory system according to an embodiment includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host.Type: ApplicationFiled: September 25, 2017Publication date: January 18, 2018Applicant: Toshiba Memory CorporationInventors: Yoon Tze CHIN, Norikazu YOSHIDA, Mitsuru ANAZAWA
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Publication number: 20180018120Abstract: An approach is provided in which a replicated memory system replicates a set of data between multiple replicas, whereby each of the replicas includes a sequence update number corresponding to an update state of its respective set of data. At least one of the replicas identifies a number of replicas to which it connects and, in turn, the replicas select one of replicas as a leader replica based at least on the selected leader replica's sequence update number and the number of replicas to which the selected leader connects.Type: ApplicationFiled: July 17, 2016Publication date: January 18, 2018Inventors: Vita Bortnikov, David H. Carman, Steven D. Clay, Shlomit I. Shachor, Ilya Shnayderman
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Publication number: 20180018121Abstract: A non-transitory computer-readable storage medium storing a memory management program that causes a computer to execute a process, the process including when a request indicating that data at a first address within a first memory region of a memory is an access destination is received from a process of a software during a time period from the start to end of a data movement processing, obtaining a second address within a second memory region of the memory, the data movement processing including moving data stored in the first memory region to the second memory region, and changing the access destination of the request from the first address to the second address.Type: ApplicationFiled: July 5, 2017Publication date: January 18, 2018Applicant: FUJITSU LIMITEDInventor: Kenji Kazumura
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Publication number: 20180018122Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides multiple CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller receives a memory write request comprising write data, determines a compression pattern for the write data, and generates a CI for the write data based on the compression pattern. The compressed memory controller writes the write data to the memory line, and writes the generated CI into one or more ECC bits of the memory line. In parallel, the compressed memory controller determines whether the physical address corresponds to a CI hint directory entry, and, if so, a CI hint of the CI hint directory entry corresponding to the physical address is updated based on the generated CI.Type: ApplicationFiled: September 28, 2017Publication date: January 18, 2018Inventors: Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan
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Publication number: 20180018123Abstract: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.Type: ApplicationFiled: September 16, 2016Publication date: January 18, 2018Inventors: Monish Shah, Benjamin Charles Serebrin, Albert Borchers
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Publication number: 20180018124Abstract: A data arrangement apparatus (100) includes: a file moving unit (101) moving a data file stored in a storage apparatus to a different storage apparatus; and an arrangement control unit (102) determining whether or not to associate trigger information for activating an agent application on a user terminal with a link file of the data file to be moved when the data file is moved between storage apparatuses by the file moving unit (101), based on a type of a storage apparatus of a movement destination.Type: ApplicationFiled: July 23, 2015Publication date: January 18, 2018Applicant: NEC Solution Innovators, Ltd.Inventor: Yoshihiro KUDO
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Publication number: 20180018125Abstract: An apparatus embodiment includes an integrated circuit (IC) and breach-detection circuitry. The IC includes data storage circuitry, a power grid configured to distribute power to the data storage circuitry, and a plurality of nodes distributed over at least one sensitive region of the IC. The breach-detection circuitry monitors power grid integrity at the at least one sensitive region of the IC and detects an event indicative of a breach by an external probe at a portion of the at least one sensitive region in response to floating node detection or a change in voltage at one of the plurality of nodes.Type: ApplicationFiled: July 14, 2016Publication date: January 18, 2018Inventors: Fabio Duarte De Martin, Andre Luis Vilas Boas, Guilherme Godoi
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Publication number: 20180018126Abstract: A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found.Type: ApplicationFiled: September 26, 2017Publication date: January 18, 2018Inventor: Yan LI
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Publication number: 20180018127Abstract: A method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device determines a respective operational state of each of one or more processes of the embedded-system device. The embedded-system device stores the respective operational state of each of the one or more processes at a memory location in a respective memory area for the each process in a memory of the embedded-system device. The embedded-system device stores the memory locations associated with the one or more processes in a register in the memory. The embedded-system device obtains, from the register, a memory location of at least one process of the one or more processes. The embedded-system device obtains, based on the memory location of the at least one process, the stored operational state of the at least one process from the respective memory area for the at least one process.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Inventors: Satheesh Thomas, J. Vinodhini, Venkatesan Balakrishnan, Baskar Parthiban
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Publication number: 20180018128Abstract: Provided herein is a memory device including a memory cell array, a peripheral circuit configured to perform a first operation for the memory cell array, and a control circuit configured to generate an operation status code and output the operation status code. The first operation includes a plurality of second operations that are successively performed. The operation status code indicates, among the plurality of second operations, a current operation that is being performed by the peripheral circuit.Type: ApplicationFiled: March 28, 2017Publication date: January 18, 2018Inventor: Tai Kyu KANG
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Publication number: 20180018129Abstract: A method for a storage monitoring system including a storage device, a manager, and agents, wherein said manager: stores information about a first range of components of a first type that are among types of components included in the storage device, and that are to be monitored by a first agent of the agents, said stored information being associated with information about the first agent; notifies the first agent of the information about the first range of components to be monitored; stores information about a second range of components of the first type that are among the types of components, and that are to be monitored by a second agent of the agents, said stored information being associated with information about the second agent; and notifies the second agent of the information about the second range of components to be monitored.Type: ApplicationFiled: July 28, 2015Publication date: January 18, 2018Inventors: Akira NIKAIDO, Takaki KURODA
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Publication number: 20180018130Abstract: A disclosed method processes a data feed including multiple streams. The method includes processing n frames of the multiple streams in parallel through n processing pipelines, n being an integer greater than or equal to 2. The n frames include a first frame belonging to a first stream and a second frame belonging to a second stream. The first stream is different than the second stream. The n processing pipelines are coupled to n-by-n value buffers per stream per recorded value for the stream, and at least one status buffer per stream. The n processing pipelines are each assigned a distinct row of read-authorized port access to the n-by-n value buffers and a distinct column of write-authorized port access to the n-by-n value buffers.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Applicant: Spirent Communications, Inc.Inventors: Jocelyn Kunimitsu, Craig Fujikami
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Publication number: 20180018131Abstract: A memory controller receives first and second write transactions from a processor and stores write data in a memory. The memory controller includes an address comparison circuit, a buffer, a level control circuit, a command generator, and a control circuit. The address comparison circuit compares second and third addresses and outputs first and second write data when the second and third addresses are consecutive. The buffer stores the first and second write data and outputs buffered data based on a control signal. The level control circuit compares a size of the buffered data with a threshold size and the size of the buffer. The command generator causes a write transaction to be executed based on the comparison results, rather than having the processor initiate the transaction, which reduces the load on the processor, and the buffered write data is stored in the memory.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Inventors: HARSIMRAN SINGH, NEERAJ CHANDAK, SNEHLATA GUTGUTIA, VIVEK SINGH
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Publication number: 20180018132Abstract: A memory device includes a memory array including a plurality of memory cells that store data, a sense circuit coupled to the memory array for reading data stored in the memory array, a data register for storing data to be written into the memory array, a data processor, and a control unit. The data processor is configured to receive input data units to be written into the memory array, and process the input data units based on array data units stored in the memory array to generate processed data units. The control unit is configured to write the processed data units into the memory array.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Inventor: Johnny CHAN
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Publication number: 20180018133Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.Type: ApplicationFiled: September 22, 2016Publication date: January 18, 2018Applicant: Advanced Micro Devices, Inc.Inventor: Kedarnath Balakrishnan
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Publication number: 20180018134Abstract: Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.Type: ApplicationFiled: March 23, 2017Publication date: January 18, 2018Inventor: Jae-Yong Kang
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Publication number: 20180018135Abstract: The present disclosure discloses a read/write path determining method and apparatus. The method is used by a physical host. The method includes: obtaining, by the host, a first read/write request of the virtual machine, where the first read/write request includes a first virtual address, searching for the first virtual address in an address translation information set, and determining to process the first read/write request by using the block device or the virtual block device according to the address translation information set and the first virtual address. According to the method and apparatus, an appropriate read/write path is determined according to a read/write request and an address translation information set, so that both storage performance and a storage function can be considered.Type: ApplicationFiled: July 28, 2017Publication date: January 18, 2018Inventor: Canquan Shen
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Publication number: 20180018136Abstract: While a specific application is running, a printer driver enables printing other data that is not data from the specific application. A dedicated driver (printer driver) that runs on a POS terminal occupies a communication port when receipt data is supplied from a POS application. The dedicated driver also sends print data generated based on the receipt data through the communication port to a POS printer. After continuing for a previously set time, the dedicated driver releases the communication port.Type: ApplicationFiled: January 28, 2016Publication date: January 18, 2018Applicant: SEIKO EPSON CORPORATIONInventors: Atsushi SAKAI, Masatoshi NAKAZAWA
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Publication number: 20180018137Abstract: A processing apparatus includes a receiving section that receives data transmitted by a sender, an output section that outputs the data received by the receiving section, and a charge section that charges the sender if the output section outputs the data within a predetermined period after the time at which the data is transmitted.Type: ApplicationFiled: May 23, 2017Publication date: January 18, 2018Applicant: FUJI XEROX CO., LTD.Inventors: Koichi YOSHIMURA, Shigeru YONEDA
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Publication number: 20180018138Abstract: Each of a plurality of servers may transmit first server identification information identifying the first server to the relay device. An terminal may transmit first access target information to a relay device. The relay device may store the first server identification information in a first memory of the relay device, in association with the first access target information. The terminal may transmit second access target information to a second server. The second server may transmit the received second access target information and second server identification information to the relay device. The relay device may cause the second server to access the image forming device identified by the second access target information.Type: ApplicationFiled: September 21, 2017Publication date: January 18, 2018Inventor: Takafumi MORI
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Publication number: 20180018139Abstract: A server is a projection image control device that can be connected to one or more projectors installed in an aircraft, and comprises a memory and a processor. The memory at least temporarily stores operation information about the aircraft. The projection image control processor determines the display direction of a projection image on the basis of operation information, produces a command to cause the one or more projectors to display a projection image in the determined display direction, and outputs this command.Type: ApplicationFiled: January 11, 2017Publication date: January 18, 2018Inventors: Kou WATANABE, Masahiko YAMAMOTO
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Publication number: 20180018140Abstract: A display control device includes a recognition unit and a controller. The recognition unit recognizes that a first area that has a specific size and in which a specific image is displayed is arranged on a display screen of a first display apparatus. After the recognition unit recognizes that the first area is arranged, the controller performs control to arrange, on a display screen of a second display apparatus, a second area that has the specific size and in which the specific image is displayed.Type: ApplicationFiled: May 11, 2017Publication date: January 18, 2018Applicant: FUJI XEROX CO., LTD.Inventors: Takumi KOBAYASHI, Kohshiro INOMATA, Masayuki YAMAGUCHI, Tetsuo FUKASAWA
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Publication number: 20180018141Abstract: The present disclosure relates to methods and systems for generating augmented reality. The method may include capturing a first image in a viewing range of a first augmented reality device in real time via a camera of the first augmented reality device, and synchronizing the first image to a second augmented reality device, the first augmented reality device being a device for providing an augmented reality image to a first user in the first display, and the second augmented reality device being a device for providing an augmented reality image to a second user in a second display. The method further includes receiving a second image from the second augmented reality device, the second image being an image returned in real time by the second augmented reality device after augmenting the first image by the second augmented reality device.Type: ApplicationFiled: September 26, 2017Publication date: January 18, 2018Applicant: Tencent Technology (Shenzhen) Company LimitedInventor: Xiaoting Wang
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Publication number: 20180018142Abstract: An electronic device is provided which includes a housing, a connecting member having a first conductive pattern formed on an inner surface thereof, and a processor configured to control a function of the electronic device according to a rotation of a plug corresponding to an alignment between the first conductive pattern and a second conductive pattern formed on the plug when the plug is inserted into a hole of the connecting member.Type: ApplicationFiled: January 30, 2017Publication date: January 18, 2018Inventors: Shin-Ho KIM, Hwan-Woo SHIM
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Publication number: 20180018143Abstract: An audio device with a music listening function and an ambient listening function is provided, which allows selective implementation of the music listening function and the ambient listening function by simplified user operation. The audio device includes: a communication part configured to perform communication with an external electronic communication device; a microphone part configured to pick up ambient sound; a speaker part configured to emit music or ambient sound; and a controller configured to perform the ambient listening function to pick up ambient sound from the microphone part and emit the ambient sound to the speaker, and perform the music listening function to play an audio file from the communication part or a stored audio file and emit the audio file through the speaker.Type: ApplicationFiled: July 11, 2017Publication date: January 18, 2018Inventors: Choong Sheek Hong, Taek Jin Han, Dong Sung Kim, Sang Hyun Lee
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Publication number: 20180018144Abstract: An environmental context of a user may be taken into account to enhance the user's communication throughput. An “environmental context” can include spatial surroundings of a user, device, and/or sensor of the device and more broadly to denote the context of the user in a multiplicity of environments such as, for example, the surroundings of a user, a digital environment such as the user or other individuals' interactions with or made near a device, etc. The techniques can include obtaining contextual data to provide context-predicted suggestions of words and/or phrases that a user can select to be output on the user's behalf, In some examples, the techniques can also use contextual data to weight, sort, rank, and/or filter word and/or phrase suggestions.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Inventors: Meredith Morris, Shaun K. Kane
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Publication number: 20180018145Abstract: Groups of metrics to form objective functions may be generated by obtaining a judgment that represents whether a first subject is comparable to a second subject, obtaining a plurality of evaluation values for each of the first subject and the second subject, each evaluation value corresponding to a metric among a plurality of metrics, comparing, for each metric, a corresponding evaluation value of a first subject to a corresponding evaluation value of the second subject, and generating one or more groups based on a result of the comparison and the judgment, each group of the one or more groups including at least one metric of the plurality of metrics, wherein metrics in each group are determined to be comparable with respect to evaluating subjects.Type: ApplicationFiled: July 14, 2016Publication date: January 18, 2018Inventor: Takayuki Yoshizumi
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Publication number: 20180018146Abstract: Control circuitry coupled to a multiply unit which includes a plurality of stage, each of which may be configured to perform a corresponding arithmetic function, may be configured to retrieve a given entry from a lookup table dependent upon a first portion of a binary representation of an input operand. An error value of an error function evaluated dependent upon a lookup value in a given entry of the plurality of entries is included in a predetermined error range. The control circuitry may be further configured to determine an initial approximation of a result of an iterative arithmetic operation using the first entry and initiate the iterative arithmetic operation using the initial approximation and the input operand.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Inventors: Josephus Ebergen, Dmitry Nadezhin, Christopher Olson
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Publication number: 20180018147Abstract: A random number expanding device (100) includes an expanding unit (120) that expands a random number r(M) to an N bits random number s(N) using a logical operation that is obtained by multiplication of one matrix of a check matrix with a size of M×N and a generator matrix with a size of M×N which are determined from an (N, N?M, D) linear code for error correction by a vector in a case in which the random number r(M) is the vector with M components, the multiplication being performed through addition based on an exclusive OR. Since the random number expanding device (100) includes the expanding unit (120), it is possible to reduce the bit numbers of random numbers to be used, and counter an irradiation attack with multiple laser beams.Type: ApplicationFiled: January 15, 2015Publication date: January 18, 2018Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Takeshi SUGAWARA
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Publication number: 20180018148Abstract: After the claims, please insert as new page 22 of the enclosed published International application, the below Abstract which originally appeared on the cover page of the published International application: An application development editor displays in a graphical user interface a list or other arrangement of variations based on or applying to conditions in the application, each variation being associated with one or more changes in properties or events in the application. The editor enables a user to select a specific variation and then displays the user interface implications or consequences of that selection. Selecting a specific variation is programmatically equivalent to a specific conditional logic branch or ‘if . . . then ’ code sequence. The invention enable someone with no, or very limited, code writing skills, such as a designer, to be able to produce an application with fully functioning, correct and potentially complex conditional logic.Type: ApplicationFiled: October 20, 2015Publication date: January 18, 2018Inventor: David BREBNER