Abstract: On the basis of a bitstream (P), an n-channel audio signal (X) is reconstructed by deriving an m-channel core signal (Y) and multichannel coding parameters (?) from the bitstream, where 1?m<n. Also derived from the bitstream are pre-processing dynamic range control, DRC, parameters (DRC2) quantifying an encoder-side dynamic range limiting of the core signal. The n-channel audio signal is obtained by parametric synthesis in accordance with the multichannel coding parameters and while cancelling any encoder-side dynamic range limiting based on the pre-processing DRC parameters. In particular embodiments, the reconstruction further includes use of compensated post-processing DRC parameters quantifying a potential decoder-side dynamic range compression. Cancellation of an encoder-side range limitation and range compression are preferably performed by different decoder-side components. Cancellation and compression may be coordinated by a DRC pre-processor.

Abstract: Provided are methods and systems for acoustic keystroke transient cancellation/suppression for user communication devices using a semi-blind adaptive filter model. The methods and systems are designed to overcome existing problems in transient noise suppression by taking into account some less-defective signal as side information on the transients and also accounting for acoustic signal propagation, including the reverberation effects, using dynamic models. The methods and systems take advantage of a synchronous reference microphone embedded in the keyboard of the user device, and utilize an adaptive filtering approach exploiting the knowledge of this keybed microphone signal.

Abstract: A method transforms a noisy audio signal to an enhanced audio signal, by first acquiring the noisy audio signal from an environment. The noisy audio signal is processed by an enhancement network having network parameters to jointly produce a magnitude mask and a phase estimate. Then, the magnitude mask and the phase estimate are used to obtain the enhanced audio signal.

Abstract: A system and method that enhances speech through reinforcement includes capturing an audio signal generated by the audio sources by one or more microphones; decomposing the audio signals into a plurality of virtual audio sources where the number of audio channels delivered by the audio sources is equal to the number of the plurality of virtual audio sources; estimating the echo paths from each of the plurality of virtual audio sources to the one or more microphones; and processing the captured audio signal in response to the estimated echo paths by subtracting the echo contributions of each of the virtual sources to the one or more microphones.

Abstract: An audio signal processing device includes: a short-time fast Fourier transform unit that generates a signal in a frequency domain obtained by performing a short-time fast Fourier transform on an input audio signal; a steady sound determining unit that determines whether a waveform of a peak portion included in a waveform of the signal in a frequency domain is a steady sound; a filter coefficient calculation unit that dynamically calculates a filter coefficient on the basis of a result of determination made by the steady sound determining unit; a comb filter that operates according to the filter coefficient calculated by the filter coefficient calculation unit so as to filter a signal in a frequency domain; and an inverse Fourier transform unit that transforms an output of the comb filter into a signal in a time domain and outputs the signal in a time domain.

Abstract: An apparatus for enhancing a speech signal includes a spectral analysis circuit that generates time-frequency spectra of signals from a microphone array, a signal separation filter, and a hardware processor. The hardware processor identifies a key phrase in the signals and aligns a template of the key phrase to time-frequency spectra of a microphone in the array. A mask is generated from the aligned template and applied to the time-frequency spectra. The masked spectra are used to determine acoustic parameters that, in turn, are used to generate coefficients for configuring the source separation filter which is then used to process the spectra to generate an enhanced speech signal. The apparatus maybe used as a front end for a speech recognition engine, for example.

Abstract: A method and system for filtering a multi-channel audio signal having a speech channel and at least one non-speech channel, to improve intelligibility of speech determined by the signal. In typical embodiments, the method includes steps of determining at least one attenuation control value indicative of a measure of similarity between speech-related content determined by the speech channel and speech-related content determined by the non-speech channel, and attenuating the non-speech channel in response to the at least one attenuation control value. Typically, the attenuating step includes scaling of a raw attenuation control signal (e.g., a ducking gain control signal) for the non-speech channel in response to the at least one attenuation control value. Some embodiments are a general or special purpose processor programmed with software or firmware and/or otherwise configured to perform filtering in accordance the invention.

Abstract: Systems and methods for escalation detection using sentiment analysis are disclosed. A computer-implemented method of the invention includes: determining, by a computer device, the occurrence of an interaction event between a first party and a second party within a recording including audio data; analyzing, by the computer device, the audio data for a change in tone over time; analyzing, by the computer device, the audio data for the presence of any negative tones; determining, by the computer device, whether the change in tone, the presence of any negative tones, or a combination of the change in tone and the presence of any negative tones, indicates an escalation during the interaction event to generate escalation data; and saving, by the computer device, the escalation data.

Abstract: An apparatus for microwave-assisted magnetic recording includes a magnetic write head operable to write data to a magnetic storage medium. The apparatus includes a spin-torque microwave oscillator coupled to the magnetic write head and operable to provide microwave radiation to the magnetic storage medium. The apparatus includes a driver circuit in communication with the magnetic write head. The driver circuit is operable to dynamically modulate bias current provided to the spin-torque microwave oscillator in sympathy with data being written to the magnetic storage medium by the magnetic write head.

Abstract: A method and system provides a near-field transducer (NFT) for a heat assisted magnetic recording (HAMR) transducer. The method and system include forming the disk of the NFT and forming the pin of the NFT. The disk is formed from a first material. The pin is formed from a second material different from the first material. The pin contacts the disk. At least a portion of the pin is between the disk and an air-bearing surface (ABS) location.

Abstract: A process for lapping a row of head sliders involves fixing the row to a lapping tool fixture, actuating each of multiple force pins to set each head slider for lapping to a respective target wedge angle, and simultaneously lapping accordingly. Each target wedge angle may be achieved by applying a respective torque to a compliant elastomer between each force pin and corresponding head slider, to transfer a pressure gradient corresponding to the torque to the corresponding head slider. Such torques may be applied through at least two wedge angle flexures interconnecting a rotatable box structure and a fixed back wall of a lapping tool, wherein the flexures virtually intersect at and define an axis of rotation about which the torques are applied. The process may further involve actuating each force pin to set each head slider for lapping to a respective reader target stripe height, and simultaneously lapping accordingly.

Abstract: A head suspension assembly for a disk drive includes a load beam and a laminated flexure that comprises a stainless steel layer, a copper trace layer, and a dielectric layer between the stainless steel layer and the copper trace layer. The laminated flexure includes a flexure tail that extends away from the load beam to a flexure tail terminal region. The copper trace layer includes a plurality of flexure bond pads in the flexure tail terminal region. The stainless steel layer includes a plurality of backing islands in the flexure tail terminal region. Each of the plurality of backing islands is aligned with a corresponding one of the plurality of flexure bond pads. A noble metal layer is disposed on the plurality of backing islands.

Abstract: A method for magnetic data recording that calibrates for magnetic thermal protrusion of elements of a magnetic data recording system. The method involves performing a series of burst mode magnetic data writings using a magnetic recording head that includes a write element, a thermal fly height control element and a near field transducer. The burst mode writings are performed at various levels of thermal fly height control power. This can be use to determine the relationship between signal amplitude and thermal fly height control power with thermal protrusion being affected only by the thermal fly height control element and not from thermal heating of the near field transducer or write element. Then, thermal fly height control can be adjusted to achieve the desired signal amplitude for recording with the near field transducer and write element operating at a thermal steady state.

Abstract: The present application provides a transducer head comprising a laser source configured to heat a target storage medium surface, and a thermal sensor configured to detect a defect on the target storage medium surface. The present application also provides a method comprising heating a target storage medium surface with an energy source configured in a transducer head to irradiate the target storage medium surface, and detecting a defect on the target storage medium surface using a thermal sensor configured in the transducer head. Other implementations are also described and recited herein.

Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of tracks. A first codeword is generated comprising first redundancy, and first position information of the head relative to a first track is saved while writing the first codeword to the first track. A second codeword is generated comprising second redundancy, and second position information of the head relative to a second track is saved while writing the second codeword to the second track. Extended redundancy is generated for the first codeword based on the first and second position information, and the first codeword is recovered from the first track based on the extended redundancy generated for the first codeword.

Abstract: The invention generally relates to a hard disk drive with a disk, a read/write head, a z-axis actuator, and a controller. A surface of the disk and/or the head can be bare and thus devoid of any overcoat or lubricant layer, or alternatively the disk surface can have one or more layers with a combined thickness of less than 4 nanometers and the head can have a layer with a thickness of less than 2 nanometers. The hard disk drive can be enclosed, and its enclosed space can be a low pressure environment such as a near-zero or a zero pressure environment.

Abstract: Described are computer-based systems, computer-implemented methods, and non-transitory computer-readable media for editing video in real-time, or substantially in real-time, using gestures to apply transitions and effects to a plurality of simultaneously played video sources to create an edited video output.

Abstract: Providing a method for creating and displaying portions of videos called video previews. The video previews may be associated with audio, such that when the video previews are activated, the audio may play with the video preview. When multiple video previews are organized to play as a playable group or composite of video previews, a corresponding composite audio file can play in response to an activation of the composite.

Abstract: A system comprising a video source, one or more audio sources and a computing device. The video source may be configured to generate a plurality of video streams that capture a view of an environment. The one or more audio sources may be configured to capture audio data of the environment. The computing device may comprise one or more processors configured to (i) perform a stitching operation on the plurality of video streams to generate a video signal representative of an immersive field of view of the environment, (ii) generate a sound field based on the audio data, (iii) identify an orientation for the sound field with respect to the video signal, and (iv) determine a rotation of the sound field based on the orientation. The rotation of the sound field aligns the sound field to the video signal.

Abstract: An imaging device includes an imaging element that acquires a first image based on signal charge generated during a first accumulation time, and a second image based on signal charge generated during a second accumulation time relatively longer than the first accumulation time and synchronized with the first image during a synchronization period including the first accumulation time, and a moving image file generating unit that generates a moving image file including a first moving image based on the first image, a second moving image based on the second image, and synchronization information for synchronizing the first moving image and the second moving image frame by frame.

Abstract: An assembled record player includes: a box having a cover and a base, and the cover being covered onto the base, and a accommodating space being included between the cover and the base; a record player contained in the accommodating space; at least one loudspeaker and contained in the accommodating space; and a circuit board contained in the accommodating space. The cover and the base are separated, and an accommodating hole is formed on the cover, and the record player is installed and fixed to the accommodating hole, and the loudspeaker and the circuit board are fixed to the base, and the circuit board is electrically connected to the record player and the loudspeaker, and the cover of the record player is covered onto the base to form the record player. Therefore, users can experience the fun of assembling the record player.

Abstract: The present disclosure generally relates to a connector structure that prevents crosstalk in devices such as electronic and data storage devices. The connector structure is disposed in a different plane than the signal lines, but is connected to ground lines that are disposed in the same plane as the signal lines. The connector structure has a beam portion for each ground line. Additionally, there is a backbone portion that connects all of the beam portions. The beam portions are coupled to the ground lines by a ground bar. The ground bar can have a width that is equal to the width of the ground line. Additionally, the connection point between the ground line and the ground bar can be sloped, and the ground line and ground bar can be parallel to each other at the connection point. The connector structure prevents crosstalk between the signal lines.

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

Abstract: A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion.

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract: Computer systems and methods for memory management in a computer system are provided. A computer system includes an integrated circuit, where the integrated circuit includes a processing unit and a memory controller coupled to the processing unit. The memory controller includes a first interface and a second interface configured to couple the memory controller with a first memory and a second memory, respectively. The second interface is separate from the first interface. The computer system includes the first memory of a first memory type coupled to the memory controller through the first interface. The computer system further includes the second memory coupled to the memory controller through the second interface, where the second memory is of a second memory type that has a different power consumption characteristic than that of the first memory type.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Technologies for clearing a page of memory include a memory device configured write a value to a block of memory cells in response to an activation signal. The memory device includes a row decoder responsive to a memory address to select a row of memory cells and a column decoder responsive to the activation signal to select one or more columns of memory cells. Additionally, a write driver of the memory device is configured to write a value to global input/output lines, which are connected to the selected memory cells in response to the activation signal and regardless of data received on a data input of the write driver.

Abstract: A magnetic memory according to an embodiment includes: a conductive layer including a first and second terminals; a plurality of magnetoresistive elements separately disposed on the conductive layer between the first and second terminals, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and a circuit configured to apply a first potential to the reference layers of the magnetoresistive elements and to flow a first write current between the first and second terminals, and configured to apply a second potential to the reference layer or the reference layers of one or more of the magnetoresistive elements to which data is to be written, and to flow a second write current between the first and second terminals in an opposite direction to the first write current.

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

Abstract: A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of data. The method further includes delaying the plurality of information bits of each group of the at least two groups during a data transfer operation to minimize the skew between the at least two groups of information bits.

Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

Abstract: A memory cell includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Abstract: An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.

Abstract: Disclosed is a wordline driver with an integrated voltage level shift function. This wordline driver receives a decoder output signal from a wordline address decoder operating at first voltage level. Based on the decoder output signal, it generates and outputs a wordline driving signal, which selectively activates or deactivates a selected wordline. To ensure that the selected wordline, when activated, is at a second voltage level that is higher than the first, the wordline driver uses a combination of clock signals received from multiple timing control blocks operating at the first voltage level and multiple logic gates operating the second voltage level. To ensure that this wordline driving signal remains low during power up when fluctuations occur due to the different voltage levels and, specifically, to ensure that the wordline driving signal only switches to high when it will be stable, the wordline driver can include a reset control block.

Abstract: A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.

Abstract: A method is for operating a resistive memory system including a resistive memory device implemented as multi-level memory cells. The method includes setting levels of reference voltages used to determine resistance states of the multi-level memory cells, and reading data of the multi-level memory cells based on the reference voltages. A difference between the reference voltages used to determine a relatively high resistance state is greater than a difference between the reference voltages used to determine a relatively low resistance state.

Abstract: A resistive memory apparatus may include a memory region including a plurality of resistive memory cells arranged in a plurality of memory cell pairs. The resistive memory apparatus may include a voltage generating circuit configured to generate a read voltage code based on a switching state of at least one memory cell pair. The resistive memory apparatus may include a voltage providing unit configured to generate a read voltage corresponding to the read voltage code.

Abstract: Memories having a plurality of resistive storage elements in a shared resistance variable material, a plurality of select devices coupled to the plurality of resistive storage elements in a one-to-one relationship and sense circuitry coupled to the plurality of select devices.

Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

Abstract: Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).

Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.

Abstract: A sensing amplifier includes a first bit line driver, a second bit line driver and a third bit line driver. The first bit line driver sets a first bit line for a fast-pass-write (FPW) operation. The second bit line driver sets a second bit line for a first operation rather than the FPW operation. The third bit line driver sets a third bit line for a second operation rather than the FPW operation. The first bit line is arranged between the second bit line and the third bit line, and the second bit line driver and the third bit line driver respectively adjust voltage statuses of the second bit line and the third bit line to rise a voltage level of the first bit line by a compensated level.

Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.