Patents Issued in February 8, 2018
  • Publication number: 20180039547
    Abstract: Techniques to back up data are disclosed. In various embodiments, a shadow copy of a source volume is created. An excluded file is deleted from the shadow copy. One or more blocks modified in the shadow copy in connection with deleting the excluded file from the shadow copy are tracked.
    Type: Application
    Filed: October 20, 2017
    Publication date: February 8, 2018
    Inventors: Kiran Kumar Madiraju Varadaraju, Neelabh Mam
  • Publication number: 20180039548
    Abstract: Determining a time for on-demand snapshotting of a virtual machine in a node prior to a failure point in a system comprising a plurality of nodes. Failure data is collected from a set of failed nodes of the plurality of nodes in a system. A failure pattern of the node is identified based on the failure data and monitoring the plurality of nodes for the failure pattern to determine that a first node of the plurality of nodes is exhibiting the failure pattern. Responsive to the determination that the first node is exhibiting the failure pattern, capturing a snapshot of a virtual machine corresponding to the first node.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: Jay S. Bryant, James E. Carey, Zachary A. Hill, Kendall J. Nelson, Lucas A. Palm
  • Publication number: 20180039549
    Abstract: The present subject matter relates to storage systems. In an example method, a write request is received from a computing device in a data backup mode. Data associated with the write request is written to a primary storage drive of a storage system when the write request is for an unallocated block of the primary storage drive. The data associated with the write request is written to a secondary storage drive of the storage system when the write request is for an allocated block of the primary storage drive.
    Type: Application
    Filed: April 30, 2015
    Publication date: February 8, 2018
    Inventors: RENY PAUL, KARTHICK THARAKRAJ
  • Publication number: 20180039550
    Abstract: A resource allocation system begins with an ordered plan for matching requests to resources that is sorted by priority. The resource allocation system optimizes the plan by determining those requests in the plan that will fail if performed. The resource allocation system removes or defers the determined requests. In addition, when a request that is performed fails, the resource allocation system may remove requests that require similar resources from the plan. Moreover, when resources are released by a request, the resource allocation system may place the resources in a temporary holding area until the resource allocation returns to the top of the ordered plan so that lower priority requests that are lower in the plan do not take resources that are needed by waiting higher priority requests higher in the plan.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Inventors: Parag Gokhale, Rajiv Kottomtharayil, Amey Vijaykumar Karandikar, Yu Wang
  • Publication number: 20180039551
    Abstract: Cloud-based storage services are provided for storing and/or sharing content across multiple devices, where the content is periodically synchronized between the devices and the storage service. Conventionally, if locally stored content is deleted from a device, the delete would be propagated to the storage service causing the content to not only be deleted from the storage service but from any other devices where the content was locally stored and synchronized with the storage service. Embodiments are directed to retainment of locally deleted content at the storage service to prevent accidental or nefarious deletions of locally stored content on a device from further causing the content to be deleted universally from the storage service and/or multiple other devices. For example, the storage service may be configured to receive content stored locally on the device, detect a deletion of the content on the device, and retain the content at the storage service.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: John D. Rodrigues, Steven Bailey, Adam Czeisler
  • Publication number: 20180039552
    Abstract: A server board includes first and second devices. A first service processor of the first device operates as a master baseboard management controller of the server board, and monitors a communication channel for alive messages from a plurality service processors. A second service processor operates as a secondary baseboard management controller, and sets a second timer to a first value. In response to a determination that the second timer has expired based on a first value: the second service processor to start a switchover process, and to set the second timer to a second value based on an alive message period. In response to a primary alive message not being received from the first service processor prior to the second timer expiring based on the second value, the second service processor to reset first service processor and to operate as the master baseboard management controller.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Avishay Moskowiz, Amitay Beler, Ira Kalman
  • Publication number: 20180039553
    Abstract: A storage control device includes a first memory, a second memory, and a processor. The first memory stores therein a first startup program for starting up the storage control device. The second memory stores therein a second startup program for starting up the storage control device. The processor performs a startup process of starting up the storage control device by executing the first startup program stored in the first memory. The processor performs diagnosis for the first memory during the startup process. The processor restores, in a case where an abnormality is detected in a first portion of a first area of the first memory, first data stored in the first portion by overwriting the first data with data of a part of the second startup program stored in the second memory. The first area is a storage area in which the first startup program is stored.
    Type: Application
    Filed: July 20, 2017
    Publication date: February 8, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Kyohei KITAGAWA
  • Publication number: 20180039554
    Abstract: Embodiments include a method of a test system that comprises a host device and at least one storage device having multiple ports connected to the host device through a multi-port connection, the method comprising: issuing, by a test program at the host device, a first command; generating, by a device driver at the host device, a plurality of second commands in response to the first command; and simultaneously transferring, by the host device, the second commands to each of the at least one storage device.
    Type: Application
    Filed: April 6, 2017
    Publication date: February 8, 2018
    Inventor: KyuYeul WANG
  • Publication number: 20180039555
    Abstract: Systems and methods for performing unsupervised baselining and anomaly detection using time-series data are described. In one or more embodiments, a baselining and anomaly detection system receives a set of time-series data. Based on the set of time-series, the system generates a first interval that represents a first distribution of sample values associated with the first seasonal pattern and a second interval that represents a second distribution of sample values associated with the second seasonal pattern. The system then monitors a time-series signals using the first interval during a first time period and the second interval during a second time period. In response to detecting an anomaly in the first seasonal pattern or the second seasonal pattern, the system generates an alert.
    Type: Application
    Filed: May 31, 2017
    Publication date: February 8, 2018
    Applicant: Oracle International Corporation
    Inventors: Sampanna Shahaji Salunke, Dustin Garvey, Uri Shaft, Maria Kaval
  • Publication number: 20180039556
    Abstract: The present system for modeling intelligent sensor selection and placement takes signal and sensor information and calculates a statistical inference. As signal data passes through a series of processors, it is transformed by functions to account for signal emission, sensor reception, environmental factors, and noise. This produces a simulation of what the emitted signal would appear to be at a given sensor. The system may be used to select the most effective sensors for a given area or to determine the best sensor coverage for a given area.
    Type: Application
    Filed: September 30, 2017
    Publication date: February 8, 2018
    Inventor: David Keith Wilson
  • Publication number: 20180039557
    Abstract: A method of performing a cooperative data processing, said method comprising performing a plurality of processes in each of a plurality of control modules capable of communicating with each other to perform the cooperative data processing, the plurality of processes includes a required application process of the cooperative data processing.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Inventor: Hisashi HATA
  • Publication number: 20180039558
    Abstract: The disclosure includes a system, method and tangible memory for providing a monitoring system for a fleet of vehicles. The method may include a monitoring server receiving a set of trace data associated with a vehicle application. The fleet of vehicles may include a plurality of vehicles that are communicatively coupled to the monitoring server via a wireless network. Each of the vehicles may include a copy of the vehicle application. The set of trace data may describe operations that are executed responsive to an onboard computer executing the copy of the vehicle application. The method may include inputting the set of trace data and model data into an RV-Predict application. The model data may describe a formal model of the vehicle application. The method may include executing the RV-Predict application with a processor to generate predictive data describing a predictive analysis of whether the vehicle application includes an error.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Shinichi Shiraishi, Grigore Rosu, Philip Daian, Akihito Iwai, Yuki Mae
  • Publication number: 20180039559
    Abstract: Some embodiments are directed to a method comprising automatically obtaining one or more reference data items representative of one or more graphical user interface (GUI) objects from a GUI of a system under test by, for each of the one or more reference data items: identifying one or more correlations between two or more pixels of the GUI of the system under test to determine a group of pixels corresponding to a GUI object; determining image boundaries of the GUI object based on at least one of the determined group of pixels and any identified correlations; generating a reference data item representative of the GUI object identified by the determined image boundaries; and storing the reference data item in a database. The method also comprises receiving a user input representative of a selection of a desired reference data item from the database and updating a test description for an automated computer test with the selected reference data item.
    Type: Application
    Filed: October 4, 2017
    Publication date: February 8, 2018
    Applicant: TestPlant Europe Limited
    Inventor: Jonathan GILLASPIE
  • Publication number: 20180039560
    Abstract: Dynamically identifying performance anti-patterns in a software system is based on a set of documented symptoms that are evaluated in real-time. The evaluation is based on the observed system behavior and its comparison against the documented symptoms of different types of performance issues.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Applicant: International Business Machines Corporation
    Inventors: Erik R. ALTMAN, Hitham Ahmed ASSEM ALY SALAMA, Nicholas M. Mitchell, Patrick Joseph O'SULLIVAN, Andres Omar PORTILLO DOMINGUEZ, Peter F. SWEENEY
  • Publication number: 20180039561
    Abstract: A computer-implemented method includes identifying a primary code segment, determining a confidence score associated with said primary code segment, and determining whether the confidence score exceeds a confidence threshold. The computer-implemented method further includes responsive to the confidence score exceeding the confidence threshold, determining a logger code segment associated with the primary code segment. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: Tomoka Mochizuki, Tomonori Sugiura, Lianzi Wen
  • Publication number: 20180039562
    Abstract: A computer-implemented method includes identifying a primary code segment, determining a confidence score associated with said primary code segment, and determining whether the confidence score exceeds a confidence threshold. The computer-implemented method further includes responsive to the confidence score exceeding the confidence threshold, determining a logger code segment associated with the primary code segment. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: September 19, 2017
    Publication date: February 8, 2018
    Inventors: Tomoka Mochizuki, Tomonori Sugiura, Lianzi Wen
  • Publication number: 20180039563
    Abstract: A system for security and software development intelligence is provided. The system includes an ontology infrastructure, which includes a web ontology language, an ontology rule system, and an ontology inference engine. The system also includes an adjustable ratings calculation module for calculating a rating of a plurality of coding errors located in the web ontology language. Moreover, the system includes a data fidelity and reduction module for reducing the complexity of the web ontology language.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Applicant: proServices Corp.
    Inventor: Brian Gill-Price
  • Publication number: 20180039564
    Abstract: A system, a method, and a computer program product for visualizing an outcome of dependency checks and resolution of errors in various software applications are disclosed. At least one first configuration setting in a plurality of configuration settings for a software application is selected. At least one first graphical notification identifying an error preventing execution of the first configuration setting and another configuration setting in the plurality of configuration settings are generated and displayed. The first graphical notification is displayed on a user interface adjacent to a graphical location on the user interface associated with another configuration setting. At least one solution to the error is executed based on the at generated first graphical notification. An absence of errors preventing execution of the plurality of configuration settings is determined and the plurality of configuration settings is executed.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Cora Zimmermann, Jan Loehe, Balazs Rabel, Ning Gao
  • Publication number: 20180039565
    Abstract: Techniques for automated generation of inputs for testing microservice-based applications are provided. In one example, a computer-implemented method comprises: traversing, by a system operatively coupled to a processor, a user interface of a microservices-based application by performing actions on user interface elements of the user interface; and generating, by the system, an aggregated log of user interface event sequences and application program interface call sets based on the traversing. The computer-implemented method also comprises: determining, by the system, respective user interface event sequences that invoke application program interface call sets; and generating, by the system, respective test inputs based on the user interface event sequences that invoke the application program interface call sets.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Shriram Rajagopalan, Saurabh Sinha
  • Publication number: 20180039566
    Abstract: A computer-implemented method for testing a control program that is modeled as one or more blocks of a block diagram in a computing environment. A first user interface is provided for selecting a simulation mode for the block diagram and a second user interface is provided for selecting a compiler intended for production code compilation. When it is confirmed that a software-in-the-loop simulation mode has been selected in the first user interface, the blocks of the block diagram are converted to a production code and is compiled to an executable using the compiler selected in the second user interface. By running the executable on the host computer while recording one or more data points based on input/output signals and/or evaluating the compliance of the one or more data points to one or more criteria, the control program corresponding to the one or more blocks is tested.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Frank LUENSTROTH, Renate HEIN
  • Publication number: 20180039567
    Abstract: Techniques are provided for automated resiliency testing. In one example, a computer-implemented method comprises analyzing, by a system operatively coupled to a processor, an annotated state transition graph of a user interface of a microservices-based application, wherein the annotated state transition graph has edges annotated with application program interface call subgraphs. The computer-implemented method also comprises generating, by the system, an ordered list of the application program interface call subgraphs based on the analyzing.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Shriram Rajagopalan, Saurabh Sinha
  • Publication number: 20180039568
    Abstract: Embodiments of the present invention provide methods, computer program products, and systems to increase code coverage. Embodiments of the present invention can receive a copy of source code and data associated with a sample execution of a set of instructions specified by the copy of the source code. Embodiments of the present invention can insert, into the set of instructions specified by the copy of the source code, an instruction that corresponds to a code statement that precedes an untraversed code path within the received copy of the source code. Embodiments of the present invention can execute the set of instructions that include the inserted instruction and provide an option to redirect execution of the set of instructions at the inserted instruction. Embodiments of the present invention can generate a test case that increases code coverage based on the redirected execution of the set of instructions.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Steven Cooper, Michael S. Fulton
  • Publication number: 20180039569
    Abstract: Embodiments of the present invention provide methods, computer program products, and systems to increase code coverage. Embodiments of the present invention can receive a copy of source code and data associated with a sample execution of a set of instructions specified by the copy of the source code. Embodiments of the present invention can insert, into the set of instructions specified by the copy of the source code, an instruction that corresponds to a code statement that precedes an untraversed code path within the received copy of the source code. Embodiments of the present invention can execute the set of instructions that include the inserted instruction and provide an option to redirect execution of the set of instructions at the inserted instruction. Embodiments of the present invention can generate a test case that increases code coverage based on the redirected execution of the set of instructions.
    Type: Application
    Filed: July 24, 2017
    Publication date: February 8, 2018
    Inventors: Steven Cooper, Michael S. Fulton
  • Publication number: 20180039570
    Abstract: Techniques for automated resiliency testing systems are provided. In one example, a computer-implemented method comprises traversing, by a system operatively coupled to a processor, an application program interface call subgraph of a microservices-based application in a depth first traversal. The computer-implemented method also comprises, during the traversing, performing, by the system, resiliency testing of parent application program interfaces of the application program interface call subgraph according to a systematic resilience testing algorithm that reduces and/or eliminates redundant resiliency testing of parent application program interfaces.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Shriram Rajagopalan, Saurabh Sinha
  • Publication number: 20180039571
    Abstract: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 8, 2018
    Inventors: Yukikazu MATSUO, Yasuyuki TANAKA, Masaru SUGIMOTO, Kyosaku NOBUNAGA
  • Publication number: 20180039572
    Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Graziano Mirichigni, Danilo Caraccio, Luca Porzio
  • Publication number: 20180039573
    Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.
    Type: Application
    Filed: August 6, 2016
    Publication date: February 8, 2018
    Inventor: Chuen-Shen Bernard Shung
  • Publication number: 20180039574
    Abstract: A method for allocating cache for a disk array includes monitoring an I/O distribution of the disk array in a predetermined time period, determining a garbage collection state of the disk array, the garbage collection state allows the disk array to perform a garbage collection and prevents the disk array to perform the garbage collection, and determining an allocation of the cache based on the I/O distribution and the garbage collection state.
    Type: Application
    Filed: October 20, 2017
    Publication date: February 8, 2018
    Inventors: Zhengyuan Feng, Xue Dong Gao, Changping Lu, Ming Zhi Zhao
  • Publication number: 20180039575
    Abstract: Representative embodiments disclosed compress expressions so they utilize less physical storage. An expression is placed in a standard representation, such as an expression tree. The system utilizes one or more rules to identify portions of the expression that are likely to be common to other expressions. The common portions are extracted from the expression tree as a template and the remaining portions are hoisted from the expression as unique portions. If the template does not already reside in a cache, the template is stored in the cache. A cache reference is obtained for the template and combined with the unique portions to create a bundle that reduces storage requirements for the expression. The original expression is recovered by retrieving the template from the cache using the cache reference and placing the hoisted unique portions into their original locations in the template.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Inventors: Bart J. F. De Smet, Eric Anthony Rozell
  • Publication number: 20180039576
    Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
    Type: Application
    Filed: July 28, 2017
    Publication date: February 8, 2018
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Publication number: 20180039577
    Abstract: Flush avoidance in a load store unit including launching a load instruction targeting an effective address; encountering a set predict hit and an effective-to-real address translator (ERAT) miss for the effective address, wherein the set predict hit comprises a cache address of a cache entry; sending a data valid message for the load instruction to an instruction sequencing unit; and verifying the data valid message, wherein verifying the data valid message comprises: tracking the cache entry during an ERAT update; and upon completion of the ERAT update, encountering an ERAT hit for the effective address in response to relaunching the load instruction.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: SUNDEEP CHADHA, DAVID A. HRUSECKY, ELIZABETH A. MCGLONE, GEORGE W. ROHRBAUGH, III, SHIH-HSIUNG S. TUNG
  • Publication number: 20180039578
    Abstract: A method of operating a data storage device in which a nonvolatile memory is included and a mapping table defining a mapping relation between a physical address and a logical address of the nonvolatile memory is stored in a host memory buffer of a host memory includes requesting a host for an asynchronous event based on information about a map miss that the mapping relation about the logical address received from the host is not included in the mapping table, receiving information about the host memory buffer adjusted by the host based on the asynchronous event, and updating the mapping table to the adjusted host memory buffer with reference to the information about the host memory buffer. A method of operating a data storage device according to example embodiments of the inventive concept can reduce the number of map misses or improve reliability of a nonvolatile memory.
    Type: Application
    Filed: July 18, 2017
    Publication date: February 8, 2018
    Inventors: EUN-JIN YUN, SIL WAN CHANG
  • Publication number: 20180039579
    Abstract: Efficiently generating effective address translations for memory management test cases including obtaining a first set of EAs, wherein each EA comprises an effective segment ID and a page, wherein each effective segment ID of each EA in the first set of EAs is mapped to a same first effective segment; obtaining a set of virtual address corresponding to the first set of EAs; translating the first set of EAs by applying a hash function to each virtual address in the set of virtual addresses to obtain a first set of PTEG addresses mapped to a first set of PTEGs; and generating a translation for a second set of EAs to obtain a second set of PTEG addresses mapped to the first set of PTEGs.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: MANOJ DUSANAPUDI, SHAKTI KAPOOR
  • Publication number: 20180039580
    Abstract: Aspects are directed to a start-up or recovery method and a central processing unit (CPU) architecture. In one example, the CPU architecture includes read-only memory (ROM) storing instructions addressable by a first range of physical memory addresses, random access memory (RAM), a direct memory access (DMA) engine, the DMA engine controllable to transfer the instructions from the ROM to RAM, the instructions addressable by a second range of physical memory addresses at the RAM, a memory management unit configured to translate a range of virtual addresses to the first range while in ROM, and translate the range of virtual memory addresses to the second range while in RAM, and a CPU to execute a DMA interrupt service routine to update the memory management unit to translate the range of virtual addresses to the second range of physical memory addresses while the DMA engine transfers the instructions to RAM.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 8, 2018
    Inventor: Eric R. Schneider
  • Publication number: 20180039581
    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.
    Type: Application
    Filed: May 22, 2017
    Publication date: February 8, 2018
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Shih-Chang Huang
  • Publication number: 20180039582
    Abstract: In an information processing apparatus having a hardware security module (HSM), an HSM function that makes it possible to encrypt and decrypt data using the encryption key of the HSM is able to be set to be enabled under the condition that the encryption key of the HSM is able to be backed up.
    Type: Application
    Filed: July 26, 2017
    Publication date: February 8, 2018
    Inventor: Naoya Kakutani
  • Publication number: 20180039583
    Abstract: A storage device includes a nonvolatile semiconductor memory module, a first interface circuit, and a second interface circuit conforming to an interface standard different from an interface standard of the first interface circuit. One of the first interface circuit and the second interface circuit is connected to the nonvolatile semiconductor memory module via first wiring, and to terminals of the storage device for connection to a host via second wiring. The other one of the first interface circuit and the second interface circuit is not connected to either the nonvolatile semiconductor memory module or the terminals.
    Type: Application
    Filed: March 1, 2017
    Publication date: February 8, 2018
    Inventors: Shunsuke KODERA, Yoshio FURUYAMA
  • Publication number: 20180039584
    Abstract: A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. The first transceiver is coupled between the first pin and a node and includes a first current limiter. The second connector is configured to couple to a peripheral device and includes a second pin. The second transceiver is coupled between the node and the second pin and includes a second current limiter. The voltage processor processes the voltage of the node to generate an operation voltage. The controller receives the operation voltage to determine whether to turn on at least one of the first and second transceivers.
    Type: Application
    Filed: June 23, 2017
    Publication date: February 8, 2018
    Inventor: Tze-Shiang WANG
  • Publication number: 20180039585
    Abstract: In accordance with embodiments of the present disclosure, an adapter for different types of devices that are defined by a full set of capabilities for a communication protocol may include one or more ports, wherein each of the one or more ports is configured to receive one of the different types of devices, and a device controller communicatively coupled to the one or more ports. The device controller may be configured to, when one of the different types of devices is received by the one or more ports obtain information related to a detection of the one of the different types of devices and, based on the information related to the detection, expose a subset of capabilities from the full set of capabilities to a bus of the communication protocol, wherein the subset of capabilities is defined by the one of the different types of devices for the communication protocol.
    Type: Application
    Filed: July 28, 2017
    Publication date: February 8, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Bradley Allan LAMBERT, Michael A. KOST
  • Publication number: 20180039586
    Abstract: A memory circuit having: a memory array including one or more memory banks (418); a first processor (420); and a processor control interface for receiving data processing commands directed to the first processor from a central processor (P1, P2), the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
    Type: Application
    Filed: February 12, 2016
    Publication date: February 8, 2018
    Applicant: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Publication number: 20180039587
    Abstract: A memory network includes a plurality of memory nodes each identifiable by an ordinal number m, and a set of links divided into N subsets of links, where each subset of links is identifiable by an ordinal number n. For each subset of the plurality of N subsets of links, each link in the subset connects two memory nodes that have ordinal numbers m differing by b(n-1), where b is a positive number. Each of the memory nodes is communicatively coupled to a processor via at least two non-overlapping pathways through the plurality of links.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventor: Gabriel Loh
  • Publication number: 20180039588
    Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.
    Type: Application
    Filed: July 25, 2017
    Publication date: February 8, 2018
    Inventors: CHANGHO YUN, SUNG-JOON KIM
  • Publication number: 20180039589
    Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: HEMANT NAUTIYAL, RAJAN KAPOOR, ARVIND KAUSHIK, PUNEET KHANDELWAL
  • Publication number: 20180039590
    Abstract: A system includes a host device, an external bus and a storage device. A driver is installed in the host device. The external bus is connected with the host device. The external bus supports a communication protocol. The storage device includes a controlling circuit and a non-volatile memory. After the storage device issues a request to the host device according to the communication protocol, a reserved space is created in a host memory of the host device in response to the request, and a device information from the storage device is stored into the reserved space. While the host device issues a first command to operate the storage device, the first command is converted into a second command by the driver according to the device information, and then the second command is transmitted to the storage device.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Inventors: Jen-Yu Hsu, Yi-Chiang Wang, Chia-Hua Liu, Chao-Ton Yang, Tsung-Ching Chang
  • Publication number: 20180039591
    Abstract: A method is provided for operating a bus system in particular of a motor vehicle, in which messages of the bus system are received, and as a function of these messages, it is detected whether a party of the bus system sending these messages is a party logging on to the bus system.
    Type: Application
    Filed: July 27, 2017
    Publication date: February 8, 2018
    Inventors: Antonio La Marca, Joachim Steinmetz, Liem Dang
  • Publication number: 20180039592
    Abstract: The present disclosure relates to a distributed console server system. The system may have a server and a software module loaded onto the server for communications with a plurality of remote devices within a data center. A remote serial port unit may be included which is in communication with the server and which is controlled in part by the server and the software module. The remote serial port unit may be in communication with the plurality of remote devices. The remote serial port unit may include at least one of a first module including a plurality of RJ45 ports, or a second module including a plurality of USB ports.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 8, 2018
    Inventors: Dante KANKI, Marcelo E. PECCIN
  • Publication number: 20180039593
    Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 8, 2018
    Applicant: Intel Corporation
    Inventors: Mark Debbage, Yatin M. Mutha
  • Publication number: 20180039594
    Abstract: A system and method for enabling hot-plugging of devices in virtualized systems. A hypervisor obtains respective values representing respective quantities of a resource for a plurality of virtual root buses of a virtual machine (VM). The hypervisor determines a first set of address ranges of the resource that are allocated for one or more virtual devices attached to at least one of the plurality of virtual root buses. The hypervisor determines, in view of the first set of allocated address ranges, a second set of address ranges of the resource available for attaching one or more additional virtual devices to at least one of the plurality of virtual root buses. The hypervisor assigns to the plurality of virtual root buses non-overlapping respective address ranges of the resource within the second set.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Marcel Apfelbaum, Michael Tsirkin
  • Publication number: 20180039595
    Abstract: The present invention provides an apparatus for expanding a serial communication port. The apparatus includes a first serial port, a second serial port and a processing and control module. The first serial port is used to transmit a first signal, and the second serial port is used to transmit a second signal. The processing and control module is coupled between the first serial port and the second serial port. The processing and control module includes a first serial bus host controller, a second serial bus host controller, a data forwarding unit and an expansion unit. The apparatus is connected between an electronic device and multiple peripheral devices, so that via the expansion unit, each peripheral device generates its own communication port on the electronic device.
    Type: Application
    Filed: August 3, 2017
    Publication date: February 8, 2018
    Applicant: ATEN International Co., Ltd.
    Inventors: KUO-FENG KAO, LI-JEN CHANG, HSIANG-JUI YU
  • Publication number: 20180039596
    Abstract: A method of serial peripheral interface (SPI) communications for a resistive memory. The method includes transmitting resistive memory commands via the SPI to operate the resistive memory according to an SPI protocol. The SPI protocol includes a command byte, an address byte, and data bytes.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventor: Hyunsuk SHIN