Abstract: A device hosting a universal integrated circuit card (UICC or eUICC) initiates an electronic subscriber identity module (eSIM) installation flow with an SIM server. The purpose of the eSIM installation flow is to perform a profile provisioning action. The device and, for example, the eUICC preserve state information related to the eSIM installation flow. The eSIM installation flow includes generation of a one-time public key at the eUICC. In some instances, the eSIM installation flow may be interrupted by an error event before successful installation of the eSIM in the eUICC. A subsequent renewed installation attempt is locally initiated and completed without assistance of the eSIM server. In some embodiments, the recovery and subsequent successful eSIM installation make use of the state information preserved during the earlier eSIM installation flow.

Abstract: Provided are a computer program product, system, and method for a computer program product, system, and method for determining an availability score based on available resources of different resource types in a distributed computing environment of storage servers to determine whether to perform a failure operation for one of the storage servers. A health status monitor program deployed in the storage servers performs: maintaining information indicating availability of a plurality of storage server resources for a plurality of resource types; calculating an availability score as a function of a number of available resources of the resource types; and transmitting information on the availability score to a management program. The management program uses the transmitted information to determine whether to migrate services from the storage server from which the availability score is received to at least one of the other storage servers in the distributed computing environment.

Abstract: A port controller includes an advertise block configured to determine a cable assembly coupled to the port controller is not compliant with a standard used by the port controller, a comparator configured to determine a current drawn from a power converter coupled to the cable assembly exceeds a capability of the power converter based on comparing a bus voltage to a threshold voltage, and a protection block configured to, in response to determining the current drawn from the power converter exceeds the capability of the power converter, cause the current drawn from the power converter to be reduced.

Abstract: A method and system for assessing resiliency of a system is provided. A fault injection system may, for each of a plurality of dimensions of a fault profile, access an indication of possible values for the dimension, which may be specified by a user. The fault injection system may, for each of a plurality of fault profiles, automatically create the fault profile by, for each of the plurality of dimensions, selecting by the computing system a possible value for that dimension. For at least some of the fault profiles, the fault injection system injects a fault based on the fault profile into the system and determines whether a failure was detected while the fault was injected.

Abstract: A non-intrusive system which monitors a data center by detecting electromagnetic waves alleviates a resource burden on components and is inexpensive to deploy and scale within a data center. The system detects waves using omnidirectional antennas positioned throughout the data center, thus alleviating the need to physically attach directional antennas to components. The system performs a learning phase wherein representations of detected waves are mapped to occurrence of events within the data center. Once the learning phase is complete, operation of existing network monitoring tools, such as agents and probes, may cease, and the system may begin monitoring for events based on the detected waves. The system may also analyze wave data prior to the occurrence of events to identify event prediction indicators, e.g. distinctive wave values or patterns, which may be used to predict the occurrence of an event.

Abstract: Behavior data associated with a user is obtained. The behavior data is generated when the user uses an Internet service and includes a user identification and identification information indicating the Internet service. At least one predefined carbon-saving quantity quantization algorithm is determined based on the identification information related to the Internet service. A carbon-saving quantity associated with the user is calculated based on the obtained behavior data and the determined at least one predefined carbon-saving quantity quantization algorithm. Based on the calculated carbon-saving quantity associated with the user and the user identification, user data is processed. The user data is related to the carbon-saving quantity associated with the user.

Abstract: Example embodiments relate to forecast resource utilization. The example disclosed herein receives the first actual resource utilization, detects its pattern and trend, and determines the first forecasted resource utilization. Furthermore, a second actual resource utilization is received and its pattern is detected. Moreover, it is determined whether to forecast a new resource utilization.

Abstract: Cloud storage solutions are provided, in which different cloud storage spaces are aggregated together from the viewpoint of a user. Embodiments of the cloud storage space monitoring and management application provide systems for effective cloud storage management and monitoring, including uploading files to a cloud storage space, downloading files to a user's personal computing device, and migrating/sorting files between different cloud storage spaces. The cloud storage space monitoring and management application will also provide an integrated user interface that displays digital information stored in or more cloud storage spaces, which may be provided by various cloud storage service vendors, in a single display.

Abstract: Methods and systems for locale verification include converting a set of expected locale responses into a normalized format based on a locale data template. A user's filled locale data template in the normalized format is compared to the normalized set of expected locale responses using a processor. A report is generated that identifies mismatches between the received locale data template and the set of expected locale responses.

Abstract: A system is provided to run new code modules safely in a duplicative, protected environment without affecting the code modules that are already trusted to be on the system. The system receives a new code module that validates operational data of a computing device, and instantiates a new, parallel execution engine to run the new code module on the operational data in parallel with another execution engine running the trusted/verified code modules that also validate the same operational data. The new engine runs the new code module with the operational data to produce new code module results. The production engine runs the trusted/verified code modules with the operational data to produce verified code module results. The new code module results are combined with the verified code module results to produce combined results describing the operational status of the computing device.

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing profile guided indirect jump checking on a computing device, including encountering an indirect jump location of implementing an indirect jump during execution of a program, identifying an indirect jump target of the indirect jump, determining whether the indirect jump location and the indirect jump target are associated in a profile guided indirect jump table, and determining whether the indirect jump location and the indirect jump target are associated in a compiler guided indirect jump table in response to determining that the indirect jump location and the indirect jump target are not associated in the profile guided indirect jump table.

Abstract: A device may receive testing instructions, for testing a computer program product, in a first format. The testing instructions may include testing data and a testing script. The testing data and the testing script may be associated with the first format. The device may identify a set of commands in the first format. The device may extract the set of commands from the first format. The device may convert the testing instructions from the first format to a second format based on extracting the set of commands. The device may execute the testing instructions based on the second format.

Abstract: A method is provided for analyzing log message content. The computer-implemented method may include detecting, by at least one processor, log messages in an application code, identifying a log level assigned to each of the log messages, and performing natural language processing (NLP) analysis on each of the log messages by using at least keyword and synonym matching percentage analysis criteria. The computer-implemented method may further include determining, in response to the NLP analysis, a severity score of each of the log messages, and reclassifying, based on the severity score, the assigned log level of one or more of the log messages to a different log level.

Abstract: High-performance tracing can be achieved for an input program having a plurality of instructions. Techniques such as executable instruction transcription can enable execution of a plurality of instructions at a time via a run buffer. Execution information can be extracted via run buffer execution. Fidelity of execution can be preserved by executing instructions on the target processor. Other features, such as an executable extraction instruction ensemble, branch interpretation, and relative address compensation can be implemented. High quality instruction tracing can thus be achieved without the usual performance penalties.

Abstract: Recording a replay-able trace of execution of a multi-threaded process includes identifying a trace memory model that defines one or more orderable events that are to be ordered across a plurality of threads of the multi-threaded process. The plurality of threads are executed concurrently across one or more processing units of one or more processors. During execution of the plurality of threads, a separate replay-able trace is recorded for each thread independently. Recording includes, for each thread, recording initial state for the thread, recording at least one memory read performed by at least one processor instruction executed by the thread that takes memory as input, and recording a least one orderable event performed by the thread with a monotonically increasing number that orders the event among other orderable events across the plurality of threads.

Abstract: Recording a replay-able trace of execution of an executable entity using cache data includes executing one or more threads of the executable entity concurrently across one or more processing units of the one or more processors. During execution of the one or more threads, a separate replay-able trace is recorded for each thread independently. Recording includes, for each thread, recording initial processor register state for the thread. Recording also includes, for each thread, and upon detecting a processor data cache miss, recording at least one line of cache data imported into the processor data cache.

Abstract: Recording a replay-able trace of execution of an executable entity using cache data includes executing one or more threads of the executable entity concurrently across one or more processing units of the one or more processors. During execution of the one or more threads, a separate replay-able trace is recorded for each thread independently. Recording includes, for each thread, recording initial processor register state for the thread. Recording also includes, for each thread, and upon detecting a processor data cache miss, recording at least one line of cache data imported into the processor data cache. Recording also includes recording the occurrence of at least one event by recording its side effects.

Abstract: The current document is directed to a subsystem that is incorporated, in one implementation, within an automated application-release-management system. The subsystem to which the current document is directed determines, based on modifications to the source code for an application or another system that are submitted through a check-in process, a subset of tests within a large set of tests developed to test the application or system that invoke routines or other compilation units affected by the submitted source-code modifications. Only those tests that invoke routines and other compilation units affected by the source-code submissions need then be applied during testing and verification of the revised application or system.

Abstract: A method may include performing stack trace sampling to obtain a compiled list of transactions performed by a software application during a preconfigured timeframe, filtering the compiled list of transactions according to a set of filtering parameters to obtain a set of transactions instances that complies with the set of filtering parameters, and finding a set of non-instrumented methods within the set of transactions instances that complies with the set of filtering parameters. The set of non-instrumented methods may exceed a percentage threshold of a total transaction time of transactions that the set of non-instrumented methods are a part of and the percentage threshold may be user-configurable. The method may further include adding a set of instrumentation points into a points file, the set of instrumentation points associated with the set of non-instrumented methods.

Abstract: A system comprising a device capable of transmitting wireless signals, a television including a processor, and a computing system capable of communicating with the television and the device. The computing system includes at least one processor programmed to: build an application executable by the television, output the application for execution at the television, output, to the device, signals to cause a sequence of wireless signals to be transmitted by the device, wherein the television is positioned to detect the sequence of wireless signals, receive, from the television, information about operations performed by the television, and determine, based at least on the information about operations performed by the television and information about the sequence of wireless signals, whether the television has operated improperly in response to the sequence of wireless signals.

Abstract: A system for use in analyzing software code using a symbolic-execution technique. The system includes a hardware-based processing unit, and a non-transitory computer-readable storage component including a (i) concurrency-analysis module, (ii) a lightweight-analysis module, and (iii) a heavyweight-analysis module. The concurrency-analysis module, when executed by the hardware-based processing unit receives initial code and generates a potential interference matrix using the initial code. The lightweight-analysis module, when executed by the hardware-based processing unit, generates a final interface matrix using the potential interference matrix. The heavyweight-analysis module, when executed by the hardware-based processing unit, generates one or more test cases using the potential interference matrix.

Abstract: Techniques are provided for creating mock responses based on default data and mapping actual requests to those mock responses so that a service under test (SUT) may be executed within a simulated integration. In one technique, multiple example requests (ERs) that exemplify actual requests that the SUT may send during a test case are created. Each ER is configured to invoke a downstream service. For each ER, a mock downstream response that is based on default values is created. In a mapping, an association between each ER and its mock downstream response is stored. During the test, the SUT is invoked. Responsively, the SUT generates downstream requests to downstream services, regardless of actual availability. The computer intercepts each invocation of a downstream request. Based on the downstream request, the computer selects a mock downstream response from the mapping and provides the mock downstream response to the SUT.

Abstract: A system and method for developing a multi-layered test suite for an operating platform including a framework layer and a system layer includes executing a first test suite against a version of the operating platform modified based on a software faults. A first counter is incremented if a first test suite executed against the modified version of the operating platform fails. A second test suite can be executed against the modified version of the operating platform and test cases may be added to the first test suite based on whether the second test suite passes or fails.

Abstract: An example device in accordance with an aspect of the present disclosure includes a screen identification engine to identify a screen(s) of a test run, an element identification engine to selectively identify an element(s) among available elements of the screen(s), and a signature building engine to build a signature corresponding to the test run. The signature incorporates the screen(s) and element(s) to capture an application flow of the test run, while excluding available elements that do not correspond to the application flow.

Abstract: A system and method for monitoring an application is disclosed. The application is monitored using a monitoring tool that is decoupled from the corresponding testing tool. When the monitoring tool desires a test to be run it communicates with the testing tool through a scheduler to cause the testing tool to initiate the desire test on the application and report the results of the test back to the monitoring tool.

Abstract: A code testing system identifies code for an application as being related to publically-available code, and modifies testing for the application for the code segments corresponding to the publically-available code. The code testing system identifies code segments in the application and generates a signature of the code segment. The signature is matched against signatures for publically-available code, and code segments for the application that match the publically-available code are identified. The matching segments may be tested with different analysis than the code which does not match publically-available code and thus correspond to privately developed code by an application developer.

Abstract: A method for resolving software problems is provided. The method may include receiving a plurality of stored error pattern data sets including a stored error pattern indicative of a historical pattern of errors and corrective action data indicative of a set of corrective action(s) designed to be used in response to the corresponding historical pattern of errors; receiving a subject error pattern data set corresponding to a subject error pattern that was experienced by a system of computing device(s); comparing the subject error pattern to each of the plurality of stored error patterns to determine a ranking of the plurality of stored error patterns for closeness to the subject error pattern, comparing positions of errors and an order errors as between the subject error pattern and the stored error pattern; presenting at least a portion of the ranking of the plurality of stored error patterns and corresponding corrective action data.

Abstract: The disclosed deployment testing system includes a test loader that loads and parses test objects and the antecedent test objects on which the selected test object depends, to prepare a test sequence. A database of test objects apply to one or more SUT and specify aspects of deployed SUT configuration that include hardware configuration, active connection of the SUT to other network devices, configuration of the actively connected network devices to accept access by the SUT, presence of files and applications in storage, and services running on the SUT; identify dependencies on antecedent test objects; specify test object features that extend object features found in the antecedent test objects; and override test parameter values in the antecedent test objects. A test executor obtains administrative credentials for accessing and testing a SUT and uses the test and antecedent test objects to verify the SUT; and a test reporter publishes tester results.

Abstract: A method performed by a processor to improve wear-leveling in a cross-point (X3D) memory, comprises detecting, by a processor coupled to the X3D memory, a trigger event, wherein the X3D memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.

Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.

Abstract: Various embodiments are generally directed to techniques for implementing memory segmentation in a welding or cutting system. Techniques described herein may include a computer-implemented method including identifying, by a processor, one or more pages within a FLASH storage module. The processor may determine the sizes of each identified page. The processor may identify one or more software modules to be stored within the FLASH storage module. The processor may determine the sizes of each identified software module. The processor may store each identified software module in an appropriately sized page of the FLASH storage module.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature.

Abstract: Embodiments of recovering data in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving a failure notification indicating that a core of a main processor is experiencing a catastrophic failure causing the core unable to execute instructions. In response, a flush command can be issued to an uncore of the processor via a debug port instructing the uncore to copy any data currently residing in a processor cache of the main processor to a volatile memory. The method further includes issuing a self-refresh command causing the volatile memory to enter a self-refresh mode in which the data copied from the processor cache is maintained and unmodifiable by the main processor during a reset of the main processor.

Abstract: A data storage device includes a write cache, a non-volatile memory and a controller coupled to the write cache and to the non-volatile memory. The controller is configured to, responsive to receiving a plurality of flush commands, write all data from the write cache to the non-volatile memory while executing fewer than all of the plurality of flush commands.

Abstract: Examples described herein relate to caching in a system with multiple nodes sharing a globally addressable memory. The globally addressable memory includes multiple windows that each include multiple chunks. Each node of a set of the nodes includes a cache that is associated with one of the windows. One of the nodes includes write access to one of the chunks of the window. The other nodes include read access to the chunk. The node with write access further includes a copy of the chunk in its cache and modifies multiple lines of the chunk copy. After a first line of the chunk copy is modified, a notification is sent to the other nodes that the chunk should be marked dirty. After multiple lines are modified, an invalidation message is sent for each of the modified lines of the set of the nodes.

Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Abstract: Memory compression devices, systems, and associated methods are provided and described. Such devices, systems, and methods increase the effective bandwidth and reduce power consumption of non-volatile memory subsystems.

Abstract: A method and apparatus are described for assigning mastership of nodes to data blocks. A method involves connecting each session of a plurality of sessions to a particular node of a cluster of nodes based on services associated with the plurality of sessions. Each session of the plurality of sessions is associated with a respective service of a plurality of services. The method also involves collecting service-based access statistics aggregated by service and ranges of data block addresses. Each range corresponds to one or more contiguous subrange of data block addresses. The method further involves assigning mastership of the nodes to the data blocks having addresses within said ranges of data block addresses based on services associated with the nodes and the service-based access statistics.

Abstract: A processing device includes a first counter having a first count value of a number of child pages among a plurality of child pages present in an enclave memory of a first virtual machine (VM). The plurality of child pages are associated with a parent page in the enclave memory. The processing device includes a second counter having a second count value of a number of child pages among the plurality of child pages not present in the enclave memory and being shared by a second VM, wherein the second VM is different from the first VM. A non-zero value of at least one of the first counter or the second counter prevents eviction of the parent page from the enclave memory.

Abstract: Systems, methods, and computer readable media to improve the operation of electronic devices that use integrated cache systems are described. In general, techniques are disclosed to manage the leakage power attributable to an integrated cache memory by dynamically resizing the cache during device operations. More particularly, run-time cache operating parameters may be used to dynamically determine if the cache may be resized. If effective use of the cache may be maintained using a smaller cache, a portion of the cache may be power-gated (e.g., turned off). The power loss attributable to that portion of the cache power-gated may thereby be avoided. Such power reduction may extend a mobile device's battery runtime. Cache portions previously turned off may be brought back online as processing needs increase so that device performance does not degrade.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: A face recognition system and method for face recognition are provided. The face recognition system includes a camera for capturing an input image of a face of a person to be recognized. The face recognition system further includes a cache. The face recognition system further includes a set of one or more processors configured to (i) improve a utilization of the cache by the one or more processors during multiple training stages of a neural network configured to perform face recognition, by performing a stage-wise mini-batch process on a set of samples used for the multiple training stages, and (ii) recognize the person by applying the neural network to the input image during a recognition stage. The stage-wise mini-batch process waits for each of the multiple training stages to complete using a system wait primitive to improve the utilization of the cache.

Abstract: A query is performed to obtain cache residency and/or other information regarding selected data. The data to be queried is data of a cache line, prefetched or otherwise. The capability includes a Query Cache instruction that obtains cache residency information and/or other information and returns an indication of the requested information.

Abstract: Methods and apparatus related to framework and/or methodology for selective caching of Erasure Coded fragments in a distributed storage system are described. In one embodiment, a plurality of fragments of a data object are generated. Each of the plurality of fragments is Erasure Coded (EC) prior to storage at a storage node of a plurality of storage nodes. Each of the plurality of fragments is transmitted with a caching hint to indicate whether that fragment is to be cached at the storage node. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.

Abstract: A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction processing pipeline includes execution logic that executes at least one thread in different protection domains over time, wherein the different protection domains are defined by descriptors each including first data specifying a memory region of the address space employed by the hierarchical memory system and second data specifying permissions for accessing the associated memory region. The address space can be a virtual address space or a physical address space. The protection domains can be associated with different turfs each representing a collection of descriptors. A given thread can execute in a particular protection domain(turf), one protection domain (turf) at a time with the particular protection domain (turf) selectively configured to change over time.

Abstract: A system and method of translation bypass includes a hypervisor configuring a host input-output memory management unit to translate a guest memory of a guest virtual machine. The hypervisor reserves a first portion of the guest memory. The hypervisor receives, from the guest virtual machine, a guest physical address. The hypervisor stores the guest physical address in the first portion of the guest memory. The hypervisor configures a device to access the first portion of the guest memory to locate a command.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: The present disclosure relates to caching content at a device in a group of co-located devices whose owners share social network connections. In one embodiment, a method generally includes electing the device as a leader device based, at least in part, on shared social network connections associated with owners of each device in the group. The device receives a data request from a first user device and searches a cache for the data. If the data exists in the cache, the data is encrypted using an encryption key associated with an owner of the first user device transmitted to the first user device. Otherwise, the device requests the data from the content provider, receives an encrypted copy of the data, decrypts the data, and uses the encryption key associated with the owner of the first device to generate and transmit an encrypted message including the data to the first device.