Abstract: An audio loudness data collection module collects and stores audio data. The data can be stored for a first time period. A monitoring system can access and store the audio data collected and stored by the loudness data collection module according to a second time period. The stored audio data can be processed and displayed to a user in a number of ways. The data can also be used to provide loudness data control. For example, a loudness data control module can perform an audio AGC function to control audio loudness.

Abstract: A system is provided for limiting distortion of an audio speaker. The system includes a first lowpass filter circuitry that is configured to receive a system input signal and generate a first lowpass filtered output signal. The system also includes a first limiter circuitry that is configured to limit the first lowpass filtered output signal. Limiting the first low pass filtered output signal includes reducing an amplitude of the first lowpass filtered output signal below a first predetermined threshold value, thereby to generate a first limited output signal. A second lowpass filter circuitry is configured to receive the first limited output signal and to generate a second lowpass filtered output signal.

Abstract: A circuit for tuning an impedance matching network is disclosed. The circuit includes a current sensor, a control circuit coupled to the current sensor and a reference current source and a tunable capacitor coupled to the control circuit. The control circuit is configured to generate a control signal based on an output of the current sensor, wherein the control signal is configured to vary a capacitance of the tunable capacitor.

Abstract: A ladder filter includes a plurality of series resonators and a plurality of shunt resonators connected between an input port and an output port. At least one of the series or shunt resonators include a bulk acoustic wave (BAW) resonator structure, which includes: a first electrode disposed over a substrate; an air cavity located in the substrate and below the first electrode; a piezoelectric layer disposed over the first electrode and comprising aluminum scandium nitride, the piezoelectric layer having a thickness in a range of approximately 1.0 microns to approximately 1.5 microns; and a second electrode disposed over the piezoelectric layer. The BAW resonator structure has an area, and the area is less than an area of a comparable BAW resonator structure comprising identical layers and materials except for an undoped aluminum nitride piezoelectric layer.

Abstract: A substrate structure for an acoustic resonator device. The substrate has a substrate member comprising a plurality of support members configured to form an array structure. In an example, the substrate member has an upper region, and optionally, has a plurality of recessed regions configured by the support members. The substrate has a thickness of single crystal piezo material formed overlying the upper region. In an example, the thickness of single crystal piezo material has a first surface region and a second surface region opposite of the first surface region.

Abstract: A high frequency module includes a first external connection terminal, a second external connection terminal, a filter unit, a first matching circuit, and a second matching circuit. The filter unit is connected between the first external connection terminal and the second external connection terminal. The first matching circuit is connected between the first external connection terminal and the filter unit. The second matching circuit is connected between the second external connection terminal and the filter unit. The first matching circuit and the second matching circuit are inductively or capacitively coupled to each other.

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis.

Abstract: Certain implementations of the disclosed technology may include systems and methods for high-frequency resonant gyroscopes. In an example implementation, a resonator gyroscope assembly is provided. The resonator gyroscope assembly can include a square resonator body suspended adjacent to a substrate, a ground electrode attached to a side of the resonator body, a piezoelectric layer attached to a side of the ground electrode, a drive electrode in electrical communication with the piezoelectric layer, and configured to stimulate one or more vibration modes of the square resonator body; and a sense electrode in electrical communication with the piezoelectric layer, and configured to receive an output from the square or disk resonator responsive to stimulation of the one or more vibration modes.

Abstract: A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.

Abstract: To provide a voltage detection circuit which avoids unintentional on/off-control of an output transistor immediately after starting a power supply. A voltage detection circuit is configured to be equipped with a comparator which compares a detected voltage and a reference voltage, and an inverter which drives an output transistor, based on an output of the comparator and to supply the operating current of the inverter by a current source.

Abstract: A switching circuit is disclosed. The switching circuit includes a normally-on switching element, a normally-off switching element, a switching unit and a power source. The drain of the normally-off switching element is electrically connected to the source of the normally-on switching element. The source of the normally-off switching element is electrically connected to the gate of the normally-on switching element. The power source and the switching unit are configured to form a serial-connected branch. A first terminal of the serial-connected branch is electrically connected to the drain of the normally-off switching element. A second terminal of the serial-connected branch is electrically connected to the source of the normally-off switching element.

Abstract: A circuit includes a switching element with a first terminal, a second terminal and a control terminal. The circuit also includes an impedance network coupled between the control terminal and a switching node. The circuit also includes a first accelerating element coupled between the control terminal and a first node. The first node is different from the switching node. The circuit is configured to temporarily activate the first accelerating element when a switching state of the switching element is to be changed.

Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

Abstract: A brown-out detector and power-on-reset circuit can be used to monitor a supply voltage to determine when brown-out and power-on events occur and provide the appropriate reset signal in response. The circuit can include a comparator to generate the reset signal and a first monitoring circuit that operates in conjunction with a second monitoring circuit to provide an input voltage to the comparator. The first monitoring circuit can incorporate a bandgap circuit and can be used to control the input voltage based on the comparison of the supply voltage and a corresponding supply voltage threshold. The second monitoring circuit can incorporate a diode and can be used when the supply voltage is lower than a threshold voltage for the bandgap circuit. The second monitoring circuit can be used to control the input voltage based on a comparison of the supply voltage and a threshold voltage for the diode.

Abstract: A semiconductor assembly includes a first FET integrated within the semiconductor assembly and comprising gate, source and drain terminals. The semiconductor assembly further includes a low voltage switching device integrated within the semiconductor assembly and being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal.

Abstract: A switching circuit includes a first diode coupled between a first terminal and a second terminal, a second diode coupled between the first terminal and a third terminal, and a bias circuit coupled to the first terminal and configured to bias the first diode on and the second diode off in a first switch state and to bias the first diode off and the second diode on in a second switch state, the bias circuit including a voltage converter configured to convert a fixed voltage to an intermediate voltage and a current source coupled in series with the voltage converter.

Abstract: A superconducting switch system is provided that includes a filter network having a first SQUID coupled to a second SQUID via a common node, an input port coupled to the common node, a first output port coupled to the first SQUID, and a second output port coupled to the second SQUID. The superconducting switch system also includes a switch controller configured to control an amount of induced current through the first SQUID and the second SQUID to alternately switch the first and second SQUIDS between first inductance states in which a desired bandwidth portion of a signal provided at the input terminal passes to the first output terminal and is blocked from passing to the second output terminal, and second inductance states in which the desired bandwidth portion of the input signal passes to the second output terminal and is blocked from passing to the first output terminal.

Abstract: An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load.

Abstract: An optical sensor, optical system, and proximity sensor are disclosed. An illustrative proximity sensor is disclosed to include a light source, a photodetector including a photo-sensitive area that receives incident light and converts the received incident light into an electrical signal, and a plurality of polarization layers stacked on the photodetector that limit light from becoming received incident light for the photo-sensitive area to light traveling toward the photodetector along a predetermined path.

Abstract: [Problem] To provide a termination control apparatus that can provide an optimum termination state. [Solution] Included are: an input terminal to which an input signal is inputted; a termination resistance unit that terminates the input terminal by use of a variable resistor the resistance value of which can be set; a voltage measurement unit that measures the voltage of the input signal; and a control unit that changes the resistance value or a target voltage range when the voltage is not within the target voltage range having been set for the input signal on the basis of both an absolute maximum rated value and an operation-guaranteed voltage.

Abstract: A bootstrap circuit integrated to a voltage converter integrated circuit (IC) and a voltage converter IC for a switch mode voltage regulator. The bootstrap circuit is used to provide a bootstrap voltage signal for driving a high side switch of the voltage converter IC. The bootstrap circuit has a pre-charger and a bootstrap capacitor. The pre-charger provides a first bootstrap signal to pre-charge a control terminal of the high side switch, and the bootstrap capacitor provides a second bootstrap signal to enhance the charge of the control terminal of the high side switch.

Abstract: A data output circuit includes a data driving unit suitable for driving a data transmission line with a driving voltage corresponding to data during a data transmission operation, and a charging/discharging unit suitable for storing charges on the data transmission line and reuse the stored charges as the driving voltage.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract: A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

Abstract: A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

Abstract: An atomic oscillator includes an alkali metal cell encapsulating an alkali metal atom; a light source that emits laser light; a light detector that detects light which has passed through the alkali metal cell; and a polarizer arranged between the alkali metal cell and the light detector. A modulation frequency in the light source is controlled, according to a coherent population trapping resonance which is a light absorption characteristic of a quantum interference effect for two kinds of resonant lights, by modulating the light source to generate sidebands and injecting laser lights with the sidebands into the alkali metal cell. A magnetic field is applied on the alkali metal cell in a direction parallel to a propagating direction of the laser light, and the laser light entering the alkali metal cell has a linear polarization, which is not parallel to a polarization direction of the polarizer.

Abstract: An analog to digital converter includes an error integration circuit configured to receive an input charge from a detector and to integrate a difference between the input charge and one or more feedback charge pulses to create an error voltage. A quantizer is in operable communication with the error integration circuit and is responsive to the created error voltage. An accumulator having a mantissa component and a radix component is in operable communication with the quantizer. A charge feedback device in operable communication with the quantizer and the radix component of the accumulator. The charge feedback device is configured to generate the one or more feedback charge pulses proportional to the radix component of the accumulator and an output of the quantizer. Digital focal plane read out integrated circuits including the analog to digital converter are also disclosed.

Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

Abstract: A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

Abstract: A processor includes a decoder to decode an instruction to compress an input data stream and an execution unit for executing the instruction. The execution unit to generate metadata for a current input of the input data stream, the metadata comprises a first hint based on a portion of a current input that represents the input data stream at a current offset, select a first pointer to identify a location in a history buffer in a hash chain, determine whether the metadata generated for the current input matches metadata previously generated for the first pointer, and filter the first pointer from a search for a best match for the current input in the history buffer based on the determination that at least a portion of the metadata for the current input does not match a portion of the metadata for the first pointer.

Abstract: A method and apparatus are provided for implementing preemptive customized Codeset Converter Selection (CCS) on Software as a Service (SaaS) in a computer system. A codeset converter is automatically selected for operational modes, customer requests and service tasks which prompt the launching of the SaaS application. The CC selection is based upon history logs, content, and learned behavior performed as the application is launched and referenced without the user having to restart the session. Launching a new session is not needed for the enablement of the CC function.

Abstract: A coding scheme for coding “code constructs” (for example, alphanumeric characters) into “bit sequences,” where at least one of the code constructs is assigned at least two different bit sequences (that is, a first bit sequence and a second bit sequence). This is sometimes referred to herein as “alternative codings for a single code construct.” In some embodiments, at least one of the alternative codings includes bits that can be used for error detection and/or correction. In some embodiments, the code scheme will be similar to a pre-existing code scheme that does not have alternative codings for a single code construct so that the alternative-codings coding scheme is back compatible with data encoded under the pre-existing coding scheme.

Abstract: A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Abstract: Provided are an antenna system, an integrated communication structure and a terminal. The antenna system comprises: a first antenna which is connected to transmission paths of a plurality of communication modules and used for transmitting transmission signals from each of the transmission paths; and a second antenna which is connected to receiving paths of the plurality of communication modules and used for transmitting a received signal from the outside to a corresponding communication module via a corresponding receiving path. By means of the technical solution of the present invention, transmitting antennas and reception antennas of all communication modules in a terminal can be integrated respectively. The number of antennas can be effectively reduced, and the stacking difficulty is reduced, thereby avoiding antenna interference among a plurality of communication devices, and making it easy to realize multi-mode.

Abstract: A multiplexer includes a common terminal connected to an inductance element at a connection path with an antenna element, filter elements including different pass bands and connected to the antenna element with the common terminal therebetween, and an inductance element arranged in series between a transmission filter with a largest capacitance when viewed from the antenna side among the filter elements and the common terminal. An inductive component of the inductance element and a capacitive component of the transmission filter element define an LC series resonant circuit, and a resonant frequency of the LC series resonant circuit is lower than any of pass bands of the filter elements.

Abstract: A wireless communication device may reduce a receive sensitivity in the face of a high number of interfering communications to improve uplink throughput. In a listen-before-talk scenario, a device detecting a large number of undesired received communications may not transmit uplink data in the face of crowded traffic conditions. To avoid this scenario, if a desired communication link has a sufficiently high RSSI, a device may reduce its receive sensitivity to reduce the number of detected undesired communications while maintaining sufficient quality of the desired communication link. This approach will increase uplink throughput and improve communication performance.

Abstract: A method is provided that comprises tuning a radio system to a frequency band that contains a locally-broadcast terrestrial radio signal. The locally-broadcast terrestrial radio signal comprising a main signal component and a side data component is thereby received. In response to receiving the locally-broadcast terrestrial radio signal a determination is made as to a permissible time for processing the side data component using a time slot schedule. The side data component is processed at the permissible time. A message corresponding to the side data component is outputted to an output device. In some instances, the side data component includes the message. In other instances, the method further includes searching a message lookup list using a code included in the side data component. When a stored code is found that matches the code, the message corresponding to the matching stored code is outputted.

Abstract: The present application discloses a signal processing apparatus and method, the method includes: receive an analog signal; adjust a frequency band of the analog signal to a lowest frequency band when a frequency band of the analog signal received by the receiving unit falls outside the lowest frequency band in multiple preconfigured frequency bands; process, by using a signal processing channel in the lowest frequency band, the analog signal whose frequency band has been adjusted to the lowest frequency band. The method provided in the embodiments of the present application processes signals of different frequency bands by using a processing channel in a lowest frequency band. In this way, only a relatively small quantity of radio-frequency link components are required to implement processing of the signals of the different frequency bands, which reduces a link size of a communications system.

Abstract: Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.

Abstract: A radio equipment and a method for interconnecting components in the radio equipment are disclosed. The radio equipment includes a signal processing module and a radio component positioned relative to each other for a high-speed connection using at least a first mechanical connector and a high-speed connector. The first mechanical connector includes a first part disposed on the radio component and a second part disposed on the signal processing module. The high-speed connector includes a first part disposed on the radio component and a second part disposed on the signal processing module. At least one high-speed processing capability is provided to the radio equipment using the signal processing module through the high-speed connector. The signal processing module and the radio equipment are interchangeably connected.

Abstract: A method implemented by an enterprise server to facilitate activation of a virtual subscriber identity module (SIM) service on a mobile communication device. The method includes detecting a triggering event and in response to detecting the triggering event: determining that a SIM application on a physical universal integrated circuit card (UICC) currently inserted into the mobile communication device is associated with a mobile network operator (MNO) providing one or more virtual SIMs to which the enterprise server has access; determining whether the SIM application on the physical UICC is associated with one of the virtual SIMs provided by the MNO; and if the SIM application on the physical UICC is associated with a virtual SIM provided by the MNO, sending a message to the mobile communication device indicating that the mobile communication device is enabled for a virtual SIM service.

Abstract: A method includes detecting, by a contact sensing layer, a position of one or more fingers of a mobile device user, the contact sensing layer is located in a back area of a mobile device and the one or more fingers of the mobile device user are in direct contact with the contact sensing layer, receiving the detected position of the one or more fingers, identifying a plurality of advanced features contained in at least one software application running on the mobile device, selecting a feedback type based on the plurality of advanced features, and sending the selected feedback type to an interactive layer of the mobile device causing the interactive layer to generate a notification which is detectable by the one or more fingers, the notification communicates at least one of the advanced features to the mobile device user.

Abstract: A removable case for a mobile device formed from a molded pulp that is capable of conforming to the shape of the mobile device. The elasticity of the molded pulp material allows it to conform to the shape of the mobile device and to retain the mobile device within the case. This elasticity also aids in the protection of the mobile device. The molded pulp case has a plurality of sides that cover at least a portion of the side walls of the mobile device and overlap a portion of the front panel of the mobile device. A back panel covers a substantial portion of the rear panel of the mobile device.

Abstract: A protective case for a mobile device such as a tablet computer is disclosed that includes modular components that can be mixed and matched by the user at the point of purchase to facilitate creation of a user customizable look. The case includes a shell that is configured to retain the tablet device and a front cover that is configured to protect and conceal the screen of the tablet when the case is in the closed position. When the assembled case is in the open position and the tablet is retained within the shell, the cover is configured to stand the shell up on edge. The shell and front cover can be reversibly attached to one another by the user, so that the user can select a shell of one color, material, design, or style and a front cover of another color, material, design or style. Retention tab and slot are employed to reversibly lock the front cover to the shell to form a seamless integrated multi use mode case.

Abstract: A digitally controlled phase shifter and (optional) attenuator circuit that has both a broad range as well as a fine-tuning resolution. Embodiments maintain a full 360° phase range while providing nth-bit least-significant bit (LSB) resolution across the entire range of possible phase shift and attenuation states, and compensate for the effect of frequency and/or PVT variations. In embodiments, two or more range partitionings can be defined that can be monotonic over respective sub-ranges while providing full coverage when combined. One such partitioning is a “coarse+fine” architecture. Embodiments of the coarse+fine architecture provide for greater than 360° of range for phase shifting and more than the total nominal design level for attenuation, and provide for fine ranges for both phase shifting and attenuation that are greater than the LSB of the corresponding coarse ranges for phase shifting and attenuation.