Abstract: Adding an instance to a series in a fashion that preserves the series for both modern and legacy systems, even when the addition would not ordinarily be compatible with the legacy system. A method includes identifying a master message. The master message includes default values for events in the series. The method further includes identifying user input for a new event in the series. The user input identifies exceptions to the default values. The method further includes creating an instance message that includes default values from the master message for which there are no exceptions identified in the user input and includes the exceptions from the user input.

Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.

Abstract: A software update system for a vehicle is disclosed, as well as a method of determining whether to install a software update at an electronic control unit (ECU) in the vehicle. The method includes the steps of: receiving at the ECU a first signal from a first vehicle system module (VSM) in the vehicle; receiving at the ECU a second signal from a second VSM in the vehicle, wherein the first and second signals each provide an indication that the vehicle is in a stationary state; based on the first and second signals, assessing at the ECU that the vehicle is in the stationary state, wherein the assessment is in accordance with a first predetermined confidence level; and in response to the assessment, authorizing at the ECU an installation of the software update on ECU memory.

Abstract: A method for upgrading microcode in a multi-module storage system may include selecting a first module from two or more modules and operating the first module using an upgraded microcode. The method may include monitoring the performance of the first module by a second module of the two or more modules and rendering an indication of performance of the first module. Further, the method may include determining whether the indication of performance of the first module is greater than or equal to a performance metric.

Abstract: Modification of the execution of a platform-independent first method of an application within an integrated circuit card having a first non-volatile memory, a second rewritable non-volatile memory, a virtual machine and a processor unit, wherein said platform-independent first method includes a first operations sequence and a second operations sequence.

Abstract: An apparatus for voltage regulation device adjustment includes an external factor module that determines external factors, where the external factors include conditions external to an electronic device that affect operating performance and operating costs. The electronic device includes a voltage regulator device (“VRD”) providing power to one or more components of the electronic device. The apparatus includes a firmware selection module that selects new firmware for the VRD of the electronic device in response to the determined external factors, and a firmware update module that replaces previously installed firmware on the VRD with the new firmware. The new firmware includes control settings for the VRD.

Abstract: Systems, methods, and non-transitory machine readable medium are provided for creating a structured report that aggregates information related to a plurality of source code files based on selective scanning of one or more repositories. A repository search request is received including a repository identifier, a project identifier, and a search term. The specified repository is scanned to identify source code files for the specified project that include the search term. It is determined whether an instance of a search term within the source code file corresponds to a reserved term. A report is generated identifying the source code files that include an instance of the search term. A new file directory is created, and populated with a first results file including the generated report.

Abstract: A system for mapping source code from a conforming format to a personalized format includes a mapping module configured in a memory to store a plurality of mapping rules, each of the plurality of mapping rules specifying modification of a source code component from a conforming format to a personalized format and a serializer module configured to apply the one or more of the plurality of mapping rules to a source code file to generate a modified file to be displayed by an integrated development environment (IDE).

Abstract: Methods, systems, and/or devices for determining relevant changes to an API are described herein. In one aspect, a server system receives a request from a client to compare two versions of an API. A comparison of the two versions, and any intervening versions, of the API is performed by a server, which may then rank the comparison results based on the call volume or other criteria and will return the ranked results to a client for display to a user. Options include restricting the list of changes to just changes impacting a specific client application.

Abstract: Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed.

Abstract: The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.

Abstract: Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.

Abstract: Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

Abstract: A method and system for implementing very long instruction words (VLIW), the system operable to: receive a first very long instruction word (VLIW) including a set of slot instructions corresponding to a set of functional units, where: each slot instruction includes an opcode identifying an operation to be performed by the set of functional units and value fields related to the operation, where a dedicated subset of the value fields include dedicated bits dedicated to the slot instruction and an allocable subset of the value fields include allocable bits allocable to other slot instructions; identify the opcodes of each slot instruction; determine, based on the opcodes, which allocable bits are allocated to which slot instructions; and instruct each functional unit to perform an operation identified by a corresponding slot instruction using the corresponding dedicated bits and any allocable bits determined to be allocated to the slot instruction.

Abstract: A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.

Abstract: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor as part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. The number of linked-list data structures formed is variable and related to the number of program threads running on the processor. The graduation controller includes linked-list head identification registers and linked-list tail identification registers that facilitate reading and writing identifications values to linked-list data structures associated with particular program threads.

Abstract: A processor may include a reorder buffer, reservation stations, and execution units. The reorder buffer may be a circular buffer with a head pointer and a tail pointer, configured to assign indexes to instructions. Reservation stations may be configured to host instructions with the assigned indexes, while waiting to be issued to the execution units. Responsive to exception event, reservation stations may be configured to flush instructions that are younger, in program order, than the instruction executed with exception. Execution units may provide the reorder buffer index EX of the instruction executed with exception. The reorder buffer may provide the reorder buffer index TP stored in the tail pointer. Reservation stations may be configured to flush instructions with assigned indexes in the wrapped-around increasing interval from the index EX to the index TP.

Abstract: Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.

Abstract: Embodiments of the present application disclose a computer instruction processing method, a coprocessor, and a system. The computer instruction processing method includes: receiving, by a coprocessor, a first instruction set migrated by a central processing unit CPU; acquiring, according to the first instruction set that is applicable to the CPU for execution, a second instruction set for execution in the coprocessor; and executing binary codes in the second instruction set. In this way, the coprocessor that executes the second instruction set substitutes for the CPU that executes the first instruction set, CPU load is reduced, and usage of the coprocessor is improved.

Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.

Abstract: A method for applications includes: determining context-related information based on a system signal obtained; executing a target application corresponding to the context-related information, wherein the target application comprises at least one application unit; and using the target application to perform a corresponding operation.

Abstract: A surveillance system includes one or more camera systems at least some of the camera systems including a camera element comprising optical components to capture and process light to produce images, camera processing circuitry that receives the light and processes the light into electrical signals and encodes the signals into a defined format, power management circuitry to power the camera system, the power management system including first and second power interfaces and first and second video output interfaces.

Abstract: A method and device applied in an Android data processing system for performing synchronous control via an external apparatus. A control message from the external apparatus is received via a communication channel connected to the external apparatus. A pre-stored event generation procedure is executed by an Android Shell user privilege to convert the control message from the external apparatus into an event message identifiable by the Android data processing system. The Android data processing system identifies the event message and generates a corresponding control event to perform corresponding operations based on the control event. The external apparatus is used to synchronously control the Android data processing system and variation on the Android data processing system is less.

Abstract: A display control method includes: based on information acquired from an information processing terminal that accesses content provided by an information processing device, computing a degree of interest and a degree of perplexity, with respect to the content, of a user using the information processing terminal; and, based on the computed degree of interest and the computed degree of perplexity, displaying a symbol corresponding to the information processing terminal at a corresponding position in a region that has degree of interest and degree of perplexity as axes.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: A method of expanding the function of an Android standard multimedia player is provided in the invention. The method includes the steps of: registering on an Android system an expanded multimedia player that is different from the Android standard multimedia player; setting on the Android operating system a derived class inheriting a JAVA interface layer of the Android player; instructing the expanded multimedia player to perform multimedia playing with respect to a playing target via the derived class. A multimedia playing system is further provided in the invention. The present invention can improve media capability of the multimedia player through the above method, thereby effectively improving user experience.

Abstract: A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The virtual adapter is for use by a guest of the host system in performing data input and output. The activating activates the virtual adapter absent involvement of the guest. Based on activating the virtual adapter, the control component obtains configuration information of the activated virtual adapter from the physical adapter, the configuration information generated based on the activating. The control component ascertains a configuration of the activated virtual adapter based on the obtained configuration information.

Abstract: A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The virtual adapter is for use by a guest of the host system in performing data input and output. The activating activates the virtual adapter absent involvement of the guest. Based on activating the virtual adapter, the control component obtains configuration information of the activated virtual adapter from the physical adapter, the configuration information generated based on the activating. The control component ascertains a configuration of the activated virtual adapter based on the obtained configuration information.

Abstract: A data storage drive that includes a data storage medium and drive control circuit communicatively coupled to the data storage medium. The data storage drive also includes embedded applet management circuitry that executes an application, installed in the data storage drive as one or more key-value objects, within a controlled environment of the data storage drive.

Abstract: A method and system are described that support proper operation of RTSA by providing it the required real-time resources at the right time. The method and system include three elements: Isolation, Independence, and Timing limited/non-blocking interfaces. Isolation defines to the host operating system and any other element involved that the CPU core or few CPU cores that are used to run the RTSA should be isolated, be in full ownership of the RTSA, and cannot serve any general purpose task of the platform. Independence is an attribute or characteristic that the code used in the RTSA preferably does not use any external service/device unless the service/device has a clear known deterministic real-time characteristic. Timing limited/non-blocking interfaces is an attribute or characteristic that, in cases where interfaces between the RTSA to other software program is needed, the interface should preferably be limited in effecting the timing operation of the RTSA.

Abstract: A method. A JavaScript (JS) object is instantiated. The instantiated JS object processes application programming interface (API) requests received from mobile devices. The instantiation of the JS object is based on a JS model including (1) a JS file that stores a description of a behavior of the JS object and (2) a JS object notation (JSON) file that stores a description of properties of the JS object. The JSON file includes at least one validation rule to reject a data tuple unless the data tuple meets a required constraint specified in the validation rule. A data abstracter is an interface between the JS object and a set of data storages from which the JS object retrieves data while processing at least two of the API requests. The data abstractor is connected with the set of data storages by implementing a data exchange logic for the set of data storages.

Abstract: A method for a secondary host to support continuous availability for an application on a primary virtual machine on a primary host is disclosed. The method includes the secondary host creating a secondary virtual machine that is identical to the primary virtual machine, the secondary host receiving activities of the primary virtual machine from the primary host, the secondary host buffering the activities, and the secondary host determining if the buffered activities are safe to replay. When the buffered activities are determined to be safe to replay, the method includes the secondary host replaying the buffered activities to the secondary virtual machine. When the buffered activities are determined to be unsafe to replay, the method includes the secondary host discarding the buffered activities and setting the secondary virtual machine as a new primary virtual machine to take over a service provided by the application.

Abstract: Provided is a computer-procurement-timing predicting device to properly predict a timing at which an additional computer on which a VM is to be placed is required, by considering a demand fluctuation, re-placement of a computational period, and a load fluctuation of the VM.

Abstract: A setting method for a server apparatus includes identifying, from virtual machine groups arranged in plural stages that realize communication functions, a termination type virtual machine that terminates traffics, extracting, for each of virtual machines that relay traffics to the termination type virtual machine, an auxiliary communication path including an output destination virtual machine to which a traffic addressed to the termination type virtual machine is output, and setting, for each of the virtual machines that relay traffics to the termination type virtual machine, the extracted auxiliary communication path.

Abstract: A computer-implemented method for cache memory management includes receiving a coherence request message from a requesting processor. The method can further include determining a request type responsive to detecting the transactional conflict. The request type is indicative of whether the coherence request is a prefetch request. The method further includes detecting, with a conflict detecting engine, a transactional conflict with the coherence request message. The method further includes sending, with the adaptive prefetch throttling engine, a negative acknowledgement to the requesting processor responsive to a determination that the coherence request is a prefetch request.

Abstract: Provided is an accelerator control apparatus including a data management table storing a name assigned to data and an identifier for an accelerator that stores the data on a local memory by associating the name and the identifier; a data management unit that is configured to determine, when receiving a first process that accepts data assigned with the name as input data, the accelerator that stores the data on the local memory, by referring to the data management table; and a task processing unit that is configured to control the accelerator being determined by data management unit to execute the first process.

Abstract: In an example embodiment, a computer-implemented method is disclosed that computes, using one or more processors, a path slack value for each path of a set of paths of a functional computing model. Each path of the set of paths comprises a set of tasks and the path slack value of each path reflects a difference between a deadline and a latency of the path. The method further determines a priority of each task of the set of tasks of each path based on the path slack value of the path, and allocates, using the one or more processors and based on the priority of each task, the tasks of each of the paths of the set to corresponding computing units from a set of computing units of an architectural platform.

Abstract: For a task that has been partially executed, a residual complexity index is computed, the task being of a complexity that cannot be ascertained prior to executing the task. An evaluation is made whether the residual complexity index exceeds a cost of a resource that should be considered for allocation to the task. When the evaluation is affirmative, a priority of the task is established relative to a second task. The resource is scheduled to perform the task according to a timing, the timing being determined using the cost of the resource. The resource is allocated to the task according to the timing.

Abstract: An example method for migrating a live operating system from a first computing device to a second computing device is provided. The example method comprises (a) providing register values of a processor of a first computing device to a second computing device which is in communication with the first computing device; (b) providing contents of a dynamic random access memory, DRAM, of the first computing device to the second computing device; (c) storing the register values in a protected memory of the second computing device, wherein the protected memory is separate from a memory used by the second computing device during normal operation of the second computing device; (d) storing the contents of the DRAM of the first computing device in a DRAM of the second computing device; and (e) loading the register values from the protected memory to registers of a processor of the second computing device.

Abstract: Operation of a multi-slice processor implementing instruction fusion, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a first instruction that has an operand dependency on a second instruction in the set of instructions; and responsive to the first instruction having an operand dependency on the second instruction: issuing the first instruction and the second instruction to execute in parallel on the particular set of execution slices configured with fusion logic between execution slices that removes the operand dependency between the first instruction and the second instruction.

Abstract: An information processing apparatus includes: a reconfiguration device which can change a circuit configuration through a dynamic partial reconfiguration; and a controller which controls a circuit arrangement in the reconfiguration device, in which when a processing circuit related to a new task is arranged in the reconfiguration device, the controller determines a circuit assignment of a processing circuit related to an existing task in execution and the processing circuit related to the new task with respect to an area as a result of combining an area used for the processing circuit related to the existing task in execution and a space area, based on a predicted end time of the processing of the respective tasks, and arranges the processing circuits related to the respective tasks in the reconfiguration device in accordance with the determined circuit assignment.

Abstract: In one embodiment, performance-based multi-mode task dispatching for high temperature avoidance in accordance with the present description, includes selecting processor cores as available to receive a dispatched task. Tasks are dispatched to a set of available processor cores for processing in a performance-based dispatching mode. If monitored temperature rises above a threshold temperature value, task dispatching logic switches to a thermal-based dispatching mode. If a monitored temperature falls below another threshold temperature value, dispatching logic switches back to the performance-based dispatching mode. If a monitored temperature of an individual processor core rises above a threshold temperature value, the processor core is redesignated as unavailable to receive a dispatched task. If the temperature of an individual processor core falls below another threshold temperature value, the processor core is redesignated as available to receive a dispatched task.

Abstract: Methods, systems, and computer program products for leveraging shared work to enhance job performance across analytics platforms are provided herein. A computer-implemented method includes comparing one or more task characteristics of multiple tasks across multiple jobs to be executed within a given environment, wherein each of the multiple jobs comprises one or more tasks; identifying, based on said comparing, one or more of the multiple tasks that can be shared by two or more of the multiple jobs; scheduling the multiple jobs for execution within the given environment, wherein said scheduling is based on (i) the identified tasks that can be shared by two or more of the multiple jobs, and (ii) one or more performance metrics of the given environment; and allocating resources to the multiple jobs based on said scheduling.

Abstract: Generic Concurrency Restriction (GCR) may divide a set of threads waiting to acquire a lock into two sets: an active set currently able to contend for the lock, and a passive set waiting for an opportunity to join the active set and contend for the lock. The number of threads in the active set may be limited to a predefined maximum or even a single thread. Generic Concurrency Restriction may be implemented as a wrapper around an existing lock implementation. Generic Concurrency Restriction may, in some embodiments, be unfair (e.g., to some threads) over the short term, but may improve the overall throughput of the underlying multithreaded application via passivation of a portion of the waiting threads.

Abstract: Software development data indicative of a development activity is accessed. A component parameter of a component of a software development platform is set, in which the component parameter is based upon, at least in part, an anticipated component workload associated with the development actively. At least one system resource is allocated for the component of the software development platform based upon, at least in part, the component parameter.

Abstract: Software development data indicative of a development activity is accessed. A component parameter of a component of a software development platform is set, in which the component parameter is based upon, at least in part, an anticipated component workload associated with the development actively. At least one system resource is allocated for the component of the software development platform based upon, at least in part, the component parameter.

Abstract: A method, a computer program product, and a computer system for controlling dispatching work tasks in a multi-tier storage environment. A computer system receives storage demands of work tasks. The computer system determines placement and migration policies for data in storage tiers in a storage system. The computer system prepares the storage tiers for meeting the storage demands of work tasks, based on the placement and migration policies. The computer system determines a state of preparation of the storage tiers for meeting the storage demands of work tasks. The computer system determines a list including work tasks that can proceed and work tasks that cannot proceed, based on the state of the preparation. The computer system modifies a schedule of the work tasks, based on the list.

Abstract: A method for controlling dispatching work tasks in a multi-tier storage environment. A computer system receives storage demands of work tasks. The computer system determines placement and migration policies for data in storage tiers in a storage system. The computer system prepares the storage tiers for meeting the storage demands of work tasks, based on the placement and migration policies. The computer system determines a state of preparation of the storage tiers for meeting the storage demands of work tasks. The computer system determines a list including work tasks that can proceed and work tasks that cannot proceed, based on the state of the preparation. The computer system modifies a schedule of the work tasks, based on the list.

Abstract: A GPU resource allocation method and system relate to the field of computer technologies. A global logic controller determines a to-be-distributed kernel program in a kernel status register table; searches an SM status register table for an SM capable of running at least one entire thread block; when the SM capable of running at least one entire block is not found, searches the SM status register table for a first SM, where the first SM is an SM capable of running at least one thread warp; and when the first SM is found, distributes a block from the to-be-distributed kernel program to the first SM; or when the first SM is not found, searches for a second SM and then distributes the block from the to-be-distributed kernel program to the second SM. The GPU resource allocation method and system are applicable to GPU resource allocation.

Abstract: An apparatus stores plural pieces of reference data selected based on operation data input from a host OS executed by an information processing device. The apparatus selects one or more pieces of selection reference data from the plural pieces of reference data, based on a plurality of correlation coefficients which are calculated upon receiving a predictive demand and which respectively indicate correlations between predictive target reference data indicating reference data to be predicted and other reference data. The apparatus calculates predictive values of the predictive target reference data, based on the selected one or more pieces of selection reference data, and controls the plurality of calculation resources for the information processing device, based on the predictive values of the predictive target reference data and a predetermined reference value.