Abstract: A TH terminal receives an analog control voltage VTH which indicates a rotational speed. With a first platform, a capacitor and a discharging resistor are connected in parallel between an OSC terminal and the ground. A charging resistor and a first switch are arranged in series between the OSC terminal and a reference voltage line via which a stabilized voltage is supplied. When an oscillator voltage VOSC that occurs at the OSC terminal reaches an upper-side threshold VH, a switching circuit turns off the first switch. When the oscillator voltage VOSC falls to a lower-side threshold value VL, the switching circuit turns on the first switch. The oscillator voltage VOSC is compared with the voltage at the TH terminal, so as to generate a pulse-modulated control pulse S3.

Abstract: An electrical switch, particularly for an electrical appliance having an electric motor. The switch has two electrical supply connections for the supply voltage, particularly for a rechargeable battery, and two electrical motor connections for the supply of voltage to the electric motor. Furthermore, the switch has a control electronics unit, such as a microprocessor, a microcontroller or the like, for executing control processes in the electrical appliance, wherein particularly the control electronics unit operates by means of a piece of software. The switch can also be connected with a data line for communication between the control electronics unit and an external device, wherein particularly one of the electrical motor connections is used as an interface for the data line. Furthermore, the invention relates to an appropriate method for communication by an electrical switch with an external device.

Abstract: Systems and methods for disposing and supporting a solar panel array are disclosed. The embodiments comprise various combinations of cables, support columns, and pod constructions in which to support solar panels. Special installations of the system can include systems mounted over structures such as parking lots, roads, aqueducts, and other bodies of water. Simplified support systems with a minimum number of structural elements can be used to create effective support for solar panel arrays of varying size and shapes. These simplified systems minimize material requirements and labor for installation of the systems.

Abstract: A mounting apparatus to secure a pair of solar panel rails to a flat tile roof and minimize penetrations or damage to the roof's rafter is provided. The mounting apparatus includes a lower hook assembly with a plurality of arm members continuously connected together, the plurality of arm members having a first end coupled to the rafter of the flat tile roof and a second end, and an upper arm assembly coupled to the second end of the plurality of arms of the lower hook assembly, the upper arm assembly having a generally U-shaped member comprising a first symmetric half member and a second symmetric half member, each symmetric half member having a slot to receive a fastener that secures one of the pair of solar panel rails thereto, thereby permitting the mounting apparatus to support the pair of solar panel rails above the flat tile roof.

Abstract: This invention relates to a roofing panel for interconnection with one or more additional roofing panels. The roofing panel comprises a PV cell coupled to an inverter, and wireless (or optionally wired) power transfer circuitry for transmitting power to another roofing panel and/or the AC grid and/or to an AC inverter, and/or for receiving power from another roofing panel.

Abstract: A linear drive apparatus is provided. The linear drive apparatus may include an outer tube, a sealing end cap provided at the end of the outer tube, a screw provided in the outer tube, a drive nut provided on the screw in a threaded fit, an extension rod provided between the outer tube and the screw, a sealing assembly provided between the extension rod and the sealing end cap, and a waterproof and oil-proof ventilation stopper provided on the outer tube. One end of the screw may be connected to a drive mechanism. One end of the extension rod may be connected to the drive nut. The other end of the extension rod may pass through the sealing end cap.

Abstract: A rigidly mountable solar panel includes lenses supported above a movable panel to focus sunlight onto photovoltaic material carried on the movable panel. Flexible supports space the movable panel at the focal points of the lenses, and a servo-mechanism enables movement of the movable panel to adjust position as the focal point moves with the sun. A light detector on the movable panel, sensing movement of the focal point signals the servo-mechanism to adjust the position of the movable panel automatically, thereby tracking the sun's movement. Concentrating sunlight on photovoltaic material selected to have higher conversion efficiency increases output. Segmenting the photovoltaic material so the output of the segments can be combined in a series-parallel relationship and using mirrors on the ends of the movable panel to reflect sunlight onto the segments allows electricity that is generated by the photovoltaic material to be more uniform during daylight.

Abstract: A solar cell module according to the embodiment includes a support substrate having a single hole at a peripheral region of the support substrate; solar cells at an upper portion of the support substrate; a bus bar electrically connected to the solar cells; and a junction box connected to the bus bar, wherein the junction box includes an insertion part partially inserted in the single hole.

Abstract: A solar battery module according to an embodiment comprises: a support substrate; a plurality of solar battery cells arranged on the support substrate; and at least one bus bar electrically connected with the solar battery cells, wherein the support substrate includes at least two cut regions formed at corner regions thereof and the bus bar is extended to the rear side of the supporting substrate from the front side of the supporting substrate through the cut regions.

Abstract: A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. The input is coupled to the control terminal of at least one transistor of the first pair. The amplitude detector includes a first node providing a voltage indicative of the amplitude voltage. The first node is in series with each of the first pair of transistors. The circuit includes a compensation circuit. The compensation circuit includes a second pair of transistors configured in parallel and a second node. The second node is coupled in series with each transistor of the second pair. The circuit includes an amplifier including a first amplifier input coupled to the first node and a second amplifier input coupled to the second node.

Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

Abstract: A method for controlling a semiconductor circuit, including forming an inductor and a capacitor on a substrate, which are inductively coupled to one another. The inductor has an inductance value while the capacitor has a capacitance value. The inductor and capacitor make up an oscillator circuit with two terminals. Eddy currents are generated through the capacitor when an operating current flows along the inductor. These eddy currents influence, by inductive coupling, the inductance value and performance of the oscillator circuit, thus simultaneously tuning the inductance and capacitance of the oscillator circuit.

Abstract: A varainductor including a signal line disposed over a substrate. The varainductor further includes a first ground plane over the substrate, the first ground plane disposed on a first side of the signal line, and a second ground plane over the substrate, the second ground plane disposed on a second side of the signal line opposite the first side of the signal line. The varainductor further includes a first floating plane over the substrate, the first floating plane disposed between the first ground plane and the signal line, and a second floating plane over the substrate, the second floating plane disposed between the second ground plane and the signal line. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the first ground plane to the first floating plane, and to selectively connect the second ground plane to the second floating plane.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: An amplifier circuitry for an envelope modulator including: a linear amplifier configured to receive an input representing an envelope of a signal to be amplified; a charge storage device coupled to the amplifier for providing an amplified envelope signal for driving a load, the amplifier and charge storage device configured to receive a supply voltage; wherein the amplifier circuitry is configured such that responsive to the voltage of the input envelope signal reaching or exceeding a defined threshold value, an input voltage based on the voltage of the received envelope signal is provided to the amplifier to enable the charge storage device to supply a charge above the supply voltage such that the output voltage of the load driven by the amplifier circuitry is increased above the supply voltage. An envelope modulator incorporates the modulator and a method for amplifying an envelope signal utilizes the modulator.

Abstract: Systems and method related to switchable output stages in power amplifiers. In some embodiments, a power amplifier (PA) circuit can include a driver stage configured to amplify a radio-frequency (RF) signal. The PA circuit can further include a plurality of output stages, with each output stage being configured to be capable of further amplification the RF signal. The PA circuit can further include a switch implemented to route the amplified RF signal from the driver stage to a selected one of the plurality of output stages, such that the selected output stage further amplifies the amplified RF signal.

Abstract: An amplifier arrangement comprises N amplifier stages, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a first cascade of quarter wavelength transmission line segments coupled to receive a first set of amplifier stages, and at least a second cascade of quarter wavelength transmission line segments coupled to receive a second set of amplifier stages. The first cascade and second cascade are connected to a common node, for example in parallel to an output node, or in parallel to an intermediate node.

Abstract: A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.

Abstract: A method for suppressing POP noise in an audio operation amplifier, comprising: connecting a first resistor and a second resistor in series at an output stage of the audio operation amplifier by turning on a first switch and a second switch; generating, with a ramp generator, a ramp voltage after an audio signal is input into the audio operation amplifier, wherein the ramp voltage varies from zero to a first value; generating, with an voltage generator, a second voltage, wherein a third switch is turned on and a fourth switch is turned off when the ramp voltage reaches the second value; short-circuiting the first and second resistors by turning off the first and second switches; and outputting, with the audio operation amplifier, an amplified audio signal.

Abstract: Frequency characteristics of a peaking stage can vary depending on variations in the process used to fabricate the peaking stage. For example, depending on the batch of wafers and where on a wafer the peaking stage is formed, the capacitors and resistors may have different values, thereby changing the frequency characteristics of the peaking stage. The embodiments herein describe a peaking stage that is invariant of the process variation. That is, one or more of the frequency characteristics of the peaking stages do not vary as the values of a capacitor or resistor change. As such, peaking stages formed in different process corners on the wafer have the same frequency characteristics, and thus, function in a similar manner.

Abstract: At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.

Abstract: Circuits for low noise amplifiers with interferer reflecting loops are provided. In some embodiments, circuits for a low noise amplifier with an interferer reflecting loop are provided, the circuits comprising: a low noise amplifier (LNA) having an input and an output; a buffer having an input coupled to the output of the LNA and an output; and notch filter having an input coupled to the output of the buffer and an output coupled to the input of the LNA.

Abstract: RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The first RF LNA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal.

Abstract: A switching amplifier provided, at a minimum, with: a first input transistor into which one of two input signals that operate in a complementary manner is input; a first cascode transistor cascade-connected between the first input transistor and a power supply; a second input transistor into which the other of the two input signals is input; and a second cascode transistor cascade-connected between the second input transistor and the first input transistor; the switching amplifier extracting an output signal, a connection point between the first input transistor and the second cascode transistor being used as an output terminal; wherein a first potential limiting circuit and a second potential limiting circuit for limiting the potential fluctuation range are respectively connected to the input terminal of the first cascode transistor and the input terminal of the second cascode transistor.

Abstract: A method includes, in at least one aspect, receiving, at both an input node of a first input stage and in input node of a second input stage, a single-ended voltage signal; providing, by at least one of the first input stage or the second input stage, inductive degeneration to the single-ended voltage signal; converting an output from the first input stage into a first single-ended current signal; converting an output from the second input stage into a second single-ended current signal; and outputting, by an output stage, a differential output including the first single-ended current signal and the second single-ended current signal.

Abstract: An amplifier includes a first input branch and a second input branch that form a differential input stage and a current mirror connected to the differential input. The current mirror is governed as a function of a common mode feedback signal applied to a control node of the current mirror. A second, amplification, stage includes a branch flowing through which is a current, which is a function of the current that flows in the first input branch, and is in turn connected to a first output branch. A capacitive element is coupled between the control node and the second stage. The circuit is symmetrical with respect to the input stage.

Abstract: A multiport amplifier MPA is provided with an N-input input network, INET, an N-output output network, ONET, and N amplifiers interposed between the INET and the ONET, the MPA comprising N wanted signal paths and N.(N?1) null signal paths wherein N is divisible by 2, half of the N amplifier paths comprise a signal inversion with respect to the other half of the N amplifier paths, the INET and the ONET each comprise one or more quadrature hybrid couplers, QHC, wherein a pair of amplifier paths is arranged between the output of a first QHC in the INET and the input of a second QHC at the ONET, and each signal inversion is arranged in one of the amplifier paths of each pair of amplifier paths such that the ideal amplitude gain of at least one of the N.(N?i) null signal paths is zero.

Abstract: A differential amplification circuit includes: a first transistor and a second transistor of a differential pair; first and second loads; current sources; and a resistor circuit, wherein the resistor circuit includes: a coarse adjustment part and a fine adjustment part, one of the coarse adjustment part and the fine adjustment part includes a first lateral adjustment part and a second lateral adjustment part which have the same configuration, the first lateral adjustment part and the second lateral adjustment part are connected symmetrically to both sides of a central adjustment part, and the central adjustment part has a circuit configuration symmetrical with respect to two connection nodes with the first lateral adjustment part and the second lateral adjustment part.

Abstract: A power amplification module includes a first input terminal that receives a first transmit signal in a first frequency band, a second input terminal that receives a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band, a first amplification circuit that receives and amplifies the first transmit signal to produce a first amplified signal and outputs the first amplified signal, a second amplification circuit that receives and amplifies the second transmit signal to produce a second amplified signal and outputs the second amplified signal, a third amplification circuit that receives and amplifies the first or second amplified signal to produce an output signal and outputs the output signal, and an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a receive frequency band component of the second frequency band.

Abstract: Disclosed is an audio output control method and an electronic device supporting the same. The audio output control method includes determining an output of an audio processing unit decoding an audio source signal, and controlling generating of a reference signal to be supplied to an audio output unit in response to an output of the audio processing unit.

Abstract: The invention relates to the measurement and control of the perceived sound loudness and/or the perceived spectral balance of an audio signal. An audio signal is modified in response to calculations performed at least in part in the perceptual (psychoacoustic) loudness domain. The invention is useful, for example, in one or more of: loudness-compensating volume control, automatic gain control, dynamic range control (including, for example, limiters, compressors, expanders, etc.), dynamic equalization, and compensating for background noise interference in an audio playback environment. The invention includes not only methods but also corresponding computer programs and apparatus.

Abstract: Various aspects of this disclosure describe setting an audio compressor threshold using averaged audio measurements. Examples include calculating one or more average values of amplitude values of an audio file, and setting a threshold used in the audio compressor based on the calculated thresholds. Samples of the audio file with amplitude values above the threshold are attenuated, while samples of the audio file with amplitude values below the threshold are not attenuated. The threshold can be set equal to a calculated average value, or from a function of one or more calculated average values. Different audio channels comprising the audio file can be processed to set a respective compressor threshold for each audio channel.

Abstract: A matching module includes an input terminal connected to an input node, a variable load capacitor, and a plurality of RF signal delivery branches. The input terminal is connected to receive RF signals from one or more RF generators. The load capacitor is connected between the input node and a reference ground potential. Each of the plurality of RF signal delivery branches has a respective ingress terminal connected to the input node and a respective egress terminal connected to a respective one of a plurality of output terminals. Each of the plurality of output terminals of the matching module is connected to deliver RF signals to a different one of a plurality of plasma processing stations/chambers. Each of the plurality of RF signal delivery branches includes a corresponding inductor and a corresponding variable tuning capacitor electrically connected in a serial manner between its ingress terminal and its egress terminal.

Abstract: An efficiency variable antenna is provided, the efficiency variable antenna including: a feeding portion; a first grounding portion; a second grounding portion; a first switching element configured to turn on or off the feeding portion and the first grounding portion; and a second switching element configured to turn on or off the feeding portion and the second grounding portion.

Abstract: A common mode filter includes a coil part in which a plurality of insulating layers having coils formed on one surfaces thereof and containing fillers are stacked; a first cover part disposed beneath the coil part; and a second cover part disposed on the coil part, wherein surface reforming layers improving close adhesion between the insulating layers are formed on at least one surfaces of the insulating layers.

Abstract: A radio frequency filter and a manufacturing method thereof are provided. A radio frequency filter includes bulk acoustic wave resonators (BAWRs), the BAWRs including first BAWRs connected in series, second BAWRs connected in parallel, or a combination thereof.

Abstract: A resonator including a piezoelectric plate and an interdigital electrode is provided. A ratio between a thickness of the plate and a pitch of the interdigital electrode may be from about 0.5 to about 1.5. A radiation detector including a resonator and an absorber layer capable of absorbing at least one of infrared and terahertz radiation is provided. A resonator including a piezoelectric plate and a two-dimensional electrically conductive material is provided.

Abstract: Methods and apparatus for anchoring resonators, such as microelectromechanical systems (MEMS) resonators. A resonator may include a substrate, a mechanical resonating structure, and at least one anchor. The mechanical resonating structure may be configured to resonate in a resonance mode of vibration at a frequency. The anchor may couple the mechanical resonating structure to the substrate. The anchor may be configured to exhibit an acoustic bandgap at the frequency of the resonance mode of vibration of the mechanical resonating structure. The anchor may be oriented in a direction substantially parallel to a direction of propagation of the resonance mode of vibration of the mechanical resonating structure.

Abstract: A cascaded integrator-comb filter (CIC) that includes a differentiator, a rate changer, an integrator, and a multiplier. The differentiator is configured to differentiate an input signal to produce a differentiated input signal. The rate changer is coupled to the differentiator and is configured to interpolate the differentiated input signal based on an interpolation rate to produce an upsample signal. The integrator is coupled to the rate changer and is configured to integrate the upsample signal to produce an output signal. The multiplier is coupled to the differentiator, rate changer, and integrator and is configured to increase the output signal amplitude based on the interpolation rate.

Abstract: An apparatus includes a plurality of delay elements, a plurality of multipliers and an accumulator to form a biquad stage; and a precision logic circuit. The biquad stage includes feedback paths; at least one feedback path has an adjustable bit precision; and the precision logic is adapted to regulate the bit precision of the feedback path(s) based at least in part on at least one parameter that is associated with the biquad stage.

Abstract: A timing device that includes an OTP NVM, a first periodic signal generator operable to generate a periodic signal having a first frequency, a second periodic signal generator operable to generate a periodic signal having a frequency that is lower than the first frequency, and selection logic. In a first operating mode, the selection logic is configured to output the first periodic signal at an output terminal as long as a crystal clock feedback signal is received at the input terminal and output the second periodic signal when the crystal clock feedback signal is not received at the input terminal. In a second operating mode, the selection logic is configured to output the first periodic signal as long as a output enable signal is received at the input terminal and not provide any output at the output terminal when the output enable signal is not received at the input terminal.

Abstract: Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal.

Abstract: A sensing circuit configured to activate a controller is disclosed. The circuit comprises a first transistor configured to output an activation signal to the controller and a plurality of switches in connection with a base of the transistor. Each of the switches is connected to an identifying resistor. A first output node and a second output node are in communication with the base of the transistor and each of the switches. The first output node and the second output node are separated across an additional identifying resistor. The first output node and the second output node are configured to output a characteristic voltage corresponding a ratio of each of the identifying resistors in response to an input received by one or more of the plurality of switches.

Abstract: A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.

Abstract: A power on reset circuit applied to a gate driver of a display apparatus is disclosed. The power on reset circuit is coupled between an operating voltage and a ground terminal. The power on reset circuit includes an output terminal, a first transistor, a second transistor, a resistor, and a buffer circuit. The first transistor is coupled between the operating voltage and a first node. A gate of first transistor is coupled to the first node. The second transistor is coupled between the operating voltage and the first node. A gate of second transistor is coupled to the ground terminal. The resistor is coupled between the first node and ground terminal. The buffer circuit is coupled between the first node and output terminal and outputs a reset signal through the output terminal. A second threshold voltage of second transistor is larger than a first threshold voltage of first transistor.

Abstract: A gate drive circuit includes first and second transistors for turning on and off semiconductor switching devices. The circuit includes a DC power supply for driving the first and second transistors. The gate drive circuit further includes a third transistor, a fourth transistor, and a DC power supply being a power supply for the third and fourth transistors with a voltage value lower than the voltage value of the DC power supply, thereby making lower the impedance of the path of a current flowing from the DC power supply to the gates of the switching devices through the third transistor than the impedance of the path of a current flowing from the DC power supply to the gates of the switching devices through the first transistor.

Abstract: A hybrid switch apparatus includes a gate drive circuit producing a gate drive signal, a GaN high electron mobility transistor (HEMT) having a first gate, a first drain, and a first source. A silicon (Si) MOSFET has a second gate, a second drain, and a second source. The GaN HEMT and the Si MOSFET are connected in a parallel arrangement so that (i) the first drain and the second drain are electrically connected and (ii) the first source and the second source are electrically connected. The second gate is connected to the gate drive circuit output to receive the gate drive signal. A delay block has an input connected to the gate drive circuit output and an delay block output is configured to produce a delayed gate drive signal for driving the GaN HEMT.

Abstract: An illustrative integrated circuit configured for galvanically isolated signaling includes a receiver having: a detector module coupled to receive a differential signal from terminals of a transformer secondary, the detector module responsively presenting an impedance that varies based on a magnitude of the differential signal; a biasing module that converts the detector module impedance to a response signal; and a comparator module that compares the response signal to a reference signal to obtain a detection signal indicative of oscillation in the differential signal.

Abstract: A capacitive sensor device for approach and/or contact detection can be coupled with an electric circuit (10) and has a sensor electronics (20) and a device for potential separation (30), which with the sensor electronics (20) is coupled and by which the capacitive sensor device can be coupled with the electric circuit (10). In a method for operating a capacitive sensor device which has a sensor electronics, the sensor electronics can be coupled with an electric circuit and the sensor electronics is coupled with the electric circuit in a separable way with respect to the potential.

Abstract: A touch- and/or proximity-sensitive input device has a cover plate with a control section. The side of the control section facing a user forms a control field for the user and a side facing away from the user forms a sensor plane. A sensor film has at least one capacitive sensor field within the control section of the cover plate. A carrier plate has at least one electric contact field. The cover plate has a contacting section next to the control section and the side facing away from the user forms a contacting plane. The sensor film has an electric contact field next to the sensor field. At least one electric contact element connects the electric contact field of the sensor film electrically conductively to the at least one electric contact field of the carrier plate.