Abstract: A processing device generates a live snapshot of a virtual disk image attached to a virtual machine, wherein generating the live snapshot comprises converting an existing read-write volume to a read-only volume. The processing device generates, from the read-only volume, a temporary snapshot of the virtual disk image, the temporary snapshot comprising a temporary read-write volume. The processing device attaches the temporary snapshot of the virtual disk image to a backup component and causes at least one of the backup component or a backup service to backup the virtual disk image from the attached temporary snapshot.

Abstract: Disclosed herein are system, method, and computer program product embodiments for replicating a database transaction to a replica table. An embodiment operates by receiving a replication log entry and an associated transaction commit log entry for a database transaction to be replayed to a row at a replica table. A row-ID value of the replication log entry is compared to a row-ID column value of the row at the replica table. The replication log entry is then replayed at a parallel log replayer based on the comparison. The database transaction is then committed to the replica table by replaying the associated transaction commit log entry at a transaction log replayer.

Abstract: The disclosed computer-implemented method for repairing corrupted data segments may include (1) detecting a corrupted data segment in a backup stored in a data storage system, (2) identifying at least one additional backup stored in the data storage system that exceeds a predetermined threshold for probability of comprising an uncorrupted version of the corrupted data segment, (3) matching at least a portion of a data segment in the additional backup with at least a portion of a data segment adjacent to the corrupted data segment in the backup, (4) locating, at least in part by examining data adjacent to the matched data segment in the additional backup, the uncorrupted version of the corrupted data segment, and (5) repairing the corrupted data segment in the backup by using the uncorrupted version of the corrupted data segment located in the additional backup. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer-implemented method for shipping I/O operations to prevent replication failure may include 1) attempting to perform an I/O operation in a system configured to replicate data from a data cluster to another data cluster, 2) detecting a failure in at least part of the attempt to perform the I/O operation that threatens to fail the system's replication of data from the data cluster to the other data cluster, and, in response to detecting the failure, 3) shipping the I/O operation from a node originally responsible for servicing the I/O operation to another node to complete the I/O operation without failing the system's replication of data from the data cluster to the other data cluster. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system for providing data communication includes a computer test tool configured to perform one or more diagnostic tests on a computer network and a cloud-based server. The cloud-based server is configured to couple to the communication network so as to exchange data with the computer test tool when the computer test tool is coupled to the communication network. The cloud-based server tracks usage of the computer test tool and, based on the tracked usage, transmits a message to the computer test tool that temporarily enables the computer test tool based on a predetermined condition.

Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.

Abstract: A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock signal, a second input terminal coupled to the memory device for receiving the notification signal, a select terminal for receiving a selection signal, and an output terminal for outputting a memory clock signal to the memory device. The memory clock signal is one of the external clock signal and the notification signal. The built-in self-test circuit is for outputting a control signal required by the memory device to perform the read operation or the write operation and check whether the memory device functions normally.

Abstract: A test system that enables real-time interactive debugging of a device under test (DUT) using native customer code. A translation module may format, in real time, debug commands, corresponding to a user input, into a format recognizable by instruments in a tester. The user input may be a test program or test instructions written in a high-level programming language. The translation module may translate the user's debug commands into lower-level test instrument commands, based on which the tester may apply control signals to a processor in the DUT to test subsystems of the DUT. A result of the test may be provided to the translation module, which may, in real time, format another debug command, or provide an indication of the result to the user. The translation module may thus enable a user to step-through and modify native customer code in an interactive manner to debug a DUT.

Abstract: An embodiment provides a method, including: in a system, determining a set of processes which run at system boot; monitoring the processes at system boot for system resource utilization; categorizing processes of the set of processes based on said monitoring; and changing a start time during boot of at least one process based on said categorizing. Other aspects are described and claimed.

Abstract: Technology for detecting processor usage of a physical host hosting computing instances is provided. In one example, a method may include identifying a location of a hardware register of a physical host containing data in a model specific register. The physical host hosts a plurality of computing instances using a hypervisor. The method may include determining power consumption by a processor of the physical host for the computing instances from the data. An upper level of acceptable processor power consumption may be identified. Processor usage may be determined based on the power consumption determined and the upper level of acceptable processor power consumption. The processor usage may be provided as data through the hypervisor.

Abstract: [Problem] To provide a server monitoring device capable of grasping the state of a server more rapidly than conventional ones, and a server monitoring system. [Solution] This server monitoring device has a configuration in which a plurality of optical fibers are optically coupled to a plurality of light-emitting elements each showing the operating state of a server by a lighting mode, and the end surfaces of the plurality of optical fibers on the opposite side to the light-emitting elements are secured in a predetermined arrangement. An image of a light emission pattern of the end surfaces of the optical fibers is captured by a camera, and the image is transmitted to a monitoring person.

Abstract: Apparatus and computer program products implement embodiments of the present invention that enable a portable computing device such as a smartphone or a tablet computer, to capture one or more codes for one or more corresponding components positioned in proximity to the portable computing device, and to convey the one or more codes to a management system. Upon receiving the one or more codes, the management system can be configured to convey, to the portable computing device, an identification and a status of each of the one or more components. The portable computing device can then present the status of the one or more components on a display.

Abstract: A dynamic library profiling method and a dynamic library profiling system including writing a first break point instruction at a start address of a dynamic library function, recording a first event count value that is a process performance management unit (PMU) count when a target process executes the first break point instruction, writing a second break point instruction to a return address of the dynamic library function, and calculating a PMU count generated in a processor core while the dynamic library function is executed, by comparing the recorded first event count value with a second event count value that is a process PMU count when the target process executes the second break point instruction, wherein the process PMU count is a cumulative value of PMU counts generated in the processor core while the target process is executed.

Abstract: Systems and methods for providing a debugging interface for inserted elements in a resource are provided. One method includes detecting a trigger for a request to provide a debugging interface for a webpage, the webpage including a content interface configured to display third party content items. The method further includes transmitting the request for the debugging interface to a remote device, and receiving a script representing the debugging interface from the remote device. The method further includes inserting the debugging interface into the webpage by injecting the script into data of the webpage during loading of the webpage. The method further includes detecting a characteristic of at least one of the webpage, the content interface, or the remote device; and generating debugging information using the detected characteristic. The method further includes providing the debugging information in the debugging interface.

Abstract: According to an embodiment of the present invention, an artifact is received, and unstructured content of the artifact is parsed and analyzed to identify data for one or more of missing structured content of the artifact and inaccurate structured content of the artifact. The identified data is then added to the artifact. Embodiments of the present invention can be used, for example, to provide data for missing and inaccurate structured content in artifacts of Application Lifecycle Management (ALM) frameworks, and improve accuracy of structured information that used to run queries and create reports.

Abstract: Inserting memory snapshots during indexing of a trace for responsive trace replay. A method includes identifying a plurality of points of interest in execution of executable entit(ies) whose execution is traced in first data stream(s). Based on the first data stream(s), a traced section of execution of the executable entit(ies) preceding each point of interest is replayed. During replay of each traced section of execution, memory addresses that are accessed by the executable entit(ies) during replay of the section, and a most recent value encountered at each memory address, is tracked. Second data stream(s) are recorded, which includes recording a plurality of memory snapshots in connection with the plurality of points of interest into the second data stream(s). Each memory snapshot summarizes memory addresses and values encountered in at least one section of execution preceding each point of interest.

Abstract: An agent installed on application server having a WSGI web application dynamically instruments that web application. The agent may modify the application via instrumentation such that it can be monitored without specific details of the WSGI application framework. A configuration file may be modified upon detecting a call to the application configuration file through a gateway interface that receives the call. After modifying the configuration file, the modified configuration file is executed in response to the call. Additionally, for subsequent calls to that particular web application, the WSGI gateway will call the modified WSGI configuration file for execution instead of the original WSGI file.

Abstract: A computer device may include logic configured to provide a centralized library for descriptive programming and other types of object descriptions to a testing script engine. The descriptive programming library may store test object descriptions for test objects associated with an application under testing. The logic may be further configured to provide a unification layer over all the object description types and to provide inheritance among the objects at the unification layer. The logic may be further configured to store a test object description, associated with a test object, in the descriptive programming library; identify a reference to the test object in a descriptive programming statement associated with the testing script engine; access the stored test object description in the descriptive programming library based on the identified reference to the test object; and identify an application object, associated with the application under testing, based on the stored test object description.

Abstract: Techniques for automated bug detection. A set of inputs are collected and a snapshotting feature is used to apply each input to a test application. Outputs from the test application are gathered and compared to determine whether the outputs are associated with bugs. Comparison can be done with one or more of many different techniques that quantify difference between outputs associated with test inputs and outputs associated with a “happy path input.” Outputs can be grouped together based on these quantifications and the groups can be used to identify outputs most likely to be associated with bugs. The output groups may also be used to group associated inputs to the set of inputs to be used for testing in the future. When a bug is identified, a report could be automatically generated that includes a scoring value as well as recorded output information and could be presented to a user.

Abstract: A definition for the API is received. A request and response model is built for each defined operation of the API resource using the received definition. A simulated response for each defined operation of the API resource is generated in an API development environment according to the request and response model.

Abstract: The disclosed embodiments provide a system that facilitates the development and testing of a software program. During operation, the system receives and stores a plurality of defect reports associated with a software program, wherein each defect report documents a previously discovered defect in the software program. In response to detecting a given test failure of the software program while testing the software program in a test environment, the system then eliminates, based on attributes of the test environment that are selected by the defect reports, one or more of the defect reports from the plurality of defect reports, wherein at least one of the selected attributes is retrieved from the test environment during the determination by invoking a provider script that is specified by one of the defect reports. Next, the system associates the test failure with a defect report that remains after the one or more eliminations.

Abstract: A graphical user interface allows a user with little or no knowledge of XML to compose and manage automated tests for a target testing platform and testing framework. An example system opens an XML file storing test parameters and converts the test parameters to fields in a graphical user interface for presentation to a user. The system receives, from the user, input via the graphical user interface to modify the test parameters to yield modified test parameters, and outputs the modified test parameters, in XML format, for use with a testing framework which is configured to perform automated tests on a target test platform based on the modified test parameters.

Abstract: Embodiments for automated testing of a virtualization management system are described. According to one aspect, a method includes generating a test case including a plurality of instances of commands and sending the test case to a plurality of interfaces supported by the virtualization management system. The method also includes generating a response file corresponding to each command in the test case. The method also includes comparing results from each interface to an instance of a command and in response to the results from each interface being identical, storing, the results in the response file corresponding to the command. The method also includes reporting an error in response to the results from each interface of the virtualization management system not being identical. The present document further describes examples of other aspects such as systems, computer products.

Abstract: A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing storage devices. In some implementations, a memory controller receives a logical write request over a logical interface that the memory controller provides for accessing a non-volatile storage device. The logical write request indicates a logical address at which to write data to the non-volatile storage device. In response to receiving the logical write request, the memory controller sends a write request event to a host system. The memory controller receives a physical write command from the host system over a physical interface that the memory controller provides for accessing the non-volatile storage device. In response to receiving the physical write command, the memory controller stores the data in the non-volatile storage device according to the physical write command.

Abstract: Embodiments described herein are directed to systems and methods for ordering read sector data that has been returned from a hard disk controller out of order. For example, in typical storage systems, the firmware of the storage system and/or the host interface typically process read sectors in logical block address order. However, some of the data that is received may be received out of order. As such, the disk block hardware within the hard disk controller may accept these out of order sectors from the read channel and subsequently provide information that describes the available sectors that are in order to the firmware and/or the host interface.

Abstract: An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.

Abstract: According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.

Abstract: A sorted key-value store is implemented using a write-back cache maintained in memory, a B-tree data structured maintained in disk, and a logical and physical log for providing transactions. The logical log and write-back cache are used to answer client requests, while dirty blocks in the write-back cache are periodically flushed to disk using the physical log.

Abstract: A multi-processor computer system with shared memory resources includes a first plurality of sensors configured to acquire inertial and positional data related to a mobile platform. The system further includes a first plurality of co-processors having a hardware logic configured to control the acquisition of the inertial and positional data and configured to analyze the acquired data. The system also includes a second plurality of sensors configured to acquire input data related to the mobile platform connected to a second plurality of co-processors having a hardware logic configured to receive a plurality of streams of input data from the second plurality of sensors and configured to segment the input data into a plurality of discrete data segments. The system also includes a plurality of hardware processing units configured to perform calculations related to the input data using the plurality of data segments.

Abstract: A data storage device is disclosed comprising a non-volatile memory. A command rate profile is initialized, wherein the command rate profile defines a limit on a number of access commands received from a host as a function of an internal parameter of the data storage device. The command rate profile is adjusted in response to a change in operating mode.

Abstract: In various embodiments, a storage device includes a magnetic media, a cache memory, and a drive controller. In embodiments, the drive controller is configured to establish a portion of the cache memory as an archival zone having a cache policy to maximize write hits. The drive controller is further configured to pre-erase the archival zone, direct writes from a host to the archival zone, and flush writes from the archival zone to the magnetic media. In embodiments, the drive controller is configured to establish a portion of the cache memory as a retrieval zone having a cache policy to maximize read hits. The drive controller is further configured to pre-fetch data from the magnetic media to the retrieval zone, transfer data from the retrieval zone to a host upon request by the host, and transfer read ahead data to the retrieval zone to replace data transferred to the host.

Abstract: The memory control unit includes a descriptor fetch block suitable for fetching a descriptor from a volatile memory; an instruction fetch block suitable for fetching an instruction set from an instruction memory through an address information, wherein the instruction fetch block obtains the address information from the instruction memory through an index information included in the fetched descriptor; and a memory instruction generation block suitable for generating a memory instruction by combining a descriptor parameter value included in the fetched descriptor to the fetched instruction set.

Abstract: A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.

Abstract: A technique for operating a lower level cache memory of a data processing system includes receiving, by a store queue controller, an operation that is associated with a first thread. The store queue controller uses level one (L1) cache memory miss information for the operation to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.

Abstract: An emulated input/output memory management unit (IOMMU) includes a management processor to perform page table translation in software. The emulated IOMMU can also include a hardware input/output translation lookaside buffer (IOTLB) to store translations between virtual addresses and physical memory addresses. When a translation from a virtual address to a physical address is not found in the IOTLB for an I/O request, the translation can be generated by the management processor using page tables from a memory and can be stored in the IOTLB. Some embodiments can be used to emulate interrupt translation service for message based interrupts for an interrupt controller.

Abstract: The disclosed embodiments provide a system for processing data. During operation, the system obtains an attribute of a stack trace of a software program. Next, the system uses the attribute to select an address-translation instance from a set of address-translation instances for processing the stack trace. The system then provides the stack trace to the selected address-translation instance for use in translating a set of memory addresses in the stack trace into a set of symbols of instructions stored at the memory addresses.

Abstract: Embodiments for generating and using an enhanced initialization vector are disclosed. In one embodiment, data and a record identifier to which the data is to be written are received. An initialization vector for encrypting the data is then generated. The initialization vector is based on the record identifier and a value that changes every time that the record identifier is to be written to. The value can be generated, for example, by a counter that increments every time the record identifier is to be written to or by a random number generator that generates a random number every time the record identifier is to be written to. In some embodiments, the generated initialization vector is also based on a second value, such as, for example, a value that is shared by other storage modules or a value that is unique to the storage module.

Abstract: For storing data in a data-storage structure of a server computer, an infrastructure is deployed to a server computer. The infrastructure has a forwarder module to receive data from an application and to identify a data portion, a crypto module to encrypt the data portion with a key and key control module adapted to generate and to store the key. The infrastructure is also able to process data in the opposite direction. The key is provided into the key control module upon receiving a key trigger from the client computer.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A peripheral device connected to a local electronic device which is connected to at least one communication network can communicate with a peripheral device attached to a remote electronic device as if the remote peripheral device was locally attached. Data designated for the remote peripheral device is received by a local virtual device object and transmitted to the remote electronic device via at least one of the electronic devices communication interfaces or peripheral devices. Data received by the remote electronic device's communication interface or peripheral device is written to the peripheral device at the remote electronic device by a virtual device object. For compensation of different transfer speeds or outages between the peripheral device and the communication interface or another peripheral device the virtual device provides the ability to utilize the virtual devices emulation driver that is attached to the virtual device object as an I/O buffer.

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

Abstract: A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a determination, for each of N addresses a1 to an (N is a natural number no less than two) included in the address set (A), whether or not the address and another address adjacent to that address in an accessing order can be accessed by the same burst access, and calculates an access time that will be taken for accessing the address set by the burst access.

Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

Abstract: Embodiments of a method and system are disclosed. One embodiment of a method for signaling an interrupt in an I2C system that includes a master I2C device and at least one slave I2C device that are connected by an SDA line and an SCL line is disclosed. The method involves, at the slave I2C device, pulling the SDA line low to signal an interrupt and at the slave I2C device, releasing the SDA line in response to either the SCL line having been pulled low or the expiration of a predetermined time period, whichever occurs first. In an embodiment, the predetermined time period is 1 ms.

Abstract: A system and method are provided for generating interrupts in a computer system using limited interrupt virtualization hardware. A peripheral component interconnect express (PCIe) device atomically sets one or more bits in a posted interrupt vector (PIV) of a target central processing unit (CPU), and sends an interrupt to the target CPU, the interrupt notifying the target CPU of changes to the PIV. Atomically setting the one or more bits may include executing a compare-and-swap function, executing a fetch-and-add instruction to increment a DWORD corresponding to the one or more bits in the PIV by a value of 2 ^ (b mod 32), using PCIe byte enables to write to a single byte in the PCIe address space that contains the one or more bits, using a helper CPU, performing a PCIe swap to the PIV, or storing the PIV in a memory of the PCIe device.

Abstract: At start-up of a computer apparatus, a CPU executes a first initialization procedure included in a RAS module to initialize resources to be used by the RAS module. After execution of the first initialization procedure, the CPU executes an initialization procedure included in an OS to initialize resources to be used by the OS. After execution of the initialization procedure, the CPU executes a second initialization procedure included in the RAS module to copy an interrupt determining part included in the OS to the RAS module, and to set the interrupt detection unit such that upon detecting an interrupt the interrupt detection unit calls an interrupt determining part copied to the RAS module, instead of the interrupt determining part in the OS.

Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold.