Patents Issued in September 11, 2018
  • Patent number: 10073619
    Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
  • Patent number: 10073620
    Abstract: Memory management is provided within a data processing system 2 which includes a memory protection unit 8 and defines memory regions within the memory address space which extend between base addresses and limit addresses and have respective attributes associated therewith. When a hit occurs within a memory region which is a valid hit, then block data is generated comprising a mask value and a TAG value (derived from the original query address) which may then be used to identify subsequent hits within at least a portion of that region using a bitwise AND. In another embodiment a micro-translation lookaside buffer is reused by the memory protection unit to store page data identifying pages which fall validly within memory regions and may be used to return attribute data for those pages upon subsequent accesses rather than performing the comparison with the base address and the limit addresses.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 11, 2018
    Assignee: ARM Limited
    Inventor: Simon John Craske
  • Patent number: 10073621
    Abstract: A method is used in managing storage device mappings in storage systems. A set of mappings is created in a distributed storage system. The distributed storage system stores data in a redundant manner at more than one location on a set of storage devices by using a set of stripes. Each stripe of the set of stripes indicates a data slice stored on a storage device. Each mapping of the set of mappings identifies information regarding location of data on a storage device for a stripe. The mapping is stored on the set of storage devices.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 11, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Robert P. Foley, Peter Puhov
  • Patent number: 10073622
    Abstract: A memory system may include: a memory device comprising a plurality of memory blocks each having N word line groups; and a controller suitable for: selecting bad memory blocks among the plurality of memory blocks, arranging normal word line groups of the selected bad memory blocks into one or more memory-block-word-line groups each including non-conflicting N normal word line groups, and managing each of the memory-block-word-line groups as a reused memory block.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Soo-Nyun Kim
  • Patent number: 10073623
    Abstract: A memory system, may include: a memory device including a plurality of memory blocks each including a plurality of stacked word lines; and a controller suitable for dividing the plurality of word lines into two or more word line groups according to heights thereof, programming data of a relatively high access frequency into a word line group having word lines of relatively low physical heights and data of a relatively low access frequency into a word line group having word lines of relatively high physical heights among the word line groups included in each of the memory blocks.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Byoung-Sung You
  • Patent number: 10073624
    Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinken Okamoto
  • Patent number: 10073625
    Abstract: The present disclosure relates to a system and methods of controlling a system of storage devices. In particular, the present disclosure relates to methods of controlling peak power and energy consumption in storage systems due to storage devices while maintaining data availability. The system implements a method for maintaining data availability in a storage subsystem by determining a plurality of storage devices to include in a fixed set of storage devices based on a fault tolerance system. The storage devices included in the fixed set are prevented from transitioning between RPM spin modes. The method further involves controlling peak power and energy consumed by the storage subsystem which may include transitioning the storage devices not included in the fixed set from a high RPM operational mode to a low RPM operational mode to reduce peak power and energy consumption.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: September 11, 2018
    Assignee: HGST Netherlands B.V.
    Inventors: Cyril Guyot, Mohammed Ghiath Khatib, Adam C. Manzanares, Lluis Pamies-Juarez
  • Patent number: 10073626
    Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 11, 2018
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Ajith Kumar
  • Patent number: 10073627
    Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 11, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Vijay Sivasankaran, Krishnamurthy Dhakshinamurthy, Arun Thandapani
  • Patent number: 10073628
    Abstract: The memory system, may include: a memory device comprising a plurality of memory blocks; and a controller suitable for performing a command operation to the memory blocks, updating update parameters and erase cycles (ECs) of the memory blocks, selecting at least one source memory block based on the update parameters, selecting at least one target memory block based on the ECs, and performing at least one swap operation between the selected at least one or more source memory block and the selected at least one target memory block.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10073629
    Abstract: Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: The method may further include: allocating, by a memory controller, a reserved portion of the memory controller to process prioritized transactions; receiving, by the memory controller, a request transaction from a processor to the memory, wherein the request transaction comprises a priority; determining, by the memory controller, whether the priority of the request transaction is above a priority threshold; and responsive to determining that the priority of the request transaction is above the priority threshold, executing the request using the reserved portion of the memory controller.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Irving G. Baysah, Prasanna Jayaraman
  • Patent number: 10073630
    Abstract: A storage module may be configured to perform log storage operations on a storage log maintained on a non-volatile storage medium. An I/O client may utilize storage services of the storage module to maintain an upper-level log. The storage module may be configured to coordinate log storage and/or management operations between the storage log and the upper-level log. The coordination may include adapting a segment size of the logs to reduce write amplification. The coordination may further include coordinating validity information between log layers, adapting log grooming operations to reduce storage recovery overhead, defragmenting upper-level log data within the storage address space, preventing fragmentation of upper-level log data, and so on. The storage module may coordinate log operations by use of log coordination messages communicated between log layers.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: September 11, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Jingpei Yang, Nisha Talagala, Swaminathan Sundararaman, Ned Plasson, Gregory N. Gillis
  • Patent number: 10073631
    Abstract: The time required for recalling the file is reduced when the file is written in a mounted plurality of tapes in comparison to recalling the file when written in a non-mounted plurality of tapes. In the non-mounted state, criteria does not typically exist in order to recall the written file within the plurality of tapes. Embodiments of the present invention provide systems and methods for recalling files based on criteria which considers: the mounted state of a tape; the type of tape; the type of available tape drive; the number of files included in a tape; and the location of the written file in a tape.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Sosuke Matsui, Shinsuke Mitsuma, Tsuyoshi Miyamura, Noriko Yamamoto
  • Patent number: 10073632
    Abstract: The time required for recalling the file is reduced when the file is written in a mounted plurality of tapes in comparison to recalling the file when written in a non-mounted plurality of tapes. In the non-mounted state, criteria does not typically exist in order to recall the written file within the plurality of tapes. Embodiments of the present invention provide systems and methods for recalling files based on criteria which considers: the mounted state of a tape; the type of tape; the type of available tape drive; the number of files included in a tape; and the location of the written file in a tape.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Sosuke Matsui, Shinsuke Mitsuma, Tsuyoshi Miyamura, Noriko Yamamoto
  • Patent number: 10073633
    Abstract: The present invention provides a data storage system and method. A controller is connected to a plurality of disk arrays, and each disk array is provided with a data protection unit for data protection. When one disk drive of one of the disk arrays is damaged, this disk array is defined as a damaged disk array, while other disk arrays without disk drives being damaged are defined as at least one normal disk array. The controller stops to write a new written data into the damaged disk array, while write the new written data into the normal disk arrays. The new written data will be protected by the data protection units of the normal disk arrays. Thereby, continuous data protection for the new written data by the data protection units together with preservation of storage performance of the system, after the disk drive is damaged, may be achieved.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 11, 2018
    Assignee: Accelstor Ltd.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Patent number: 10073634
    Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: September 11, 2018
    Assignee: Apple Inc.
    Inventors: Shai Ojalvo, Eyal Gurgi, Yoav Kasorla
  • Patent number: 10073635
    Abstract: Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes and determining a particular endianness format of the plurality of bytes. The method can include, responsive to determining the particular endianness format is a first endianness format, reordering bits of each byte of the plurality of bytes on a bytewise basis, storing the reordered plurality of bytes in an array of memory cells, and adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array. The method can include, responsive to determining the particular endianness format is a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jeremiah J. Willcock, Kyle B. Wheeler, Timothy P. Finkbeiner
  • Patent number: 10073637
    Abstract: A data storage device includes a nonvolatile memory device; a control unit configured to generate a descriptor in which works for controlling the nonvolatile memory device are written; a memory control unit configured to provide control signals and write data to the nonvolatile memory device based on the descriptor; and a voltage detector configured to provide a voltage drop signal to the memory control unit in the case where a first operating voltage provided to the memory control unit or a second operating voltage provided to the nonvolatile memory device, drops.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dong Jae Shin
  • Patent number: 10073638
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device detects a commissioned storage unit (SU) that was previously non-commissioned and identifies SU(s) that include commissioned SUs among the SUs. The computing device then identifies a SU topology of the SU(s) and selects a subset of the SU(s) based on the SU topology. The computing device then obtains SU address range assignments of the subset of the SU(s) facilitates assignment of a SU address range for the commissioned SU that was previously non-commissioned within the SUs based on the SU address range assignments of the subset of the SU(s).
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Greg R. Dhuse, Jason K. Resch
  • Patent number: 10073639
    Abstract: A method and system for improving operation of a memory device is provided. The method includes detecting, via sensors, environmental factors affecting an operation of individual hardware storage devices within an array of hardware storage devices. The environmental factors are analyzed with respect to operational characteristics of the individual hardware storage devices and a resulting expected failure rate for the individual hardware storage devices is determined. Array parameters associated with a hardware configuration for the array of hardware storage devices with respect to each expected failure rate are determined and associated issues are detected. Reliability characteristics and associated risks of the array of hardware storage devices are determined and a functionality of the array of hardware storage devices is modified.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: John J. Auvenshine, Perry J. Gallo, Bent B. Holst, Mikael H. Lindstrom
  • Patent number: 10073640
    Abstract: In one embodiment a plurality of open channel solid state drives (SSDs) are implemented over a network comprised of a network switch having a plurality of nodes, a remote host connected to a first node of the network switch, a metadata server connected to a second node of the network switch, and an abstracted memory structure comprised of at least part of one of the plurality of open channel SSDs. In one embodiment, the remote host is configured to communicate with the metadata server by issuing a command identifying data related to the abstracted memory structure. In another embodiment, the metadata server is configured to communicate with the remote host by responding to the command and identifying a physical address corresponding to the identified data.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Yaron Klein
  • Patent number: 10073641
    Abstract: Cluster families for cluster selection and cooperative replication are created. The clusters are grouped into family members of a cluster family base on their relationships and roles. Members of the cluster family determine which family member is in the best position to obtain replicated information and become cumulatively consistent within their cluster family. Once the cluster family becomes cumulatively consistent, the data is shared within the cluster family so that all copies within the cluster family are consistent.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Bish, Takeshi Nohta, Joseph M. Swingler, Rufus-John Y. Twito
  • Patent number: 10073642
    Abstract: A method for operating a data storage device including a plurality of memory regions. The method includes performing a read operation for a first memory region, increasing a read count based on read sequences of the first memory region and a second memory region which has been read before the read operation for the first memory region, and performing a management operation for the plurality of memory regions based on the read count.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Ik Joon Son
  • Patent number: 10073643
    Abstract: A method of initializing a storage device includes; resetting an interface chip in response to a reset signal generated by the memory controller, loading a boot loader from a nonvolatile memory device via the interface chip in response to a nonvolatile memory initialization signal generated by the memory controller, and initializing a plurality of nonvolatile memory devices by executing the boot loader in the memory controller.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Kil Jung, Hyunggon Kim
  • Patent number: 10073644
    Abstract: An electronic apparatus includes a processor, non-volatile memory devices having first modules running in memory mode and second modules running in storage mode, and a memory controller. In response to a request to load data stored in a third module running in storage mode, into a space that is mapped by the memory controller, the processor changes the mode of the third module to memory mode and the memory controller creates a mapping for the data stored in the third module. In response to a request to copy data loaded into a space that is mapped by the memory controller to a module running in storage mode, the processor changes the mode of a third module, which is storing a portion of the data and running in memory mode, to storage mode.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Shintaro Wada
  • Patent number: 10073645
    Abstract: A method begins by detecting a recovery error when decoding a seemingly valid threshold number of existing encoded data slice. The method continues by sending a notice of the recovery error and a known integrity check value for the data segment to a rebuild module. The method continues by the rebuild module retrieving the set of existing encoded data slices and selectively decoding a different combination of a decode threshold number of existing encoded data slices of the set of existing encoded data slices until the data segment is successfully recovered. The method continues by dispersed storage error encoding the successfully recovered data segment to produce a set of new encoded data slices. The method continues by comparing the seemingly valid encoded data slices with corresponding new encoded data slices on an encoded data slice by encoded data slice basis to identify a corrupted encoded data slice.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Niall J. McShane, Jason K. Resch, Ilya Volvovski
  • Patent number: 10073646
    Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Oluwatobi A. Ajila, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
  • Patent number: 10073647
    Abstract: Methods, systems, and apparatuses are described for provisioning storage devices. An example method includes specifying a logical zone granularity for logical space associated with a disk drive. The method further includes provisioning a zone of a physical space of the disk drive based at least in part on the specified logical zone granularity. The method also includes storing compressed data in the zone in accordance with the provisioning.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: September 11, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Timothy R. Feldman
  • Patent number: 10073648
    Abstract: Methods, systems, and apparatus for allocating, by a source of one or more sources, a segment of a data file of a transient memory for exclusive access by the source, the transient memory being a distributed in-memory file system that supports remote direct memory access; writing, by the source, data from an initial partition to one or more blocks within the allocated segment of the data file, wherein a portion of the initial partition is written to a first block of the one or more blocks; publishing, by the source, the segment of the data file of the transient memory to be accessible for reading by one or more sinks; and reading by a particular sink of the one or more sinks, a particular block of the published segment of the data file of the transient memory, wherein the particular block is associated with the particular sink.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 11, 2018
    Assignee: Google LLC
    Inventors: Hossein Ahmadi, Matthew B. Tolton, Michael Entin
  • Patent number: 10073649
    Abstract: A method and a system for storing metadata. The method includes requesting an update of metadata from an external source. The method includes storing updated metadata to a fast storage medium using an update thread. The method further includes moving the updated metadata from the fast storage medium to a slow storage medium using a flush thread.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: September 11, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventor: David Michael DeJong
  • Patent number: 10073650
    Abstract: An exemplary system preserves the autonomy of two or more distinct storage management systems all the while enabling backed up data to be restored from a first storage management system (the “local system”) to a specially-configured client in a second storage management system (the “remote system”). For example, backed up data in the local system (e.g., a secondary copy of production data) may be transferred, in a restore operation, from secondary storage in the local storage management system, which originated the data, to a client of the remote storage management system (the “remote client”). As a specially-configured “restore-only client,” the remote client is limited to receiving backed up data from the local storage management system, via restore operation(s) managed by the local storage manager. The remote client remains a full-fledged client in its home system, the remote storage management system.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 11, 2018
    Assignee: COMMVAULT SYSTEMS, INC.
    Inventors: Prasad Nara, Michael F. Klose
  • Patent number: 10073651
    Abstract: A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for performing a plurality of operations to first memory blocks among the memory blocks at a first time, recording a checkpoint information for the operations in the memory blocks, selecting second memory blocks among the first memory blocks through the checkpoint information at a second time after a power-off in the memory system while performing the operations, and performing a dummy write operation to the second memory blocks.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10073652
    Abstract: Methods for use in a dispersed storage network (DSN) to enable rapid retrieval of data. A first set of storage units of the DSN is configured as a performance optimized internal vault that utilizes dispersed error encoding/decoding parameters which provide improved data access performance in relation to a second set of storage units. Upon receiving a data object for storage, a computing device of the DSN determines, based on at least one performance criterion, to store the data object in the performance optimized internal vault as opposed to the second set of storage units. The data object is then dispersed storage error encoded, in accordance with dispersal parameters associated with storage of data in the internal vault, to produce a plurality of sets of performance encoded data slices, wherein the data object is segmented and each resulting data segment is encoded into a respective set of performance encoded data slices.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Harsha Hegde, Wesley B. Leggette
  • Patent number: 10073653
    Abstract: A solid state disk, including a main body, a processing unit, a display screen and a transmit port. The main body has a substrate and a shell portion covering on two opposite side faces of the substrate, the substrate is provided with a memory module; the processing unit is disposed in the main body; the display screen is attached to the main body and viewable from outside of the solid state disk, the display screen is electrically connected with the processing unit, the processing unit can control a display state of the display screen; and the transmit port is disposed on the substrate, and the transmit port is electrically connected with the memory module.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 11, 2018
    Assignee: Alson Technology Limited
    Inventors: Han-Hung Cheng, Chi-Fen Kuo
  • Patent number: 10073654
    Abstract: Example systems and related methods may relate to monitoring performance of an image forming operation. Namely, a system may include an image forming apparatus configured to execute an operation. The system further includes an external sensor circuit comprising one or more sensors and a processor. The system yet further includes a host computing device configured to generate, in response to receiving notifications of a status of the operational parameter received from the one or more processors of the sensor circuit, a first timestamp indicative of when the image forming apparatus started to execute the printing operation, and a second timestamp indicative of when the image forming apparatus completed the printing operation. The host computing device is further configured to generate a log file. Data of the log file includes the first timestamp and the second timestamp, and is indicative of how quickly the image forming apparatus executed the operation.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: September 11, 2018
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Edwin Philip Lockwood
  • Patent number: 10073655
    Abstract: A semiconductor integrated circuit apparatus 23 is used for obtaining an optimum solution using an Ising model, and the semiconductor integrated circuit apparatus 23 includes plural spin cells 1 that are connected with each other. Here, each spin cell 1 includes: a memory cell 9(N) for memorizing a spin value; a computing circuit 10 for computing interactions among the plural spin cells that are connected with each other; a memory circuit 4 for holding at least one-bit data; and an inversion logic circuit LG capable of modifying a computed result obtained by the computing circuit in accordance with data held by the memory circuit 4. The computed result modified by a modification circuit in accordance with the data held by the memory circuit is memorized in the memory cell 9(N) included in each spin cell 1.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: September 11, 2018
    Assignee: HITACHI, LTD.
    Inventors: Masanao Yamaoka, Chihiro Yoshimura
  • Patent number: 10073656
    Abstract: An I/O manager may be configured to service I/O requests pertaining to ephemeral data of a virtual machine using a storage device that is separate from and/or independent of a primary storage resource to which the I/O request is directed. Ephemeral data may be removed from ephemeral storage in response to a removal condition and/or trigger, such as a virtual machine reboot. The I/O manager may manage transfers of ephemeral virtual machine data in response to virtual machines migrating between host computing devices. The I/O manager may be further configured to cache virtual machine data, and/or manage shared file data that is common to two or more virtual machines operating on a host computing device.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: September 11, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jerene Zhe Yang, Yang Luan, Brent Lim Tze Hao, Vikram Joshi, Michael Brown, Prashanth Radhakrishnan, David Flynn, Bhavesh Mehta
  • Patent number: 10073657
    Abstract: According to an embodiment, an update request reception unit receives a data update request to update data stored in a storage. A read request unit makes a read request to read data from the storage. A data reception unit receives the data from the storage. An update value calculator calculates an update value of the received data. A write request unit makes a write request to write the calculated update value into the storage. A data processing execution unit executes reading and writing on the storage. A history processing unit generates a history of the reading and deletes a history of reading corresponding to the writing. An update information estimator estimates, from the generated history, update information indicating how the data is to be updated. A data update unit updates the data read according to the estimated update information and output new updated data to the data reception unit.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shingo Tanaka
  • Patent number: 10073658
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device receives a data access request involving a set of EDSs associated with a data object that are distributedly stored among storage units (SUs) including first SU(s) coupled via a local network of the DSN and second SU(s) remotely located to the computing device and coupled via an external network of the DSN. The computing device caches within the at least one memory therein a subset of EDSs stored within the second SU(s) remotely located to the computing device and coupled to the computing device via the external network.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Manish Motwani, Ethan S. Wozniak
  • Patent number: 10073659
    Abstract: A method is described. The method includes receiving an indication of an activity of load circuitry of a power supply. The method includes, in response to the indication, generating a first signal that describes the activity and a second signal that describes whether the event is initiating or completing. The method includes determining a weight amount from the first signal and adjusting a credit count by the weight amount up or down based on the second signal. The method includes comparing the credit count against a first threshold. The method includes calculating an average credit count that accounts for the credit count and previous credit counts and comparing the average credit count against a second threshold. The method includes adjusting an activity level of the load circuitry if either threshold is crossed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: James Alexander, Muthukumar P. Swaminathan, Richard P. Mangold
  • Patent number: 10073660
    Abstract: Provided herein are a memory system and method of operating the memory system, which have improved reliability. A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks, the method comprising generating a program command and a program address for performing a program operation on at least one page included in an open block, among the plurality of memory blocks, reading data from the at least one page corresponding to the program address and transmitting the program command and the program address to the semiconductor memory device when the number of fail bits included in data read from the at least one page is equal to or less than a first reference value.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventors: Byoung Jun Park, Seong Jo Park, Kang Jae Lee
  • Patent number: 10073661
    Abstract: The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 11, 2018
    Assignee: Atmel Corporation
    Inventors: Frode Milch Pedersen, Ian Fullerton, Joseph Martinez, Martin Olsson
  • Patent number: 10073662
    Abstract: An image forming apparatus and a method of recovering errors of the image forming apparatus connectable to a server for supporting a service for error recovery of the image forming apparatus are provided. The method includes connecting, when connection with the server through a first network is restricted, to a mobile apparatus through a second network different from the first network, transmitting state information required for error recovery of the image forming apparatus to the connected mobile apparatus through the second network, receiving a control command required for error recovery of the image forming apparatus from the mobile apparatus through the second network, in response to the transmitted state information, and recovering errors of the image forming apparatus according to the received control command.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 11, 2018
    Assignee: S-Printing Solution Co., Ltd.
    Inventor: Hyun-wook Park
  • Patent number: 10073663
    Abstract: A network device that is capable of notifying of a factor of an error when reboot in response to an instruction cannot be performed due to an operating state. The network device is connected to a network. A receiving unit receives a reboot instruction through the network. A determination unit determines propriety of reboot based on an operating state of the network device when the receiving unit receives a reboot instruction. A reply unit replies information indicating no error when the determination unit determines that reboot is available, and replies information indicating an error together with information indicating a factor of unavailable reboot when the determination unit determines that reboot is unavailable.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 11, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hironobu Nakai
  • Patent number: 10073664
    Abstract: A system for providing print device dynamic status indicator feedback includes a print device, and a status indicator feedback unit. The print device includes a print engine and one or more status monitors. The status indicator feedback unit includes a display device, a light emitting module, a processor in communication with the light emitting module, and a computer-readable medium containing programming instructions. The system may receive information corresponding to one or more current machine states of the print device from the one or more status monitors of the print device, determine a priority level associated with each of the one or more current machine states, identify a machine state associated with a highest priority level, identify a dynamic feedback pattern associated with the identified machine state. The dynamic feedback pattern includes a visual pattern. The system may and instruct the light emitting module to emit the visual pattern.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 11, 2018
    Assignee: Xerox Corporation
    Inventors: Stephen F. Skrainar, Andrew T. Martin, Donald A. Brown, Keith L. Willis, Ken Hayward, Brandon S. McComber, Shinichi Maekawa, Mitsuharu Ito, Shinya Kogoh, Masaaki Takenouchi
  • Patent number: 10073665
    Abstract: An image forming apparatus includes a management application and a common application. The management application manages a counter. The common application is other than the management application. The management application causes the image forming apparatus to function as: a counter managing unit that manages the counter that counts a count of executions of specific processing by the common application; and an execution count unit that counts the count of executions using the counter managed by the counter managing unit.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: September 11, 2018
    Assignee: Kyocera Document Solutions Inc.
    Inventor: Jumpei Takagi
  • Patent number: 10073666
    Abstract: A notification manager is provided that manages notifications for a user. The notification manager detects a notification event and determines a context of the notification event. The notification manager determines a target device for the notification event based on the determined context and one or more available displays. The notification manager then generates a notification on one or more of the one or more available displays to direct the user's attention to the target device.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: September 11, 2018
    Assignee: Immersion Corporation
    Inventors: Vincent Levesque, Danny Grant, Jean-Francois Blanchard-Dionne, Amaya Becvar Weddle, Juan Manuel Cruz-Hernandez
  • Patent number: 10073667
    Abstract: A monitor device is one of a plurality of monitors connected in series. The monitor device includes: an acquisition unit that acquires the number of the monitors; a calculation unit that calculates a region to be displayed by the monitor device, of an image corresponding to an image signal, and a display size of an image corresponding to the region, based on the acquired number of the monitors and arrangement of the monitor device in the serial connection; a display unit that displays the image corresponding to the region according to the display size; and a communication unit that outputs the acquired number of the monitors to one of the monitors when the one of the monitors is arranged at a subsequent stage of the monitor device.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: September 11, 2018
    Assignee: NEC DISPLAY SOLUTIONS, LTD.
    Inventor: Hiromi Hosokawa
  • Patent number: 10073668
    Abstract: An electronic device is provided. The electronic device includes a foldable housing including a first housing part that includes a first surface and a second surface facing opposite to the first surface, a second housing part including a first surface that faces the first surface of the first housing part when the housing is folded in a first direction and a second surface that faces the second surface of the first housing part when the housing is folded in a second direction. The electronic device includes a first display, a second display disposed, a first sensor disposed in the first housing part, a second sensor disposed in the second housing part, and a processor that is configured to identify an angle between the first housing part and the second housing part using the first sensor and the second sensor and execute at least one action of the electronic device based on the identified angle.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Woosung Chun, Soohyeon Sim, Seulki Lee, Kyungjung Kim, Seongeun Kim, Jinwoo Kim, Jungsik Park, Jingil Yang, Yujeong Jeon, Inji Jin, Hyunju Hong
  • Patent number: 10073669
    Abstract: Disclosed herein are an image display device and a method of controlling the image display device. The image display device includes an image acquirer configured to acquire a user image, an image outputter configured to display the user image, a communicator configured to perform communication with a mobile terminal, a controller configured to perform a real time image display operation. The real time image display operation includes displaying the user image in real time and transmitting image data processed from the user image to the mobile terminal when a real time image display command is input.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yui Yoon Lee