Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: The present invention provides methods and apparatuses for processing a gateway device fault. According to one embodiment, when a fault on a gateway device is detected, computing tasks currently executed by the faulty gateway device are acquired; to-be-allocated computing tasks are screened out according to parameters configured when the computing tasks are issued; the computing tasks running on the faulty gateway device are terminated, and the to-be-allocated computing tasks are scheduled to other gateway devices in a normal state according to a preset scheduling strategy. Further, task states of the to-be-allocated computing tasks are recovered, and the to-be-allocated computing tasks are executed by the other gateway devices. Embodiments of the present application can help avoid the problem that computing tasks fail due to a fault occurring in the gateway device, thereby the overall execution efficiency of the computing tasks and ensuring system stability.

Abstract: Aspects of the disclosure relate to management node failover systems and methods. The system includes two management devices and a detection and reversal device. Each of the two management devices has a processor and a non-volatile memory storing computer executable code. The two management devices function respectively as an active node and a passive node. The detection and reversal device monitors status of the active node. When the active node fails, the detection and reversal device sends an activation signal to the passive node. The passive node, in response to receiving the active signal, switches from the passive node to the active node.

Abstract: Near clones for a set of targeted computing systems are provided by determining a highest common denominator set of components among the computing systems, producing a pseudo-clone configuration definition, and realizing one or more pseudo-clone computing systems as partially configured backups for the targeted computing systems. Upon a planned failover, actual failure, or quarantine action on a targeted computing system, a difference configuration is determined to complete the provisioning of the pseudo-clone system to serve as a replacement system for the failed or quarantined system. Failure predictions can be used to implement the pseudo-clone just prior to an expected first failure of any of the targeted systems. The system can also interface to an on-demand provisioning management system to effect automated workflows to realize pseudo-clones and replacement systems automatically, as needed.

Abstract: Various techniques for deferred server recovery are disclosed herein. In one embodiment, a method includes receiving a notification of a fault from a host in the computing system. The host is performing one or more computing tasks for one or more users. The method can then include determining whether recovery of the fault in the received notification is deferrable on the host. In response to determining that the fault in the received notification is deferrable, the method includes setting a time delay to perform a pending recovery operation on the host at a later time and disallowing additional assignment of computing tasks to the host.

Abstract: Aspects of the present disclosure involve systems and methods for removes and/or adding log and/or cache devices to storage pools of a storage appliance. Users, via a graphical-user interface, identify the log and/or cache devices for removal or addition. Subsequently, the log and/or cache devices are moved, according to a data profile corresponding to the devices, from a first storage appliance to a second storage appliance.

Abstract: One or more techniques and/or computing devices are provided for communicating storage controller failures utilizing service processor traps. A first storage controller, of a first storage cluster, has a disaster recovery relationship with a second storage controller of a second storage cluster. The first storage controller comprise a first service processor configured to monitor health of the first storage controller. Responsive to identifying a failure of the first storage controller, the first service processor uses stored communication configuration of a second service processor of the second storage controller to send a service processor trap to the second service processor. In this way, the second service processor initiates a switchover operation by the second storage controller to provide clients with failover access to data previously available through the first storage controller before the failure.

Abstract: A processor memory is stress tested with a variable link stack depth using link stack test segments with non-naturally aligned data boundaries. Link stack test segments are interspersed into test code of a processor memory tests to change the link stack depth without changing results of the test code. The link stack test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The link stack test segments include branch to target, push/pop, push and pop segments. The depth of the link stack is varied independent of the memory test code by changing the number to branches in the branch to target segment and varying the number of the push/pop segments.

Abstract: A processor memory is stress tested with a variable link stack depth using link stack test segments with non-naturally aligned data boundaries. Link stack test segments are interspersed into test code of a processor memory tests to change the link stack depth without changing results of the test code. The link stack test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The link stack test segments include branch to target, push/pop, push and pop segments. The depth of the link stack is varied independent of the memory test code by changing the number to branches in the branch to target segment and varying the number of the push/pop segments.

Abstract: A circuit for calculating power consumption of a phase change memory (PCM) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. The plurality of pipelines may be configured to correspond to a plurality of write periods exhibiting different power consumption values during a write operation of the PCM device executed by a write command. The plurality of pipelines may shift or transmit data in synchronization with a clock signal. The arithmetic logic circuit may be configured to perform an adding operation of all of deviations of the power consumption values at a point of time that data transmission between at least two of the plurality of pipelines occurs, to thus generate a total power consumption value.

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.

Abstract: A management computer that monitors the performance of the components of the computer system includes attribute information for storing characteristic information of the component, component related information for storing the connection relationship between the components, dynamic threshold value calculation information set for each performance information of the constituent elements, and performance related information set with characteristic information of the components related to the performance information.

Abstract: A method includes, with a hypervisor, receiving a first request from a guest to write a first piece of data to a first memory location within a kernel code page. The method further includes determining that the first request triggers a violation based on a kernel protection mechanism, and in response to determining that the first request triggers the violation, determining that the first piece of data includes a breakpoint. The method further includes, in response to determining that the first piece of data includes the breakpoint, copying a second piece of data currently stored at the first memory location to a second memory location within non-guest writeable memory and overwriting the first memory location with the first piece of data.

Abstract: The present invention provides a debugging system and method for an embedded device, including: an embedded device, including a processing unit and a memory unit, where the memory unit includes a staging area used to store debugging data; a mobile storage device, including a debugging data control unit and a storage unit; and a computer, electrically connected to the embedded device and the mobile storage device. The debugging data control unit transmits a debugging demand message to the embedded device by using the computer. The embedded device transmits the debugging data in the staging area back to the computer. The computer transmits the debugging data to the mobile storage device and stores the debugging data in the storage unit.

Abstract: Enabling breakpoints on entire data structures include methods, systems, and computer program products for setting breakpoints on a plurality of memory addresses covered by a data structure. One embodiment includes receiving a reference to a data structure for which breakpoints are requested and then, based on this reference, identifying a data structure layout of the data structure. Based on the data structure layout of the data structure, a plurality of memory addresses that are covered by the data structure are identified, and the plurality of memory addresses are added to a list of breakpoints.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to obtain a source code. The processor is configured to generate color information by executing conversion processing with regard to the source code while following a rule for converting a character into a color or converting a color of a character in accordance with a type of the character. The processor is configured to output the generated color information.

Abstract: Methods and systems for an automated micro-scheduler testing framework that allows tests to be automatically scheduled or rescheduled based on information such as results of previously-executed tests or other external information are provided. In large-scale development environments, where individual changes to a code repository cannot be specifically fully tested due to scalability and resource issues, micro-scheduler servers may be configured and designed to automatically identify target tests and request that the target tests be executed by a continuous integration system to automatically identify and resolve breakages introduced into a codebase managed by the continuous build system in a large-scale environment.

Abstract: A system generates screenshots of a graphical user interface (GUI) of an application that is displayed by target devices testing the application. Each screenshot includes an image of the GUI and metadata indicative of elements of the GUI present in the image or a state of the application or target device when the image is generated. The system determines, based on the metadata of a screenshot from a first set of the screenshots and the metadata of a screenshot from a second set of the screenshots, whether the screenshots are similar and if so, the system assigns the screenshot from the second set of screenshots to a cluster that includes the screenshot from the first set of screenshots. The system outputs an indication of the cluster (e.g., a notification or graphical indication) indicative of the similarity or discrepancy between the screenshots.

Abstract: A system, method, and computer-readable medium are disclosed for predicting a defect within a computer program comprising: accessing a code base of the computer program, the code base of the computer program comprising a plurality of computer program files; training the defect prediction system, the training including performing a historical analysis of defect occurrence patterns in the code base of the computer program; analyzing a commit of the computer program to identify a likelihood of defect occurrence within each of the plurality of files of the computer program; and, calculating a defect prediction metric for each of the plurality of files of the computer program, the defect prediction metric providing an objective measure of defect prediction for each of the plurality of files of the computer program.

Abstract: Disclosed herein are a method and system for automatic generation of a test script. The method may include acquiring a plurality of test steps from a database, the plurality of test steps being associated with a test case and including one or more words in natural language. The method may also include identifying, using natural language processing on the plurality of test steps, one or more actions to be performed in a testing process. The method may include generating, based on the identified one or more actions, the test script to perform the plurality of test steps. The method may further include identifying, by performing the natural language processing on the plurality of test steps, an expected test result associated with each test step. The method may additionally include generating, a validation script based on the expected test result associated with each of the plurality of test steps.

Abstract: Example implementations relate to automatically identifying regressions. Some implementations may include a data capture engine to capture data points during test executions of the application under test. The data points may include, for example, test action data and application action data. Additionally, some implementations may include a data correlation engine to correlate each of the data points with a particular test execution of the test executions, and each of the data points may be correlated based on a sequence of events that occurred during the particular test execution. Furthermore, some implementations may also include a regression identification engine to automatically identify, based on the correlated data points, a regression between a first version of the application under test and a second version of the application under test.

Abstract: Disclosed are systems and methods for altering functionality of an application. An example method comprises receiving, by a hardware processor, an application update to the application, wherein the application update comprises one or more of a patch, service pack and software update, updating, by the hardware processor, the application based on the application update by applying the application update to the application, detecting, by the hardware processor, one or more events occurring on a computer after updating the application based on the application update, determining, by the hardware processor, one or more portions of the application which caused the one or more events to occur on the computer, altering, by the hardware processor, the one or more portions of the application when a number of detected events exceeds a threshold, wherein how the one or more portions are altered depends on the one or more events.

Abstract: A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Abstract: A process improves upon the binary buddy allocation approach by salvaging memory units that are typically unused during the binary buddy technique. A free power of 2 size block of memory, retrieved in response to an allocation request, is decomposed by releasing units in power of 2 sizes until the requested size is reached. Released units are made available for subsequent allocation requests. The deallocation of a previously allocated block causes the decomposition of the block into power of 2 size sub-blocks. These sub-blocks may be merged with adjacent free blocks using the binary buddy approach now that units in power of 2 are available. The process keeps free blocks maximally coalesced, so that additional steps of defragmentation or merging are not required. A maximum size value restriction may be attached to some blocks of memory which remains preserved during any of the allocation or deallocation processes.

Abstract: A technique for supporting in-place updates in a data storage system includes in response to garbage collection for a logical block address (LBA) being indicated, determining whether an in-place update to the LBA is pending. In response to one or more in-place updates to the LBA being pending prior to the garbage collection for the LBA being indicated, the garbage collection for the LBA is initiated following completion of the one or more in-place updates to the LBA. In response to the one or more in-place updates to the LBA not being pending prior to the garbage collection for the LBA being indicated, the garbage collection for the LBA is completed prior to any subsequent in-place update to the LBA that occurs subsequent to initiation and prior to completion of the garbage collection for the LBA.

Abstract: The systems described herein are configured to enhance the efficiency of memory in a host file system with respect to hosted virtual file systems. In situations when the hosted virtual file systems use smaller file block sizes than the file block sizes of the host file system. During storage of a file, a file block is assigned a block address and unmapping bits. The block address and unmapping bits are stored in a pointer block or other similar data structure associated with the file. Particularly, the block address is stored in a first address block and the unmapping bits are stored in at least one additional address block located in proximity to the block address, such that the unmap granularity of the file is not limited by the fixed size of address blocks in the system.

Abstract: A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.

Abstract: The present disclosure directs to solutions for performing deduplication by a storage device. In the solutions, according to a duplicate data locality principle, non-duplicate data blocks whose logical addresses are contiguous are stored in contiguous physical addresses in a sequence of the logical addresses, and fingerprints of the non-duplicate data blocks whose logical addresses are contiguous are also stored in contiguous physical addresses in the sequence of the logical addresses, and in addition, a mapping from a logical address, which is of one data block in the non-duplicate data blocks whose logical addresses are contiguous, to an aggregation address is established.

Abstract: A memory system includes: a memory device; and a controller including a cache which is coupled between a host and the memory device and includes a plurality of storing regions, for determining whether or not a storing region corresponding to address information which is requested by the host exists in the cache among the plurality of the storing regions based on bitmap information which hierarchically represents the plurality of the storing regions.

Abstract: A first data storage holds cache lines, an accelerator has a second data storage that selectively holds accelerator data and cache lines evicted from the first data storage, a tag directory holds tags for cache lines stored in the first and second data storages, and a mode indicator indicates whether the second data storage is operating in a first or second mode in which it respectively holds cache lines evicted from the first data storage or accelerator data. In response to a request to evict a cache line from the first data storage, in the first mode the control logic writes the cache line to the second data storage and updates a tag in the tag directory to indicate the cache line is present in the second data storage, and in the second mode the control logic instead writes the cache line to a system memory.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A control apparatus includes: an external apparatus control unit configured to load data necessary for execution of calculation processing onto an external memory included by an external apparatus and also cause the external apparatus to execute the calculation processing; a memory access unit configured to convert a logical address used in the calculation processing into a physical address and also access the external memory on the basis of the converted physical address; and an external memory virtualizing unit configured to virtualize the external memory by associating the converted physical address with an external memory physical address that is a physical address in the external memory.

Abstract: A method for accessing data is provide, the method includes: receiving a first address and identification information used to identify an address type; and when the identification information indicates a logical address type, converting the first address into a first physical address, and accessing at least one corresponding flash memory chip in the storage device; or when the identification information indicates a physical address type, directly accessing at least one corresponding flash memory chip in the storage device. When the storage device is accessed, a type of an accessed address is determined according to the identification information. If the address is a logical address, the storage controller maps the logical address to a physical address and accesses the physical address; or if the address is a physical address, the storage controller directly accesses the physical address sent by the host.

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

Abstract: A memory system includes: a controller suitable for generating a control signal for changing a data output status of a memory device to an abnormal status; and the memory device suitable for, when the data output status is the abnormal status, changing second data, which correspond to a read command from the controller among first data stored therein, into encrypted data, and outputting the encrypted data.

Abstract: An automated item transfer vehicle typically includes an item storage unit and an item transfer unit configured to (i) dispense items stored in the item storage unit and (ii) receive items and store the items in the item storage unit. The vehicle also typically includes a memory, a processor, and an item transfer application stored in the memory. The item transfer application is typically configured to: receive an activity request from a user, wherein the activity request includes (i) a request to withdraw items or (ii) a request to store items; authenticate an identity of the user; determine that the location of the vehicle is within an authorized region of the user; and in response to authenticating the identity of the user and determining that the location of the automated item transfer vehicle is within the authorized region of the user, process the activity request.

Abstract: Disclosed aspects relate to hardware-based memory protection of a container-based virtualization environment. A set of access identifiers for a container of a kernel process related to a memory component may be established. An access request from a first user process to a first portion of the memory component may be received. A first candidate access identifier for the first portion of the memory component may be detected. A first access identifier of the set of access identifiers that corresponds to the first portion of the memory component may be identified. A hardware-based memory protection response operation may be determined. The hardware-based memory protection response operation may be carried-out.

Abstract: According to an embodiment, upon receiving a use request including an identifier of a program and authentication information, a use request processing unit makes a determination on validity of the use request based on an ID management information and access authority management information, generates an access key when the use request is valid, registers the access key in access key management information in correlation with a usable address range, and returns the access key to a transmission source of the use request. Upon receiving a read/write request including an address where reading-out or writing of data is performed and an access key, a read/write request processing unit makes a determination on validity of the read/write request based on the access key management information, and executes reading-out or writing of data with respect to a shared memory in response to the read/write request when the read/write request is valid.

Abstract: A media transfer method includes establishing a data connection between a mobile device and an accessory device such that the accessory device acts as a host configured to control access to first content stored within the accessory device. A a request for the first content is sent from the mobile device to the accessory device. In response to the request for the first content, the method includes sending, from the accessory device, the first content to the mobile device via the data connection, wherein first content is sent as a first transaction comprising a single header and a plurality of headerless data packets.

Abstract: A method of managing an external device includes obtaining parameter information of the external device, loading a service module according to the parameter information of the external device, and enabling a communication between a user interface module and a network interface corresponding to the service module.

Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Abstract: Adaptive control of Input/Output (I/O) operations in a data storage system is provided to enable efficient use of the data storage system. More specifically, an interface is provided in order to adaptively control I/O operations to the data storage system. The interface receives a data request. The interface mediates with the data storage system and employs a handle which references one or more files. The handle designates how to process the data request associated with the referenced one or more files. The interface supports execution of the data request in accordance with the handle. Accordingly, the interface provides adaptive direct management of the data storage system at file granularity and/or at data request granularity as designated in the handle(s).

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

Abstract: An electrical device configured to transmit or receive a signal related to an operation element and transmit a data signal using a small number of wirings is realized. An electrical device includes a first terminal and a second terminal to which a pair of signal lines are connected, an operation element connected between the first terminal and the second terminal, and a transmission circuit configured to operate using a voltage between the first terminal and the second terminal as a power source. The second terminal transmits an output signal according to a state of the operation element to the outside, and the transmission circuit superimposes a data signal on the output signal and transmits the data signal from the second terminal to the outside.

Abstract: An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.

Abstract: Many devices may comprise interfaces, such as serial interfaces, over which configuration and/or enablement/disablement of device features may be provided to the device. Connecting a computer to individual devices for manual configuration may be cumbersome and/or time consuming. Accordingly, as provided herein, a device interfacing component (e.g., a microcontroller integrated into an interface cable) is configured to couple to a target device. The device interfacing component may receive data streams from the target device, and may match strings, within the data streams, to expressions. If a string matches an expression (e.g., “F5 for IP setup”), then a corresponding scripted response may be executed to send a response instruction (F5, wait 10 seconds, enter key, “192,168.0.1”) to the target device.

Abstract: The present invention is an SPI-communication-method communication apparatus that has a plurality of slave communication units for a single master communication unit and an electric power converter utilizing the communication apparatus; the master communication unit outputs communication signals simultaneously to all of the slave communication units and separately reads respective data signals outputted by the slave communication units, in accordance with a priority.

Abstract: A modified serial peripheral interface (SPI) is provided in each of a master device and a plurality of slave devices that does not use a slave select line. The master device may thus engage in full-duplex serial communication with each slave device through an SPI MOSI line, an SPI MISO line, and an SPI clock line.

Abstract: A connection management method for a plurality of networked devices, the method constituted of: assigning a priority value to each of the devices, the priority value representing a priority level associated with the respective device; receiving a plurality of connection requests, each of the connection requests being associated with a respective one of the plurality of devices; for each of the received connection requests, tracking the amount of time the respective device has been waiting for connection; for each of the received connection requests, assigning an arbitration wait time value representing the tracked amount of time; responsive to the assigned priority values and the assigned arbitration wait time values, connecting the device associated with one of the received connection requests to an expander port; and responsive to the connection, adjusting the respective priority value assigned to the connected device.