Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.

Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.

Abstract: A data services module performs log storage operations in response to requests by storing data on one or more storage devices, and appending information pertaining to the requests to a separate metadata log. A log order of the metadata log may correspond to an order in which the requests were received, regardless of the order in which data of the requests are written to the storage devices. The requests may correspond to identifiers of a logical address space. The data services module implements an any-to-any translation layer configured to map identifiers of the logical address space to the stored data. The virtualization module may include a metadata management module configured to checkpoint the translation layer metadata by, inter alia, appending aggregate, checkpoint entries to the metadata log. The data services module may leverage the translation layer between the logical identifiers and underlying storage locations to efficiently implement logical manipulation operations.

Abstract: Systems and methods are disclosed to perform out of order LBA processing at a data storage device. A data storage device may be configured to receive a read command including a sequential LBA range, read data for the LBA range in non-sequential order and store the data to a buffer, and return the data to the host in sequential LBA order. The storage device may begin a read operation at a sector in the middle of the LBA range, and read the beginning of the LBA range on a next rotation of the media. The storage device may note the location of read errors without interrupting a read operation. Successfully read data may be buffered, while rereads and error recovery may be performed only on LBAs at which errors were encountered. Once the data from the LBA range has been acquired, the data may be organized into sequential order.

Abstract: Methods may include after a power loss, determining a most recently saved section of a logical block addressing (LBA) table, a previous section saved prior to the most recently saved section of the LBA table, and a least recently saved section of the LBA table, reading an open super block and updating entries in the LBA table from the most recently saved section through to the least recently saved section, reading a newest closed super block from a plurality of closed super blocks and updating entries in the LBA table from the previous section saved prior to the most recently saved section through to the least recently saved section, and reading an oldest super block and updating entries in the LBA table in the least recently saved section.

Abstract: In a system in which a plurality of computing elements share a cache, each computing element owns a stripe of the cache. Each stripe contains cache objects that are accessible to all computing elements but managed only by the owning computing element. Each computing element maintains an LRU FIFO queue in local memory for the cache objects owned by that computing element. Each computing element also maintains a separate hash table in local memory for each other computing element. The hash tables indicate access to cache objects that are owned by those other computing elements. Each computing element updates its LRU FIFO queue when it accesses cache objects that it owns. The hash tables are periodically distributed by all computing elements via RDMA so that the LRU FIFO queues of all computing elements can be updated based on accesses to owned cache objects by other non-owner computing elements.

Abstract: A memory is made up of multiple pages, and different pages can have different priority levels. A set of memory pages having at least similar priority levels are identified and compressed into an additional set of memory pages having at least similar priority levels. The additional set of memory pages are classified as being the same type of page as the set of memory pages that was compressed (e.g., as memory pages that can be repurposed). Thus, a particular set of memory pages can be compressed into a different set of memory pages of the same type and corresponding to at least similar priority levels. However, due to the compression, the quantity of memory pages into which the set of memory pages is compressed is reduced, thus increasing the amount of data that can be stored in the memory.

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

Abstract: An adaptive smart data cache eviction method takes file-based quotas into account during eviction of WEUs as opposed to a default eviction policy that treats all files the same. Adaptive smart data cache eviction is a granular and dynamic eviction of the least frequently and least recently accessed blocks contained in a WEU for those files that have exceeded file-based quotas established for them or that are determined to be candidates for eviction based on the number of blocks stored for them relative to other files and how frequently and recently those blocks were accessed.

Abstract: A method includes generating a set of virtual-machine-specific (VMS) encryption keys for a dedicated virtual machine, storing the set of VMS encryption keys in a protected memory, storing a first look-up table in the protected memory, and replacing an encryption key stored in a crypto unit with at least one VMS encryption key of the set of VMS encryption keys in an operation mode where the dedicated virtual machine is executed by a processor. The protected memory is selectively excluded from access by operating systems executable on a computer system. The look-up table being accessible only by firmware of the computer system.

Abstract: A method includes generating a set of virtual-machine-specific (VMS) encryption keys for a dedicated virtual machine, storing the set of VMS encryption keys in a protected memory, storing a first look-up table in the protected memory, and replacing an encryption key stored in a crypto unit with at least one VMS encryption key of the set of VMS encryption keys in an operation mode where the dedicated virtual machine is executed by a processor. The protected memory is selectively excluded from access by operating systems executable on a computer system. The look-up table being accessible only by firmware of the computer system.

Abstract: An information handling system and method performs Unified Extensible Firmware Interface (UEFI) interception and pre-processing of data associated with block input/output (I/O) commands targeting encrypted storage devices. A UEFI interceptor block (IB) I/O driver intercepts each block I/O command targeting block addresses on a storage device and identifies whether any of the target block addresses is encrypted. In response to identifying an encrypted block address among the target block addresses, the UEFI IB I/O driver forwards data associated with the encrypted block address to an encryption-decryption module to perform one of an encryption and a decryption of the data. Final handling of the block I/O command is performed using a block I/O driver chained to the UEFI IB I/O driver. Data associated with I/O commands targeting encrypted block addresses is first processed by the encryption-decryption module before final handling of the I/O command is performed by the block I/O driver.

Abstract: In some examples, in response to a computing device powering on, a protected memory area inaccessible to an operating system is created, where the protected memory area includes information relating to instructions and an indication settable to a first value to indicate that the instructions are allowed to access a memory external of the protected memory area, and a second value to indicate that the instructions are not allowed to access the memory external of the protected memory area. In response to creating the protected memory area, the indication is modified from the first value to the second value to restrict the instructions when executed from accessing the memory external of the protected memory area. In response to modifying the indication, code in the computing device is launched, the launched code comprising the operating system or firmware.

Abstract: The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory; the flash controller is used to divide the user area into a first sub-area and a second sub-area; the method comprising: when the instruction bus accesses the user area, determining, whether the instruction bus accesses the first sub-area; if yes, entering the first sub-area working state; in the first sub-area working state, if the instruction bus accesses the second sub-area, entering the transition state; determining whether the time at transition state reaches a preset waiting time; if yes, entering the second sub-area working state; the disclosure is used to protect program from being stolen by users and prevent the cooperative companies stealing program from each other.

Abstract: A display apparatus including a display that displays messages includes a message retrieval unit that retrieves messages by accessing a message management server, a display method selection unit that selects a display method for the retrieved messages in response to a count of the retrieved messages, and a display controller that performs control to display on the display the messages retrieved from the message management server in the display method selected by the display method selection unit. The display method selection unit selects a first display method that displays the retrieved messages while scrolling the retrieved messages repeatedly if the count of the retrieved messages is equal to or below a display switching threshold value, and selects a second display method that displays the retrieved messages while scrolling the retrieved messages if the count of the retrieved messages is above the display switching threshold value.

Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.

Abstract: Methods and apparatus relating to the transfer of data for processing and/or the transfer of the resulting processed data are described. Some features relate to a processing system which performs data transfers under control of a Dynamic Sequence Controller (DSC). In various embodiments a sequence of operational codes is used to control data transfer with the status of data source and destination locations taken into consideration. Modification of the op code sequence used to control the dynamic sequence controller and thus the transfer of data can be performed asynchronously to control of processing units which can be controlled via a command and control bus used to control the function of operators which process the data provided via the data bus.

Abstract: A data storage system includes a host having a write buffer, a memory region, a submission queue and a driver therein. The driver is configured to: (i) transfer data from the write buffer to the memory region in response to a write command, (ii) generate a write command completion notice; and (iii) send at least an address of the data in the memory region to the submission queue. The host may also be configured to transfer the address to a storage device external to the host, and the storage device may use the address during an operation to transfer the data in the memory region to the storage device.

Abstract: A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.

Abstract: A microcomputer includes: a central processing unit (CPU); a data transfer apparatus (DTC); and a storage apparatus (RAM). The data transfer apparatus includes a plurality of register files each including a mode register storing the transfer mode information, an address register to which the address information is transferred, and a status register (SR) representing information that specifies the transfer information set. The data transfer apparatus checks the information of the status register, to determine whether to use the transfer information set held in the register files or to read the transfer information set from the storage apparatus and to rewrite a prescribed one of the register files. The data transfer apparatus performs data transfer based on the transfer information set stored in one of the register files.

Abstract: Processing an adaptive interrupt includes selectively setting an input/output (I/O) device in a computing system to an adaptive masking mode when at least one factor value of the at least one I/O device regarding a workload of the computing system exceeds a first threshold condition. Processing the adaptive interrupt further includes performing an interrupt masking process, where an interrupts generated by an I/O device set to the adaptive masking mode are prevented from being output when a time interval between I/O submission events of the I/O device is less than a first threshold value. The adaptive interrupt may be processed by an adaptive interrupt processing module (AIPM). The AIPM may be included in various portions of the computing system, including the I/O device and a host connected to the I/O device.

Abstract: The invention relates to a bus participant device (30) for receiving and transmitting data telegrams (18) via a serial data bus (12) according to a master/slave method, wherein the bus participant device (30) is configured to function, in a slave mode, as a slave (16) on the data bus (12) by means of a slave unit (36) that is part of the bus participant device (30), wherein the bus participant device (30) comprises a master unit (38) that can be activated. In particular, by means of the slave unit (36) and/or the master unit (38), a transmission of data telegrams (18) via the data bus (12) can be monitored for a malfunction of an active bus master (14). Preferably, subject to a result of the monitoring process, an activation of the master unit (38) by means of the slave unit (36) or the master unit (38) can be effected. The invention further relates to a method for operating a serial data bus (12), and to various safety-critical devices.

Abstract: A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.

Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.

Abstract: The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.

Abstract: This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control unit and a USB interface, and includes the steps of: detecting a voltage of a configuration channel pin of the USB interface to generate a detection signal; determining whether the USB control unit and the USB interface are connected according to the detection signal; and performing an audio signal processing procedure when the USB control unit and the USB interface are not connected.

Abstract: A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a first queue and a second queue. The memory management unit may be configured to buffer first cells for transmission. The egress cell circuit may be configured to queue the first cells from the memory management unit in the first queue, queue second cells from an off-chip memory management unit of another device in the second queue, and schedule the first cells from the first queue and second cells from the second queue for transmission via an egress processor. The egress processor may be configured to transmit the first and second cells over at least one first port.

Abstract: The present disclosure provides a method and system for dynamically migrating a port in a PCIe switch. The PCIe switch comprises emulated P2P bridges stored in a memory and a processor to load the emulated P2P bridge address range values from the memory to a routing table. The processor can configure the routing table so that the P2P bridges can be remapped to various physical ports of the switch. Therefore, a device connected to a physical port may be migrated from one host to another, via the operations of the processor.

Abstract: An input/output (I/O) device includes a management controller interface, a plurality of network switching interfaces, a storage interface, a component controller interface, and a plurality of multifunction modules. The multifunction modules further include a processing node interface, a first endpoint coupled to the management controller interface, a second endpoint coupled to one of the plurality of network switching interfaces, a third endpoint coupled to a remote direct memory access (RDMA) block, a fourth endpoint coupled to the storage interface, and a fifth endpoint coupled to the component controller interface.

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.

Abstract: A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.

Abstract: Methods and devices for controlling frequency of a bus are disclosed. A method may include determining a total-pending load value indicative of a number of a bytes that will pass through the bus in the future and calculating an expected load value based upon i) the total-pending load value, ii) a number of bytes that passed through the bus during a prior time window, and iii) a time duration the bus was active during the prior time window. The frequency of the bus is decreased if the expected load value is less than a lower threshold and increased if the expected load value is greater than an upper threshold. A frequency of the bus is maintained if the expected load value is greater than the lower threshold and less than the upper threshold.

Abstract: A smart harness may comprise a connector configured to selectively plug into and be removable from an Electronic Control Unit (“ECU”) of a vehicle, a first On-Board Diagnostics device (“first OBD device”), and a second On-Board Diagnostics device (“second OBD device”). The smart harness may further comprise at least one transceiver configured to receive and send diagnostic information between the ECU and the first OBD device and the second OBD device. The smart harness may further comprise a processor and a memory having a program communicatively connected to the processor.

Abstract: Apparatus and methods for digital bus operation. In one embodiment, the digital bus is a bidirectional, time-division multiplexing (TDM) audio bus operation, and a bus technology is described that enables multi-drop (e.g., multiple device, multiple node, etc.) connectivity for real-time audio over a small form factor interface (e.g., as few as two (2) wires). Specifically, an exemplary tri-level signaling scheme provides bidirectional functionality, real-time clock edges, audio data, in a multi-drop topology in one implementation.

Abstract: Methods and apparatus for enabling rapid transactions over a speed limited bus are disclosed. In one exemplary embodiment of the present disclosure, a host controller and an application specific integrated circuit (ASIC) are connected via an Inter-Integrated Circuit (I2C) Bus that is further adapted to enable a simplified signaling scheme. Unlike traditional I2C bus transactions which are flexible but speed limited, the simplified signaling scheme reduces bus overhead and enables rapid transactions. In an exemplary context, the simplified signaling scheme enables the ASIC to rapidly configure a series of photodiodes with different channel gain parameters so as to, for example, measure heartbeats by visually detecting a pulse within human flesh.

Abstract: To provide a serial communication system that can flexibly or easily change a system configuration. For example, when coupled to first and second serial buses, a motor module transmits a first signal to the second serial bus. Subsequently, the motor module transmits a first command containing a candidate address to the first serial bus; meanwhile, the motor module searches for an address where an acknowledgement is not received in response to the first command. The motor module transmits the search result address to the second serial bus. A control unit at the reception of the first signal changes to a sleep state that stops communications with the first serial bus and receives an address as a search result from the second serial bus.

Abstract: A multisite sensing system including two or more analyte sensors, an interface device, and a shared bus. The interface device may be configured to receive a power signal and generate power for powering the analyte sensors and to convey data signals generated by the analyte sensors. The shared bus connected to the interface device and each of the analyte sensors and configured to provide the power generated by the interface device to the analyte sensors and to provide the data signals generated by the analyte sensors to the interface device. The interface device may be an inductive element. The shared bus may be a two wire, multiplexed bus. The analyte sensors may be spatially separated for analyte sensing at least two different locations. The analyte sensors may generate data signals indicative of the presence and/or amount of the same analyte or of one or more different analytes.

Abstract: A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

Abstract: An object of the invention is to provide a majority circuit which may be manufactured cheaply and easily and may process necessary majority functions for calculation in an interaction model. The majority circuit according to the invention simplifies the processing of the majority function by using a bitonic sort circuit to round the sum of input signals to a power of 2.

Abstract: Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. mobile devices) which have limited processing resources. At each of a set of predetermined interpolation positions within an array of data points, a set of predetermined weights represent a bicubic interpolation which can be applied to the data points. For a plurality of the predetermined interpolation positions which surround the sampling position, the corresponding sets of predetermined weights and the data points are used to determine a plurality of surrounding interpolated values which represent results of performing the bicubic interpolation at the surrounding predetermined interpolation positions.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media for graphically indicating text continuity. One method includes receiving text including a first line of text followed by a second line of text followed by a third line of text and selecting a distinct line beginning and line end of each of the first, second, and third lines of text. The method further includes formatting the text, including setting respective first attribute values for a first appearance attribute, so that, with respect to the first appearance attribute, the text has a continuity of visual appearance from the first line end to the second line beginning, and so that, with respect to the first appearance attribute, no continuity of visual appearance exists from the first line end to either the first line beginning or to the third line beginning, and presenting the formatted text on the output device.

Abstract: A system and method to view, edit, share, and organize files using software in the form of a computing application for a computing device, allowing a user to keep annotations directly on a document that may be transferred between updates. This allows multiple users to work on one project and share edits no matter where they are or what device they are using.

Abstract: When a browsing computer navigates to a network document, such as a web page, the corresponding server also downloads computer readable formatting information necessary for the operating system of the browsing computer to render correctly any characters within the network document even if the fonts associated with those characters do not exist on the browsing computer prior to encountering the network document. An exposure module is also downloaded to the browsing computer. The exposure module is loaded onto the browsing computer, which in turn either permanently installs or temporarily exposes the operating system of the browsing computer to the computer readable font formatting information associated with the network document. As a result, the operating system of the browsing computer is able to display or otherwise process the network document correctly and consistently regardless of the computer readable fonts installed on the browsing computer.

Abstract: A device including a processor and a memory communicatively coupled to the processor is provided. The memory stores instructions causing the processor, after execution of the instructions by the processor, to: display a reference page number with each displayed page of a digital document having reference page numbers, the digital document corresponding to a reference document having page numbers that correspond to the reference page numbers; and display a fractional page number with each displayed page of the digital document, each fractional page number corresponding to a portion of a page of the reference document.

Abstract: A system for providing a graphical interface to a user includes a server platform and an operating system and application software running thereon. The system includes a client device capable of running a standard web browser that accesses the software application on the server platform for displaying information to the user in a display area on the client device. The web browser displays the information without requiring additional software to be installed, downloaded or run on the client device, and without requiring a scripting language to be enabled in the web browser on the client. The application software facilitates user manipulation of unstructured data in the display area for detailed inspection, and facilitates the user selectively causing to display annotations within the display area. The application software facilitates the user inserting annotations within the display area, thereby causing an action to occur in this system or an external system.

Abstract: Information about named entities referenced in an electronic book (ebook) is provided to a client device. An ebook identifier identifying the ebook is received from the client device. A set of layers available for use with the ebook is determined. The layers in the set provide information associated with the ebook and a layer in the set provides information associated with named entities referenced in content of the ebook. A content range identifying a range of content of the ebook for which layer information is requested and an identification of one or more of the layers in the set for which layer information is requested is received from the client device. Layer information associated with the ebook content identified by the content range for the identified layers is transmitted to the client device. The transmitted layer information includes information associated with named entities referenced by ebook content.

Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving a common schema definition language (CSDL) document that describes an Internet-accessible service, processing the CSDL document through a CSDL parser to provide a CSDL object document, processing the CSDL object document through a text document generator to provide a human-readable text document, and transmitting the human-readable text document for display to a user.

Abstract: Provided are methods, devices, and computer-readable media for generating a string of characters based on a set of rules; parsing the string of characters into string of graphemes; determining one or more phonetic representations for one or more graphemes in the string of graphemes based on a first data structure; determining at least one grapheme representation for one or more of the one or more phonetic representations based on a second data structure; and constructing the phonetic representation of the string of characters based on the grapheme representation that was determined.

Abstract: Memory conserving versioning of an electronic document is provided. Client versioning factors are analyzed by a client versioning engine and server versioning factors are analyzed by a server versioning engine for determining when an electronic document should be stored as a new version. Accordingly, new versions of an electronic document are only created when determined to be sufficiently important, thus reducing the amount of memory required for increased version payload.