Abstract: In an embodiment, photoelectric conversion units (10) each include a package (12) accommodating a photoelectric conversion device (11). The package (12) has a front surface (12a) having a window (13); and a side surface (12c). The package (12) includes a first coupling portion (14) protruding from the side surface (12c) in a first direction X parallel to a light incident surface (11a) of the photoelectric conversion device (11), and a second coupling portion (15) recessed from the side surface (12c) in the first direction X. The first coupling portion (14) includes a first terminal (16) electrically connected with the photoelectric conversion device (11), and the second coupling portion (15) includes a second terminal (17) electrically connected with the photoelectric conversion device (11). The first coupling portion (14) and the second coupling portion (15) have shapes and sizes matching each other, and are coupled with each other by fitting.

Abstract: An avalanche photodiode (APD) array with reduced cross talk comprises, in the illustrative embodiment, a 2D array of Geiger-mode APDs, wherein a via is formed through the backside (substrate) of each APD in the array.

Abstract: A semiconductor photodiode, including a light-absorbing layer; an optical waveguide via which light can evanescently be coupled into the light-absorbing layer, and a doped contact layer arranged between the light-absorbing layer and the optical waveguide. The optical waveguide at least sectionally has a doping which produces a diffusion barrier counteracting a diffusion of dopant of the contact layer into the optical waveguide.

Abstract: A lateral Ge/Si APD constructed on a silicon-on-insulator wafer includes a silicon device layer having regions that are doped to provide a lateral electric field and an avalanche region. A region having a modest doping level is in contact with a germanium body. There are no metal contacts made to the germanium body. The electrical contacts to the germanium body are made by way of the doped regions in the silicon device layer.

Abstract: An optical sensor module has a light receiver and a light-emitter which is surrounded by a light blocking wall, wherein the light receiver is disposed on a main plate and the light-emitter is disposed on a side plate separately from the main plate. The light blocking wall is formed as a light barrier wall between the light receiver and the light-emitter. A projecting portion projecting upward from the main plate is enclosed by the light barrier wall, and a top face of the projecting portion is higher than the light receiving face and the light-emitting face.

Abstract: A method of manufacturing a solar cell includes: forming a solar cell substrate having one main surface and the other main surface and having a p-type surface and an n-type surface which are exposed on one region and another region in the one main surface, respectively; forming seed layers in an electrically separated state on the p-type surface and the n-type surface, respectively; and forming a plated film on the seed layer on each of the p-type surface and the n-type surface by an electrolytic plating method.

Abstract: A method for manufacturing a solar cell is disclosed. The disclosed method includes conductive region formation of forming a first-conduction-type region at one surface of a semiconductor substrate and a second-conduction-type region at another surface of the semiconductor substrate, and electrode formation of forming a first electrode connected to the first-conduction-type region and a second electrode connected to the second-conduction-type region. In the conductive region formation, the first-conduction-type region is formed by forming a dopant layer containing a first-conduction-type dopant over the one surface of the semiconductor substrate, and heat-treating the dopant layer, and the second-conduction-type region is formed by ion-implanting a second-conduction-type dopant into the semiconductor substrate at the another surface of the semiconductor substrate.

Abstract: The present invention relates to a novel process for the preparation of printable, high-viscosity oxide media, and to the use thereof in the production of solar cells.

Abstract: A method for producing a multiplicity of semiconductor chips (13) is provided, comprising the following steps: —providing a wafer (1) comprising a multiplicity of semiconductor bodies (2), wherein separating lines (9) are arranged between the semiconductor bodies (2), —depositing a contact layer (10) on the wafer (1), wherein the material of the contact layer (10) is chosen from the following group: platinum, rhodium, palladium, gold, and the contact layer (10) has a thickness of between 8 nanometers and 250 nanometers, inclusive, —applying the wafer (1) to a film (11), —at least partially severing the wafer (1) in the vertical direction along the separating lines (9) or introducing fracture nuclei (12) into the wafer (1) along the separating lines (9), and —breaking the wafer (1) along the separating lines (9) or expanding the film (11) such that a spatial separation of the semiconductor chips (13) takes place, wherein the contact layer (10) is also separated.

Abstract: A light-emitting element includes: a sapphire substrate including: a principal surface that is in a c-plane of the sapphire substrate, and a plurality of projections on the principal surface, wherein each of the plurality of projections has a shape of pseudo-hexagonal pyramid including six lateral surfaces, each of the six lateral surfaces including an inwardly curved surface portion, and wherein, in a top view of the sapphire substrate, each of the plurality of projections has a shape of a pseudo-hexagon; and a semiconductor layered body comprising a nitride semiconductor on the principal surface side of the sapphire substrate, the semiconductor layered body including an active layer.

Abstract: A method for wafer to wafer bonding for III-V and CMOS wafers is provided. A silicon carrier wafer is provided having an epitaxial III-V semiconductor region and an oxide region disposed over the wafer top surface, the regions having substantially equal heights. A sidewall of the epitaxial III-V semiconductor region directly contacts a sidewall of the oxide region. A eutectic bonding layer is formed over a top surface of the epitaxial III-V semiconductor region and the oxide region for bonding to the CMOS wafer which contains semiconductor devices. The silicon carrier wafer is removed, and the CMOS wafer is singulated to form a plurality of three-dimensional integrated circuits, each including a CMOS substrate corresponding to a portion of the CMOS wafer and a III-V optical device corresponding to a portion of the III-V epitaxial semiconductor region.

Abstract: A manufacturing method of light-emitting device is disclosed. The method includes providing an LED wafer comprising a substrate and a semiconductor stack formed on the substrate, wherein the semiconductor stack has a lower surface facing the substrate and an upper surface opposite to the lower surface; providing a first laser to the LED wafer and irradiating the LED wafer from the upper surface to form a plurality of scribing lines on the upper surface; providing and focusing a second laser on an interior of the substrate to form a plurality of textured areas in the substrate; and providing force on the LED wafer to separate the LED wafer into a plurality of LED chips.

Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein a convex region or a concave region is formed by the first deteriorated surface, the first crack surface and the second crack surface, or the second deteriorated surface, the first crack surface and the third crack surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.

Abstract: An improved light emitting heterostructure is provided. The heterostructure includes an active region having a set of barrier layers and a set of quantum wells, each of which is adjoined by a barrier layer. The quantum wells have a delta doped p-type sub-layer located therein, which results in a change of the band structure of the quantum well. The change can reduce the effects of polarization in the quantum wells, which can provide improved light emission from the active region.

Abstract: A semiconductor light emitting device including a first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer; an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, the active layer including at least one quantum well layer and at least one quantum barrier layer that are alternately stacked and form a multiple quantum well structure; at least one border layer in contact with the first conductivity-type semiconductor layer and interposed between the first conductivity-type semiconductor layer and the active layer, the at least one border layer having a band gap energy that decreases in a direction away from the first conductivity-type semiconductor layer; and at least one growth blocking layer interposed between the active layer and the border layer, the at least one growth blocking layer having a band gap energy equal to a band gap energy of the at least one quantum barrier layer.

Abstract: A ?LED including an epitaxial stacked layer, a first electrode and a second electrode is provided. The epitaxial stacked layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. The epitaxial stacked layer has a first mesa portion and a second mesa portion to form a first type conductive region and a second type conductive region respectively. The first electrode is disposed on the first mesa portion. The second electrode is disposed on the second mesa portion. The second electrode contacts the first type doped semiconductor layer, the light emitting layer and the second type doped semiconductor layer located at the second mesa portion. Moreover, a manufacturing method of the ?LED is also provided.

Abstract: A method of manufacturing a light emitting device includes preparing a wafer having a sapphire substrate with semiconductor structures, forming a plurality of straight-line cleavage starting portions within the substrate by scanning a laser beam, and cleaving the wafer along the cleavage starting portions to obtain a plurality of light emitting devices each having a hexagonal shape. The forming step includes forming first cleavage starting portions with each first cleavage starting portion separated by a first interval from a common vertex point of three adjacent light emitting devices, forming second cleavage starting portions with each first cleavage starting portion separated by a second interval, which is shorter than the first interval, away from the common vertex point, and forming third cleavage starting portions with each first cleavage starting portion separated by a third interval, which is shorter than the first interval, away from the common vertex point.

Abstract: The invention relates to a light emitting device, a manufacturing method thereof and a display device. The light emitting device comprises: a substrate, and a first electrode layer, a second electrode layer and a light emitting layer arranged above the substrate, the light emitting layer being disposed between the first electrode layer and the second electrode layer, the light emitting layer comprises a hole transport layer having a first thickness which is capable of avoiding performance degradation of the light emitting device.

Abstract: A light emitting device package is provided. The light emitting device package includes a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.

Abstract: A light emitting element for flip-chip mounting having a flat mounting surface which allows a decrease in the width of the streets of a wafer. In the light emitting element, the insulating member filling around the bumps and flattening the upper surface is formed with a margin of a region with a width which is equal to or larger than the width of the streets on the dividing lines, so that at the time of dividing the wafer along the dividing lines, the insulating member is not processed, which allows designing of the streets with a small width.

Abstract: A light emitting element includes a semiconductor stacked body, an oxide film, and a reflecting film. The semiconductor stacked body has a body surface. The oxide film has an upper surface and a bottom surface opposite to the upper surface. The oxide film is provided on the semiconductor stacked body such that the bottom surface of the oxide film is opposite to the body surface of the semiconductor stacked body. The reflecting film is provided on the oxide film to be in contact with the upper surface of the oxide film and includes silver and oxide nanoparticles.

Abstract: A light emitting diode includes a support substrate; a light emitting structure including a second semiconductor layer, an active layer, and a first semiconductor layer; at least one groove formed on the lower surface of the light emitting structure; a second electrode located on at least the lower surface of the second semiconductor layer, and electrically connected with the second semiconductor layer; an insulating layer partially covering the second electrode and the lower surface of the light emitting structure, and including at least one opening corresponding to the at least one groove; and a first electrode electrically connected to the first semiconductor layer exposed to the at least one groove, and at least partially covering the insulating layer, wherein the second electrode includes a second contact layer including an ohmic contact layer, and the ohmic contact layer is disposed in the shape of a plurality of islands.

Abstract: A surface-mountable optoelectronic semiconductor component is specified. The surface-mountable optoelectronic semiconductor component includes an optoelectronic semiconductor chip, a radiation-transmissive growth substrate, a housing body and an electrically conductive connection. The housing body is arranged at least in places between a side surface of the growth substrate and the electrically conductive connection. The housing body completely covers all of the side surfaces of the growth substrate, and the housing body has, on a surface facing away from the side surface of the growth substrate, traces of material removal or traces of a form tool.

Abstract: A phosphor layer contains phosphor particles, and satisfies the following relations: y?0.0623x2+0.2107x+28.789 and y??0.1172x2+7.584x+81.148 where x represents the average particle size (?m) of the phosphor particles, and y represents the thickness (?m) of the phosphor layer.

Abstract: A light emitting device includes a first phosphor emitting a fluorescence having a peak emission wavelength of not less than 445 nm and not more than 490 nm, a second phosphor emitting a fluorescence having a peak emission wavelength of not less than 491 nm and not more than 600 nm, a third phosphor emitting a fluorescence having a peak emission wavelength of not less than 601 nm and not more than 670 nm, and a light emitting element that emits a light having a peak emission wavelength at a shorter wavelength side than the peak emission wavelength of the first phosphor. 0.586?x?0.734, 0.017?y?0.081, 0.239?z?0.384 and x+y+z=1 are satisfied, where x, y, z are defined as mass ratios of the first, second and third phosphors, respectively, to a total mass of the first, second and third phosphors.

Abstract: In at least one embodiment, the semiconductor layering sequence (1) is designed for generating light and comprises semiconductor columns (2). The semiconductor columns (2) have a respective core (21) made of a semiconductor material of a first conductivity type, and a core shell (23) surrounding the core (21) made of a semiconductor material of a second conductivity type. There is an active zone (22) between the core (21) and the core shell (23) for generating a primary radiation by means of electroluminescence. A respective conversion shell (4) is placed onto the semiconductor columns (2), which conversion shell at least partially interlockingly surrounds the corresponding core shell (23), and which at least partially absorbs the primary radiation and converts same into a secondary radiation of a longer wavelength by means of photoluminescence. The conversion shells (4) which are applied to adjacent semiconductor columns (2), only incompletely fill an intermediate space between the semiconductor columns (2).

Abstract: Submount based surface mount design (SMD) light emitter components and related methods are disclosed. In one aspect, a method of providing a submount based light emitter component can include providing a ceramic based submount, providing at least one light emitter chip on the submount, providing at least one electrical contact on a portion of the submount, and providing a non-ceramic based reflector cavity on a portion of the submount.

Abstract: Provided is a quantum dot LED package structure comprising a bottom bracket, an external bracket, a quantum dot layer light emitting chip, an inorganic barrier layer and a top silica gel layer, wherein the inorganic barrier layer covers the external bracket and the quantum dot layer light emitting chip on the bottom bracket to package the external bracket and the quantum dot layer light emitting chip; the external bracket and the quantum dot layer light emitting chip are packaged by using the inorganic barrier layer, and a top silica gel layer is provided on the inorganic barrier layer, and the water and oxygen barrier condition that the existing package structure simply using the silica gel layer cannot meet can be satisfied and good heat dissipation can be provided. Thus, the issues of mass production difficulty, high cost, low luminous efficiency, difficulty to achieve narrow border application can be solved.

Abstract: A package structure of an ultraviolet light emitting diode is provided, which includes a substrate, a transparent body, at least one ultraviolet light emitting diode, a connecting element and an ultraviolet shielding layer. The transparent body is disposed on the substrate. The transparent body has a space inside thereof. The at least one ultraviolet light emitting diode is disposed on the substrate and inside the space. The connecting element is disposed between the substrate and the transparent body. The ultraviolet shielding layer is disposed between the transparent body and the connecting element.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: A light emitting device includes a first substrate including a flexible first base member and a first wiring pattern provided on the first base member; a second substrate including a second base member and a second wiring pattern provided on the second base member; and a plurality of light emitting elements mounted on the first wiring pattern. The first substrate includes: a joining end portion that is located at a first, joining end of the first substrate, and that overlaps a portion of the second substrate, and a second end, other than the joining end, that does not overlap the second substrate. The first wiring pattern and the second wiring pattern do not face each other. An electrically conductive joining member is disposed across the first wiring pattern and the second wiring pattern, while partially covering the joining end portion of the first substrate.

Abstract: A light-emitting device includes first and second lead frames spaced apart from each other, the first and second lead frames each including a top surface, an opposing bottom surface, and sidewalls arranged between the top surface and the bottom surface thereof, in which at least one of the first and second lead frames include three inset sidewalls that at least partially define a fixing space, the fixing space undercutting at least one of the first lead frame and second lead frame, a light-emitting diode chip disposed on the top surface of the first or second lead frame, and the top surfaces of the first and second lead frames are substantially flat.

Abstract: Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile.

Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Abstract: In the present disclosure, disclosed are a novel compound semiconductor which can be used as a thermoelectric material or the like, and applications thereof. A compound semiconductor according to the present disclosure can be represented by the following chemical formula 1: <Chemical formula 1>[Bi1-xMxCuu-wTwOa-yQ1yTebSez]Ac, where, in the chemical formula 1, M is one or more elements selected from the group consisting of Ba, Sr, Ca, Mg, Cs, K, Na, Cd, Hg, Sn, Pb, Mn, Ga, In, Tl, As and Sb; Q1 is one or more elements selected from the group consisting of S, Se, As and Sb; T is one or more elements selected from transition metal elements; A is one or more elements selected from the group consisting of transition metal elements and compounds of transition metal elements and group VI elements; and 0?x<1, 0.5?u?1.5, 0?w?1, 0.2<a<1.5, 0?y<1.5, 0?b<1.5, 0?z<1.5 and 0<c<0.2.

Abstract: A thermoelectric converter includes a first substrate that is deformable, a second substrate that is deformable, a plurality of thermoelectric conversion elements, and a group of electrodes. The plurality of thermoelectric conversion elements are disposed between the first substrate and the second substrate. The group of electrodes electrically interconnect the plurality of thermoelectric conversion elements. The plurality of thermoelectric conversion elements are arranged in a plurality of rows. The group of electrodes include a bridge electrode disposed across a first row and a second row among the plurality of rows. The first row is adjacent to the second row. The bridge electrode has a first part whose thickness is smaller than a thickness of each of remaining electrodes other than the bridge electrode among the group of electrodes and whose surface area is larger than a surface area of each of the remaining electrodes.

Abstract: A cryogenic quantum bit package with multiple qubit circuits facilitates inter-qubit signal propagation using a multi-chip module (MCM). Multiple qubits are grouped within the package into one or more qubit integrated circuits (ICs). The qubit ICs themselves are electrically coupled to each other via a structure including a superconducting MCM and superconducting interconnects. Coupling of quantum electrical signals between a qubit and other qubits, a substrate, or the MCM uses a coupler circuit, such as a Josephson junction, capacitor, inductor, or resonator.

Abstract: The present application relates to the technical field of transducer, it provides an ultrasonic transducer and the manufacture method therefore. The ultrasonic transducer comprises: a piezoelectric layer for radiating sound signal forward or backward, each side thereof being plated with an electrode; a matching layer arranged in the front of the piezoelectric layer and suitable for sending the forward sound signal; a tuning layer arranged on the back of the piezoelectric layer, wherein the piezoelectric layer is disposed between the tuning layer and the matching layer; a backing layer for absorbing the backward sound signal from the piezoelectric layer, wherein the backing layer is arranged against the piezoelectric layer on the tuning layer.

Abstract: A method for identifying an overcurrent when charging a piezo actuator, by periodically connecting and disconnecting the piezo actuator to and from an energy source via a charging coil. A connection is followed by a disconnection when the charging current has reached a prescribed maximum current value and a minimum switched-on time has elapsed, and a connection is effected again when either a prescribed minimum current value has been reached or a maximum switched-off time has elapsed. An overcurrent is identified when a disconnection is effected when the minimum switched-on time has elapsed and the charging current has previously reached or exceeded a prescribed maximum current value. An overcurrent is also identified when, after a disconnection on account of the prescribed maximum current value having been reached, a connection is effected again when the maximum switched-off time has elapsed without the minimum current value having been reached.

Abstract: An electromechanical actuator includes an oscillation resonator having the shape of a rod. The oscillation resonator is divided by a dividing plane that is not parallel to the longitudinal direction of the oscillation resonator into a first resonator portion and a second resonator portion. At least the first resonator portion includes electromechanical means which, when activated, are configured to generate a 3-dimensional acoustic bulk wave are with a mode shape asymmetric with respect to the dividing plane.

Abstract: The piezoelectric body is configured to have a layered structure such that a plurality of unit layers are stacked in a film thickness direction, and each of the unit layers is formed of a first layer on which the displacement is relatively easy to occur, and a second layer which has a high concentration of Zr as compared with the first layer. In addition, when composition ratio Ti/(Zr+Ti) of Zr to Ti in each of the first layer and the second layer is set as Cr1 and Cr2, the composition ratio of each layer is adjusted so as to satisfy the following conditions (1) to (3): 0.41?Cr1?0.81??(1) 0.1?Cr1?Cr2?0.3??(2) Cr1>Cr2??(3).

Abstract: A piezoelectric element has, from a substrate side, a first electrode, a piezoelectric layer containing a composite oxide of an ABO3 type perovskite structure containing Mg, and a second electrode, which are laminated, in which the first electrode includes a diffusion suppressing layer which suppresses diffusion of the Mg and a diffusion layer which diffuses the Mg as compared with the diffusion suppressing layer, and the diffusion suppressing layer is provided on the substrate side relative to the diffusion layer.

Abstract: A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a tantalum portion, and a ruthenium portion overlying the platinum portion. The magnetic cell structure comprises a magnetic region overlying the seed material, an insulating material overlying the magnetic region, and another magnetic region overlying the insulating material. Semiconductor devices including the magnetic cell structure, methods of forming the magnetic cell structure and the semiconductor devices are also disclosed.

Abstract: A spintronic device is disclosed. The spintronic device includes a spin current transport layer, a spin injector, and a spin detector. The spin injector includes a first tunnel barrier layer made of strontium oxide (SrO) disposed over the spin current transport layer and a first magnetic material layer disposed over the first tunnel barrier layer. The spin detector includes a second tunnel barrier layer made of SrO disposed over the spin current transport layer. A second magnetic material layer is disposed over the second tunnel barrier layer and a spin sensor has a sensor input terminal coupled to the second magnetic material layer.

Abstract: In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.

Abstract: A magnetic tunnel junction (MTJ) that avoids electrical shorts and has improved data retention is disclosed. An uppermost capping layer has a first sidewall that is coplanar with an interface between outer oxidized portions and a center ferromagnetic portion of a free layer (FL) that has a FL width (FLW). A dielectric spacer is formed on the first sidewall and oxidized outer FL portions. The pinned layer (PL) has a width (PLW) substantially greater than FLW, and a second sidewall thereon is formed by a self-aligned etch using the dielectric spacer and capping layer as an etch mask. A sidewall layer may be formed on the second sidewall and dielectric spacer but does not degrade MTJ properties since the sidewall layer does not contact the FL and PL center portions responsible for device performance. PL width>FLW ensures greater capability for data retention especially for FLW<60 nm.

Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.

Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device.

Abstract: Providing an electrode for a two-terminal memory device is described herein. By way of example, the electrode can comprise a contact surface that comprises at least one surface discontinuity. For instance, the electrode can have a gap, break, or other discontinuous portion of a surface that makes electrical contact with another component of the two-terminal memory device. In one example, the contact surface can comprise an annulus or an approximation of an annulus, having a discontinuity within a center of the annulus, for instance. In some embodiments, a disclosed electrode can be formed from a conductive layer deposited over a non-continuous surface formed by a via or trench in an insulator, or over a pillar device formed from or on the insulator.