Abstract: The present application provides a method and device for processing audio in a captured scene including an image and spatially localizable audio. The method includes capturing a scene including image information and spatially localizable audio information. The captured image information of the scene is then presented to a user via an image reproduction module. An object in the presented image information is then selected, which is the source of spatially localizable audio information, by isolating the spatially localizable audio information in the direction of the selected object. The isolated spatially localizable audio information is then altered.

Abstract: A system is described for maintaining synchrony of operations among a plurality of devices that have independent clocking arrangements. The system includes a task distribution device that distributes tasks to a synchrony group comprising a plurality of devices that are to perform the tasks distributed by the task distribution device in synchrony. The task distribution device distributes each task to the members of the synchrony group over a network. Each task is associated with a time stamp that indicates a time, relative to a clock maintained by the task distribution device, at which the members of the synchrony group are to execute the task.

Abstract: An electronic device may comprise audio processing circuitry, pace tracking circuitry, and positioning circuitry. The pace tracking circuitry may be operable to selects songs to be processed for playback, and/or control time stretching applied to such songs, by the audio processing circuitry based on position data generated by the positioning circuitry, a desired tempo, and whether the songs are stored locally or network-accessible. The position data may indicate the pace of a runner during a preceding, determined time interval. The pace tracking circuitry may control the song selection and/or time stretching based on a runner profile data stored in memory of the music device. The profile data may include runner's distance-per-stride data. The electronic device may include sensors operable to function as a pedometer. The pace tracking circuitry may update the distance-per-stride data based on the position data and based on data output by the one or more sensors.

Abstract: A context aware service provision method and apparatus for recognizing the user context and executing an action corresponding to the user context according to a rule defined by the user and feeding back the execution result to the user interactively are provided. The method for providing a context-aware service includes receiving a user input, the user input being at least one of a text input and a speech input, identifying a rule including a condition and an action corresponding to the condition based on the received user input, activating the rule to detect a context which corresponds to the condition of the rule, and executing, when the context is detected, the action corresponding to the condition.

Abstract: A method for allocating a resource to multiple requesters is disclosed. In one embodiment, such a method includes maintaining, for a resource, a regular queue and an express queue. The method receives requests to control the resource and determines, for each request, an anticipated amount of time that the request needs to control the resource. In the event the anticipated amount of time for a request is greater than a selected threshold, the method allocates the request to the regular queue. In the event the anticipated amount of time for a request is less than the selected threshold, the method allocates the request to the express queue. The method provides priority to requests allocated to the express queue over requests allocated to the regular queue. A corresponding system and computer program product are also disclosed.

Abstract: The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion thereof, a fixed-point or floating-point multiplication operation or a portion thereof, a fixed-point or floating-point multiply-add operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers or a Radix-2 Butterfly circuit, just to name a few.

Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.

Abstract: A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET (metal oxide semiconductor field effect transistor) device and a gate voltage Vg of the MOSFET device so that the MOSFET device comprises a noise source configured in a manner such as to tune as desired a random number statistical distribution of an output of the MOSFET device. An output voltage of the MOSFET is provided as an input signal into a low noise amplifier and an output voltage of the low noise amplifier provides values for a random number generator.

Abstract: A method and system for improving software object definition is provided. The method includes receiving a software object from a hardware and software connector device and parsing top level hierarchal software structures of the software object. The top level hierarchal software structures are mapped to specified software element properties and in response a container memory structure is identified. A search process for the container memory structure is executed and based on the results software building block code is executed thereby modifying the first container memory structure resulting in an improved operation of the hardware and software connector device and the hardware framework system.

Abstract: In some embodiments, a real-time event is detected and context is determined based on the real-time event. An application model is fetched based on the context and meta-data associated with the real-time event, the application model referencing a micro-function and including pre-condition and post-condition descriptors. A graph is constructed based on the micro-function. The micro-function is transformed into micro-capabilities by determining a computing resource for execution of a micro-capability by matching pre-conditions and post-conditions of the micro-capability, and enabling execution and configuration of the micro-capability on the computing resource by providing access in a target environment to an API capable of calling the micro-capability to configure and execute the micro-capability. A request is received from the target environment to execute and configure the micro-capability on the computing resource.

Abstract: Systems and methods are provided for obtaining one or more source code files that correspond to a software program. At least one first software package that is separately executable from the software program is obtained, the first software package including one or more source code files. At least one first callable library for the first software package and at least one first invocation mechanism for calling the first callable library are generated. A composite software program that is capable of invoking at least the software program and the first callable library for the first software package using the first invocation mechanism is generated.

Abstract: A system includes a memory and a semiconductor-based processor coupled to form logic circuits. The logic circuits generate a voice-enabled user interface (UI) framework for a computer application. The voice-enabled UI framework includes a base controller coupled to a model of the computer application and one or more views that form respective voice-enabled UIs of the computer application. Each view includes a respective speech listener configured to receive speech input. The base controller includes a speech engine, a natural language processor, and a command executor. The voice-enabled UI framework further includes one or more view-specific controller extensions extending the base controller to control the one or more respective views that form the respective voice-enabled UIs of the computer application.

Abstract: An aspect includes source code analysis and adjustment. An analysis request is received based on a change detected in a source file. A static analysis of the source file is initiated using a parser to produce a list of named elements and element types based on the source file. Name and pattern recognition is performed by a pattern analyzer based on the list of named elements and element types to identify one or more naming convention inconsistencies in the source file using at least one pattern learned from the source file. A change is suggested to modify at least one named element in the source file based on identifying the one or more naming convention inconsistencies.

Abstract: An aspect includes source code analysis and adjustment. An analysis request is received based on a change detected in a source file. A static analysis of the source file is initiated using a parser to produce a list of named elements and element types based on the source file. Name and pattern recognition is performed by a pattern analyzer based on the list of named elements and element types to identify one or more naming convention inconsistencies in the source file using at least one pattern learned from the source file. A change is suggested to modify at least one named element in the source file based on identifying the one or more naming convention inconsistencies.

Abstract: A data storage device utilized for confirming firmware data includes a flash memory and a controller. The controller is coupled to the flash memory to receive at least one first hash data related to a first firmware data, and it divides the first hash data into a plurality of data groups. The controller sorts the data groups based on a predetermined sorting mechanism to generate a first sorting hash data. The controller includes an efuse region for writing the predetermined sorting mechanism. When the controller determines that a second sorting hash data of a second firmware data is identical to the first sorting hash data or a second hash data of the second firmware data is identical to the first hash data, the second firmware data is allowed to update the controller.

Abstract: One embodiment provides an apparatus. The apparatus includes a processor circuitry; a memory circuitry; and a compile time interface. The compile time interface is to identify, at compile time, a loop that contains a library function in response to detecting a compiler hint associated with the library function. The compile time interface is further to generate a bypass structure and to modify the loop to include a call to a planning function for a first pass through the loop and a call to a bypass function for one or more subsequent passes though the loop, the bypass function defined based on the generated bypass structure.

Abstract: Techniques are provided for identifying and removing one or more layers of a software appliance. Layers may be identified and removed quickly and efficiently, without disrupting the distribution or provisioning of the software appliance, and without disrupting desired operations of the software appliance as a whole. In various implementations, it may be necessary or desirable to re-package the same or modified layer(s) within the software appliance at a later point in the distribution cycle of the software appliance. For example, one or more operating system layers may be identified and removed from a software appliance. Then, when the software appliance is distributed and provisioned in a cloud or other network context, a same or different version of the operating system layer(s) may be utilized in re-packaging the software appliance for one or more customers.

Abstract: Presented herein are methods, non-transitory computer readable media, and devices for provisioning an application within a network storage system, which include: providing an application template; requesting input into the application template to construct the application in the network storage system and receiving the requested input; validating the input using standard templates for known applications stored within the network storage system; determining storage specifications within the network storage system based on the validated input; and creating storage and protocol objects associated with the application that identifies the storage specifications.

Abstract: A software package retention system that uses pre-defined rules to retain software packages based on how the packages are used, and not merely based on a package's date/time of creation (age) or type. A retention policy server in the system integrates with the build, deployments, and artifact storage systems of a software supplier/vendor to ensure appropriate retentions are met for audit and regulatory compliance and unneeded artifacts or packages are purged to save storage space and lower operational costs. The server has the capability to monitor software deployments to the customer and to developer test environments, and to make rule-based decisions on when and how to run retention policy clean-up jobs and on what packages. With increasing reliance on frequent build and release of software packages across the software industry, package management post-release using the rule-based retention policy provides an efficient and cost-effective solution for legal compliance with retention requirements.

Abstract: A method of delivering a user specific customized service to a mobile user device is disclosed. User specific customized service information is received over a first channel. An identifier for the user specific customized service is generated. A link is sent that includes the identifier of the user specific customized service over a second channel. The user specific customized service identifier is received. The user specific customized service over a third channel is sent.

Abstract: A system, method, and computer-readable medium are disclosed for performing a deployment operation, comprising: receiving an application module command request; accessing a metadata repository for application modules to obtain metadata corresponding to the application module; determining whether an application module corresponding to the application module command request is loaded within an application based upon metadata corresponding to the application module; contacting a package manager to download an application module package if the application module is not loaded within the application or an update to the application module exists; loading the application module package; and, providing an invocation to an entry point of the application module.

Abstract: There is provided a software updating device which performs communication with a server device and a plurality of control devices and controls software updating processes of control devices. A writing instruction unit instructs the control devices to write update software transmitted from the server device in second areas provided separately from first areas storing software which is being used. A confirming unit confirms that the update software has been written in the second areas with respect to all of control devices which constitute a cooperating control device group which is the set of control devices cooperating with each other, in the plurality of control devices which are software updating objects. A switching instruction unit instructs all of the control devices constituting the cooperating control device group to perform switching processes of setting the update software written in the second areas as software to be thereafter executed.

Abstract: Various embodiments of systems, computer program products, and methods to provide descriptor-transformer framework in an integration platform are described herein. In an aspect, an instruction to integrate a plurality of applications is received through a web interface application corresponding to the integration platform. A descriptor file associated with connectivity adapters corresponding to the plurality of applications is retrieved. Further, one or more preprocessor steps and/or one or more postprocessor steps are determined by analyzing the descriptor file. The plurality of applications is integrated by executing an integration flow based on the determined one or more preprocessor steps and/or one or more postprocessor steps.

Abstract: Apparatus and method are described for trimming parameters of analog circuits. The apparatus includes trim result registers for storing trim results for adjusting parameters of analog circuits, respectively; a memory device configured to store sets of operands; and a trim calculation unit configured to generate the set of trim results by performing a set of arithmetic operations on the sets of operands based on a set of commands, respectively. The trim calculation unit receives a set of commands; transfers sets of operands from the memory device to a programmable ALU array based on the set of commands, respectively; generates trim results by performing arithmetic operations on the sets of operands based on the set of commands, respectively; and sends the trim results to the trim result registers based on the set of commands, respectively.

Abstract: Methods, systems, and apparatus, including an apparatus for accessing a N-dimensional tensor, the apparatus including, for each dimension of the N-dimensional tensor, a partial address offset value element that stores a partial address offset value for the dimension based at least on an initial value for the dimension, a step value for the dimension, and a number of iterations of a loop for the dimension. The apparatus includes a hardware adder and a processor. The processor obtains an instruction to access a particular element of the N-dimensional tensor. The N-dimensional tensor has multiple elements arranged across each of the N dimensions, where N is an integer that is equal to or greater than one. The processor determines, using the partial address offset value elements and the hardware adder, an address of the particular element and outputs data indicating the determined address for accessing the particular element of the N-dimensional tensor.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

Abstract: It is disclosed a processing arrangement utilizing function capable of efficiently utilizing a processing arrangement and a method performed therein, where the processing arrangement comprises a first and a second physical processing unit, PU, where the first physical PU is adapted to be assigned to a first logical PU. When the first physical PU is turned off, it may be assigned to another logical PU in need to be activated. When the first logical PU needs to be activated, it can be assigned to a second physical PU. A notification is sent to a power management unit to activate the physical PU to which a logical PU is assigned. Embodiments of this disclosure increase the utilization of processing arrangements, taking advantage of statistical multiplexing.

Abstract: Tensor register files in a hardware accelerator are disclosed. An apparatus may comprise tensor operation calculators each configured to perform a type of tensor operation. The apparatus may also comprises tensor register files, each of which is associated with one of the tensor operation calculators. The apparatus may also comprises logic configured to store respective ones of the tensors in the plurality of tensor register files in accordance with the type of tensor operation to be performed on the respective tensors. The apparatus may also control read access to tensor register files based on a type of tensor operation that a machine instruction is to perform.

Abstract: A hardware accelerator having an efficient instruction set is disclosed. An apparatus may comprise logic configured to access a first and a second machine instruction. The second machine instruction may be missing a tensor operand needed to execute the second machine instruction. The logic may be further configured to execute the first machine instruction, resulting in a tensor. The logic may be further configured to execute the second machine instruction using the resultant tensor as the missing tensor operand.

Abstract: In accordance with embodiments of the present disclosure, a system may include a controller configured to control a process value using closed-loop control, wherein: (i) when using closed-loop control, the controller controls the process value based on a measured process value indicative of the process value communicated from a sensor and by generating a driving signal that is a maximum of a first driving signal which is the function of the measured process value and a second driving signal; and (ii) the controller is configured to disable polling by the controller of the sensor for the measured process value when the driving signal is greater than a threshold open-loop driving signal sufficient to maintain the process value within a desired range of the process value in the absence of closed-loop control.

Abstract: A processor circuit is provided that includes an input terminal and an output terminal, a plurality of vector processor operation circuits, a selector circuit coupled to the input terminal, the output terminal, and each of the vector processor operation circuits, and a scheduler circuit adapted to control the selector circuit to configure a vector processing pipeline comprising zero, one or more of the vector processor operation circuits in any order between the input terminal and the output terminal.

Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

Abstract: Systems and methods are disclosed for block-based or Explicit Data Graph Execution (EDGE) processors that can predispatch instructions for a next instruction block before a current instruction block has committed. Instruction state, including instruction scheduler instruction state and other decoded control state can be stored in one or more memories. As individual instructions of a current instruction block issue, instructions for a next instruction block can be fetched, decoded, and the generated instruction state stored in the memory at the now-unused instruction slot locations. The next instruction block can be determined speculatively, or non-speculatively. Prior to committing the first instruction block, the instruction state is stored in one or more of the now-unused instruction slot locations.

Abstract: A method and apparatus are provided. The method includes executing a plurality of threads in a temporal dimension, executing a plurality of threads in a spatial dimension, determining a branch target address for each of the plurality of threads in the temporal dimension and the plurality of threads in the spatial dimension, and comparing each of the branch target addresses to determine a minimum branch target address, wherein the minimum branch target address is a minimum value among branch target addresses of each of the plurality of threads.

Abstract: A method of and system for performing metadata tag compression in security policy enforcement system may comprise conveying a set of data elements, each with an associated metadata tag, from a first processor subsystem to a second processor subsystem. The first processor subsystem may be configured to process conventional tasks, the second processor configured to apply one or more policy decisions to the data element. The conveying may further comprise sending the set of data elements along with an index element that identifies one or more metadata tags, and sending one or more of the metadata tags identified by the index element.

Abstract: Disclosed herein are an apparatus and method for sharing memory between computers. The apparatus for sharing memory between computers includes multiple memory adapters, installed in corresponding ones of multiple computers, for receiving an address corresponding to an instruction from the computers and transforming the received address into an instruction in the form of a packet; and shared memory for transforming the instruction in the form of the packet, received from the multiple memory adapters, into an address and performing an operation corresponding to the instruction for a memory cell corresponding to the address.

Abstract: A processor device capable of raising a hit rate of branch destination prediction is provided. Every time a load instruction to a data cache is generated, an equivalent value judgment circuit judges accord/disaccord of present load data and previous load data from a corresponding line. In an N bit region, as history records, a judgment history record circuit records judgment results of N times by the equivalent value judgment circuit before a conditional branch instruction is generated. When the conditional branch instruction is generated, based on the history records in the N bit region, a branch prediction circuit predicts the same branch destination as the previous branch destination obtained by a previous execution result of the conditional branch instruction or a branch destination different from the previous destination. Further, the branch prediction circuit issues an instruction fetch direction of the predicted branch destination to a processor main-body circuit.

Abstract: Methods and systems enabling rapid application development, verification, and deployment requiring only knowledge of high level languages. Two aspects of the disclosed methods and systems are called Machine Intelligence and Learning for Graphic chip Accessibility (MILeGrA) and Machine Intelligence and Learning for Graphic chip Execution (MILeGrE). Using MILeGrA and MILeGrE, high-level language programmers do not need to learn complex coprocessor programming languages, but can still use coprocessors (e.g., GPU processors) to benefit from results-in-seconds big data capabilities through the translation of coprocessor-unaware code to coprocessor-aware code. Execution of such coprocessor-unaware code on coprocessors includes parsing the coprocessor-unaware code to generate intermediate code, analyzing the intermediate code to determine a model for coprocessor-aware code generation, and generating coprocessor-aware code based on the model using machine learning techniques.

Abstract: Generally discussed herein are systems, devices, and methods for network security monitoring (NSM). A hardware queue manager (HQM) may include an input interface to receive first data from at least a first worker thread, queue duplication circuitry to generate a copy of at least a portion of the first data to create first copied data, and an output interface to (a) provide the first copied data to a second worker thread, and/or (b) provide at least a portion of the first data to a third worker thread.

Abstract: An accelerator for processing of a convolutional neural network (CNN) includes a compute core having a plurality of compute units. Each compute unit includes a first memory cache configured to store at least one vector in a map trace, a second memory cache configured to store at least one vector in a kernel trace, and a plurality of vector multiply-accumulate units (vMACs) connected to the first and second memory caches. Each vMAC includes a plurality of multiply-accumulate units (MACs). Each MAC includes a multiplier unit configured to multiply a first word that of the at least one vector in the map trace by a second word of the at least one vector in the kernel trace to produce an intermediate product, and an adder unit that adds the intermediate product to a third word to generate a sum of the intermediate product and the third word.

Abstract: A method dynamically reconfigures a system on a chip (SOC) comprising multiple semiconductor intellectual property (IP) blocks. The method comprises, when booting a data processing system (DPS) comprising the SOC, automatically allocating different IP blocks to multiple different microsystems within the DPS, based on a static partitioning policy (SPP). The method also comprises, after booting the DPS, determining that reallocation of at least one of the IP blocks is desired, based on (a) monitored conditions of at least one of the microsystems and (b) a dynamic partitioning policy (DPP). The method also comprises, in response to determining that reallocation of at least one of the IP blocks is desired, automatically reallocating at least one of the IP blocks from one of the microsystems to another of the microsystems without resetting at least one of the microsystems. Other embodiments are described and claimed.

Abstract: An information handling system includes a memory and a central processing unit. The memory stores a boot image for a boot process of the information handling system. The central processing unit loads the boot image and executes the boot process. During the boot process, the central processing unit performs a pre-EFI initialization phase that configures a socket of the central processing unit during an auto-discovery of the socket, and stores the socket configuration in a memory.

Abstract: A request is received from a user of one of the one or more business applications for a business object. A single user interface is generating for displaying the data associated with the requested business object. A link between the requested business object and all of the data associated with the business object stored in the one or more data repositories is created. A subset of all of the data associated with the business object in the single user interface is displayed, the displaying being based on a role associated with the user making the request for the business object, the role being used by the at least one programmable processor for determining the subset of all of the data associated with the business object for displaying in the single user interface.

Abstract: Universal platform application support for plugin modules is provided. Connectivity to a universal platform application may be provided for plugin modules through an application service. Upon being launched on the same device as the universal platform application, a plugin module may submit a request for connection through the application service. Once connected, the universal platform application may receive a request for activation from the plugin module and may determine whether to activate the plugin module through an internal decision process or manual input. Subsequently, a user interface of the plugin module may be allowed to be visible and a user interface of the universal platform application may be hidden or pushed to background. When the plugin module is deactivated based upon completion of its tasks, the user interface of the plugin module may be hidden and the user interface of the universal platform application may be rendered visible.

Abstract: A dataflow control apparatus extracts a device capable of providing data that satisfies requirements of an application by matching device-side metadata and app-side metadata. In the case where the extracted device is a virtual device that generates new data on the basis of data that is obtained from one or more original devices and outputs the generated new data as virtual data, the dataflow control apparatus transmits a first dataflow control command instructing transmission of data from the original device to the virtual device, and transmits a second dataflow control command instructing transmission of virtual data from the virtual device to the application.

Abstract: The present disclosure provides a method and device for distributing an application. The method includes: acquiring a card category of a card to be displayed, where the card includes a download entry of the application and is loaded on a preset desktop, and provides a subset of functions of the application; acquiring real-time card information corresponding to the card category according to the card category; and displaying the card in a preset displaying format on the preset desktop based on the real-time card information.

Abstract: A system and method for customizing communication processing within a communication platform that includes configuring a service handler, which comprises of at least setting execution code of the service handler; setting an association between the service handler and a communication event of the communication platform; detecting the occurrence of the communication event of a communication facilitated through the communication platform; invoking the service handler in response to the event, which comprises: executing the execution code in a serverless execution environment and generating a service handler response; and augmenting the communication in accordance with the service handler response.

Abstract: A system and method for providing dynamic information virtualization (DIV) is disclosed. According to one embodiment, a device includes a dynamic optimization manager (DOM), a process and memory manager (PMM), a memory, and a host device driver. The device starts virtual functions after booting to allow a virtual machine (VM) running a guest operating system to identify the virtual functions and load virtual drivers of the virtual functions. The PMM allocates a unified cache from the memory to facilitate coherent access to information from storage and network resources by the VM. The host device driver enables a guess process in the VM to access the information stored in the unified cache in a secure and isolated manner.

Abstract: In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor is operable to generate one or more native machine instructions to explicitly control the virtual machine coprocessor.