Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Abstract: Circuitry for controlling a non-overlap time for a first switch and a second switch is described. Within a first state, the first switch is closed and the second switch is open, and within a second state, the first switch is open and the second switch is closed. The control circuitry has a first auxiliary switch and a second auxiliary switch. The control circuitry determines whether during a transition from the first state to the second state a current has flown through the serial arrangement of the first and second auxiliary switches. The control means adapts a non-overlap time between the first and second control signals for controlling a following transition from the first state to the second state, dependent on whether during said transition between the first and second states a current has flown through the serial arrangement of the first and second auxiliary switches.

Abstract: A clock duty cycle calibration and frequency multiplier circuit used in a square wave frequency multiplier has a multiplexing module, which performs a phase-inversion operation on a clock signal according to a control signal; a calibration module which adjusts the duty cycle according to a control signal, and outputs a clock signal with a 50% duty cycle; a delay module, which performs a delay operation on the clock signal according to a control signal; a detection module, which compares the clock signal and outputs a feedback signal; a control module, which outputs a control signal according to the feedback signal; a frequency multiplication module, which performs a frequency multiplication operation on the clock signal. Therefore, high-precision clock signal frequency multiplication is implemented with relatively low circuit complexity and low cost.

Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

Abstract: An overcurrent protection circuit that can cope even with a case where a ground fault occurs in a mask time period for overcurrent detection. The overcurrent protection circuit detects, when a switching element is on, a differential voltage value between both ends of the switching element that is caused by an electric current flowing therethrough, and turns off the switching element when the detected differential voltage value is larger than a predetermined voltage value. A detection circuit that detects respective voltage values at both ends of the switching element, and means for preventing the switching element from being turned on if either of the respective voltage values detected by the detection circuit is less than a predetermined value.

Abstract: An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage.

Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.

Abstract: A control circuit provides a signal to a control terminal of the transistor to control the conductivity of the transistor. The control circuit includes a voltage-to-current converter that provides an indication of the control terminal-to-current terminal voltage of a transistor. The control circuit includes control circuitry that uses the indication from the voltage-to-current converter in controlling the current applied to the control terminal.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: An electronic device with one or more gates that each include first circuit blocks configured for implementing a first N-type logic function and second circuit blocks configured for implementing a second N-type logic function that is a complement of the first N-type logic function. In the electronic device, a number of the of first circuit blocks and a number of the second circuit blocks are the same. Further, the first circuit blocks and the second circuit blocks each have a block feedback node, a block output node, and one or more block input logic nodes. Also, the block feedback node for each one of the first circuit blocks is singly coupled to the block output node of one of the second circuit blocks and the block output node of the one of the first circuit blocks is singly coupled to the block feedback node of another of the second circuit blocks.

Abstract: A bidirectional voltage translator shifts a voltage level of a first voltage signal to generate a second voltage signal, and vice-versa. The voltage translator includes first and second I/O terminals for receiving and outputting the first and second voltage signals, respectively, and first and second one-shot circuits connected to first and second output transistors, respectively. The outputs of the transistors are connected to the first and second I/O terminals, respectively, and also are fed back to the respective one-shot circuits. When the output of the voltage translator has a high slew-rate, the one of the first and second one-shot circuits that corresponds to the output modulates the gate voltage of the corresponding output transistor based on the feedback signal to control the slew-rate of the output.

Abstract: Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, the interface circuit can provide a selectable impedance.

Abstract: An input buffer circuit providing an interface between integrated circuits having differing power supply voltage sources. A voltage reference generator that produces dual reference voltages employing a flipped gate anti-doped transistor. A receiver is connected to receive the first reference voltage and the second reference voltage and the input voltage signal from an integrated circuit operating with a low power supply and transmitting with the first voltage range. The receiver has a first comparator, a second comparator, and a latching circuit. The first comparator compares receive the input voltage and the first reference voltage and the second comparator compares the input voltage and the second reference voltage for determining the output state of the receiver. The output of the receiver provides the data output signal from the input buffer.

Abstract: An integrated circuit includes a first logic circuit region comprising a first regional clock network for supplying a first regional clock signal to digital logic circuit(s); and a clock gating circuit to derive the first regional clock signal from a clock signal and selectively apply and interrupt the first regional clock signal in accordance with a state select signal. The first logic circuit region comprises a first back bias voltage grid connected to respective bodies of PMOS transistors of the digital logic circuit(s) and a second back bias voltage grid connected to respective bodies of NMOS transistors of the digital logic circuit(s). The integrated circuit further comprises a controllable back bias voltage generator configured to adjust a first back bias voltage of the first back bias voltage grid, and to adjust a back bias voltage of the second back bias voltage grid, in accordance with the state select signal.

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.

Abstract: An analog-to-digital converter includes an integrator, a single comparator, a successive approximation result register, and correction circuitry. The comparator is coupled to an output of the integrator. The successive approximation result register is coupled to an output of the comparator. The correction circuitry is configured to determine whether a sum of a reference voltage and an output voltage of the integrator changes an output of the comparator. The correction circuitry is also configured to, responsive to the sum of the reference voltage and the output of the integrator not changing the output of the comparator, add twice the reference voltage to the output of the integrator to produce a bit value at the output of the comparator, and select a bit value to be loaded into the successive approximation result register based on the bit value at the output of the comparator.

Abstract: Sampling accuracy during sampling of analog input signals may be improved by performing an “auto-zero every sample” procedure. The ratio of input signal samples to zero input samples for the sampling time interval defined by the sampling frequency may be determined based on the sampling frequency. For sampling frequencies equal to or less than a specified frequency characteristic of the signal conditioning path of the analog input signal, the ratio may be set to unity (one). For sampling frequencies above the specified frequency, the ratio may be set to be greater than unity (one), and may be a power-of-two. A digital signal processing block may include independent digital signal processing paths for the input signal measurements and the zero input measurements. Each signal processing path may include a low-pass infinite impulse response filter, an average decimation finite impulse response filter, and a binary shifter to allow for the adjustable ratio.

Abstract: An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

Abstract: A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.

Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.

Abstract: A delta-sigma modulator (DSM) includes: a first summation circuit coupled to an input signal for subtracting an error feedback signal from the input signal; a tunable signal transfer function coupled to the first summation circuit for setting a desired pole in a frequency response of the DSM; a second summation circuit coupled to the tunable signal transfer function for adding a noise transfer function to an output of the tunable signal transfer function; and a quantizer coupled to the second summation circuit for quantizing an output of the second summation circuit to generate an output of the DSM. The output of the DSM is used as feedback to the first summation circuit as the error feedback signal, and the tunable signal transfer function is dynamically tuned to allow selecting and tuning a center frequency and a bandwidth of the DSM.

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.

Abstract: The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.

Abstract: A mobile radio apparatus for a motor vehicle has a first mobile radio module and a second mobile radio module. Furthermore, a first antenna and a second antenna are provided for transmitting mobile radio signals. To provide robust voice telephony for the motor vehicle that can be implemented with little circuit complexity, a switching device is connected to the antennas and to a respective signal connection of the mobile radio modules and that is designed to take a switching signal as a basis for changing over between a first switching state, in which the first signal connection is coupled to the first antenna and the second signal connection is coupled to the second antenna, and a second switching state, in which the first signal connection is coupled to the second antenna and the second signal connection is coupled to the first antenna.

Abstract: An outphasing transmitter includes a combiner, a decomposition block, first and second power amplifiers, and antennas in a phased array antenna panel. The combiner combines a plurality of beamforming signals into a composite input signal. The decomposition block decomposes the composite input signal into first and second decomposed radio frequency (RF) signals coupled to the first and second power amplifiers. Non-overlapping sub-arrays of the antennas may be uniquely associated with the first and second power amplifiers. Alternatively, groups of interleaved antenna rows may be uniquely associated with the first and second power amplifiers. Alternatively, random pluralities of the antennas may be randomly hard-wired to the first and second power amplifiers. Alternatively, pluralities of the antennas may be dynamically and selectably assigned to the first and second power amplifiers. The phased array antenna panel forms a plurality of RF beams corresponding to the plurality of RF beamforming signals.

Abstract: Crest factor reduction techniques and apparatus provide good performance while reducing the impact to power consumption and implementation cost. An example method begins with identifying multiple non-overlapping and separated signal segments in a signal made up of a sequence of digital signal values, each identified segment being an interval in which at least one the digital signal values exceeds a predetermined threshold. For each identified signal segment, an overshoot vector representing the extent by which the identified signal segment exceeds the predetermined threshold is calculated. Each overshoot vector is separately filtered with a digital filter having one or more passbands corresponding to in-band portions of the signal. Each filtered overshoot vector is separately scaled, in some embodiments, and each scaled, filtered, overshoot vector is subtracted from the corresponding portion of the signal, to obtain a compensated signal having a reduced crest factor.

Abstract: An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes a single-balanced passive mixer driven by the output of a low noise amplifier (LNA) and a passive filter driven by an output of the single-balanced passive mixer. The RF receiver further includes a programmable gain amplifier (PGA) having an input resistance that generates noise, where the PGA is driven by an output of the passive filter, and the noise generated by the input resistance of the PGA is suppressed.

Abstract: Methods and systems for a configurable low-noise amplifier with programmable band-selection filters may comprise a receiver with a low-noise amplifier (LNA) with first and second input terminals and differential output terminals; a low pass filter operably coupled to the LNA; a high pass filter operably coupled to the second input terminal of the LNA; and a signal source input coupled to the low pass filter and the high pass filter. The LNA may be operable to receive signals in a pass band of the high pass filter and a pass band of the low pass filter. The receiver may be operable to amplify input signals in the pass band of a first filter but not signals in the pass band of the second filter by operably coupling the second to ground.

Abstract: The present disclosure provides a method and a dual band receiver for handling an analog dual band radio signal comprising a first frequency band component and a second frequency band component. The method comprises sampling the analog dual band radio signal through the use of interleaving analog-to-digital converters, ADCs, to obtain four sampled signals including a first I component, Iin+, a first Q component, Qin+, a second I component, Iin?, and a second Q component, Qin?, wherein phases of Qin+, Iin? and Qin? are respectively offset with respect to phases of Iin+, Qin+ and Iin? by ?/2. Then, the four sampled signals are filtered through the use of polyphase filters to obtain a first set of filtered signals (a1, a2, a3, a4) each of which has a same power as the first frequency band component and a second set of filtered signals (b1, b2, b3, b4) each of which has a same power as the second frequency band component.

Abstract: In an interactive communication system, one or more stations enter a scan mode to receive ID codes transmitted by wearable devices and transmit the ID codes to a server. The server receives the ID codes and transmits a command to one of the wearable devices via at least one of the stations. The one of the wearable devices receives the command via the at least one of the stations and transmits a feedback, in response to the command, to the server. The stations can detect signal strengths of the wearable devices. The server can determine a location of each of the wearable devices according to the ID codes and the signal strengths detected by the stations.

Abstract: An example method of capacitive sensing includes: receiving at least one code division multiplexed (CDM) signal transmitted from different transmitters using different codes over a plurality of signal bursts, wherein a length of each of the different codes is equal to or greater than a number of the different transmitters; filtering the at least one CDM signal using an impulse response filter, wherein the filtering comprises: accumulating the at least one CDM signal over the plurality of signal bursts to obtain measurements of the at least one CDM signal; and for the measurements of the at least one CDM signal, applying different filter weights to the resulting signals over a number of the plurality of signal bursts that is greater than the length of the different codes.

Abstract: A powerline communication system includes a plurality of rail segments. Each of the rail segments is electrically isolated from other rail segments, and each receives power from a rail segment power supply. At least one cart operates on the rail segments. The cart has a powerline communications controller. Each rail segment has a current state defined by how many and which carts are operating on the rail segment. A central coordinator is coupled to each rail segment and configured to execute a channel estimation using a sounding protocol on its rail segment. The central coordinators store tone maps associated with the possible states of its rail segment, and possibly its adjacent rail segment. A main controller communicates with each central coordinator to direct the state and future state of its segment so that tone maps and network keys can be managed by the CCo in advance of an imminent state change.

Abstract: A system for transmitting power and data, particularly including a half-wave control, includes a control unit connected to grid phases, the system having a phase-failure detection device which has bistable multivibrators, especially bistable multivibrators assigned to a respective grid phase. Each bistable multivibrator has an input for setting and an input for resetting, one of the inputs being connected to a digitizing device for digitizing the positive half-waves of a respective grid phase, the other of the inputs being connected to a digitizing device for digitizing the negative half-waves of a respective grid phase. The effective value of the output voltage of the bistable multivibrator is compared by a comparison device to a threshold value to detect a phase failure.

Abstract: Control module(s) and safety link(s) for ship communications arranging for emergency shutdown ESD communication between an unloading storage facility for hazardous goods on either ship or shore and a loading storage facility for hazardous goods on either ship or shore, with at least one umbilical line, connectors for coupling the control module(s) with the lines, the lines using bidirectional communication between a ship type control module and a shore type control module, and a transfer switch to switch the communication mode of the concerning control module between ship type and shore type.

Abstract: An application providing system is provided. The application providing system includes a portable terminal device having an IC chip configured to perform radio communications; and a server device; the application providing system connecting the portable terminal device and the server device through a communication network, wherein the portable terminal device includes a transmitted message receiver section, an application determination section, an application transmission request generation section, and an application storage section, wherein the server device includes a transmitted message generation section, a transmitted message sender section, an application transmission request receiver section, an application storage section, and an application sender section.

Abstract: The present invention relates to systems and methods for a charger which interacts with devices equipped with receivers. The charger may likewise have access to a server via a network connection. The charger receives a beacon signal from the receiver, and transmits power, and a control signal, to the device. Applications enable proper communication between the charger and the receiver. The receiver interprets and effectuates the commands. The receiver also includes sensors which generate data regarding the device status and usage. This data is provided to the server, via the charger. The server maintains a database of all user data collected from the devices, as well as user configurations. The user and third parties may access this data.

Abstract: Driver circuit in which a capacitor (4), in a manner controlled by a switch control device (9) which is connected downstream of a current measuring device (8), is charged to a reference voltage (Ur) by means of a charging current (Ic2), and the charged capacitor is discharged in an oscillating manner via an inductor coil (1), wherein the discharging operation is terminated when the current (Ia) through the inductor coil has passed through an entire oscillation period or several oscillation periods, wherein a first controllable switch (5) is connected in series between a first non-reactive resistor (6) and the first capacitor (4) in one of two input paths. Furthermore, a second controllable switch (7) and a fourth controllable switch (14) are connected into two output paths, and a second non-reactive resistor (13) is connected between a second connection (X2) of the inductor coil (1) and a connection for a reference potential (Um).

Abstract: Apparatuses, methods, and systems zone precoding are disclosed. One method includes training a transmission channel between a base station and each of a plurality of users and determining a precoding of transmission signals to each of the plurality of users from the base station. The training includes determining a transmission zone for each of the plurality of users, wherein the transmission zone includes an angle of direction of a directional beam to each user, and a deviation of the angle of direction. Determining a precoding of transmission signals to each of the plurality of users from the base station, includes determining an initial precoding for each of the users based on the transmission zone associated with the user, and constructing the precoding for each user by adjusting the initial precoding for each user based on the transmission zone determined for each of the other users.

Abstract: Systems, apparatuses, and techniques relating to wireless local area network devices are described. A described technique includes transmitting a sounding packet to wireless communication devices; receiving, in response to the sounding packet, feedback packets from the wireless communication devices, wherein the feedback packets collectively comprise beamforming feedback, the beamforming feedback being derived from received versions of the sounding packet; determining a steering matrix based on the beamforming feedback; and transmitting, within a frame, spatially steered data packets to the wireless communications devices. The spatially steered data packets can be based on the steering matrix and data streams intended respectively for the wireless communication devices. The spatially steered data packets can concurrently provide the data streams respectively within the frame to the wireless communication devices via different spatial wireless channels.

Abstract: A method for determining a precoding matrix indicator, user equipment, and a base station are disclosed in embodiments of the present invention. The method includes: receiving a first reference signal set sent by a base station, where the first reference signal set is associated with a user equipment-specific matrix or matrix set; selecting a precoding matrix based on the first reference signal set, where the precoding matrix is a function of the user equipment-specific matrix or matrix set; and sending a precoding matrix indicator to the base station, where the precoding matrix indicator corresponds to the selected precoding matrix. In the embodiments of the present invention, CSI feedback precision can be improved without excessively increasing feedback overhead, thereby improving system performance.

Abstract: Methods, apparatus, and systems for wireless communications are described. Example methods, devices, and systems are described that utilize a precoding matrix indicator (PMI) computed based at least in part on first signals received via a first cell and on second signals received via a second cell. Information in a measurement information message may be used as part of computing a PMI. The measurement information message may indicate resources of a first cell and a second cell for use in computing the PMI. A wireless device may receive first signals via the first cell and second signals via the second cell based on information in the measurement information message, and may use these signals to compute the PMI. The computed PMI may be used in communications with a base station. For example, the wireless device may receive a packet beamformed employing the computed PMI.

Abstract: A method performed by a base station of enabling a User Equipment, UE, to determine a precoder codebook in a wireless communication system is provided. The base station transmits (303) to the UE, information regarding precoder parameters enabling the UE to determine the precoder codebook. The precoder parameters are associated with a plurality of antenna ports of the base station. The precoder parameters relate to a first dimension and a second dimension of the precoder codebook. The plurality of antenna ports comprises a number NT of antenna ports that is a function of a number Nh of antenna ports in the first dimension, and a number Nv of antenna ports in the second dimension.

Abstract: The present invention relates to a method for transmitting, by a base station, a downlink signal using a plurality of transmission antennas comprises the steps of: applying a precoding matrix indicated by the PMI, received from a terminal, in a codebook to a plurality of layers, and transmitting the precoded signal to the terminal through a plurality of transmission antennas. Among precoding matrices included in the codebook, a precoding matrix for even number transmission layers can be a 2×2 matrix containing four matrices (W1s), the matrix (W1) having rows of a number of transmission antennas and columns of half the number of transmission layers, the first and second columns of the first row in the 2×2 matrix being multiplied by 1, the first column of the second row being multiplied by coefficient “a” of a phase, and the first column of the second row being multiplied by “?a”.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of wireless communication via multiple antenna assemblies. For example, a device may include a wireless communication unit to transmit and receive signals via one or more quasi-omnidirectional antenna assemblies, wherein the wireless communication unit is to transmit, via each quasi-omnidirectional antenna assembly, a plurality of first transmissions, to receive, in response to the first transmissions, a plurality of second transmissions from another device via one or more of the quasi-omnidirectional antenna assemblies, and, based on the second transmissions, to select at least one selected transmit antenna assembly for transmitting to the other device and a selected receive antenna assembly for receiving transmissions from the other device. Other embodiments are described and claimed.

Abstract: A method, and a device, for reporting channel state information (CSI) in a wireless local area network system are discussed. The method according to one embodiment includes receiving, by a responding station, a sounding Physical layer Protocol Data Unit (PPDU) from a requesting station; and transmitting, by the responding station, a CSI report to the requesting station, the CSI report including CSI report information in a form of angles representing a beamforming feedback matrix that is estimated by the responding station based on the sounding PPDU. If the sounding PPDU is received via a plurality of contiguous channels, the beamforming feedback matrix is estimated based on all of the plurality of contiguous channels. If the sounding PPDU is received via at least one of a plurality of non-contiguous channels, the beamforming feedback matrix is estimated based on only one of the plurality of non-contiguous channels.

Abstract: Methods and corresponding apparatuses for wireless communication are disclosed. The method for wireless communication includes dividing a two-dimensional antenna array to a plurality of sub-arrays, mapping the two-dimensional antenna array into a one-dimensional vertical channel state information reference signal (CSI-RS) port array for receiving elevation CSI feedback and a one-dimensional horizontal CSI-RS port array for receiving azimuth CSI feedback, and transmitting one or more elevation CSI-RS from the one-dimensional vertical CSI-RS port array and one or more azimuth CSI-RS from the one-dimensional horizontal CSI-RS port array. Methods and corresponding apparatuses for CSI feedback mechanism are also disclosed.

Abstract: Disclosed is a communication method using outdated channel state information in a network environment having a G-cell and 2-user terminal, by allowing a terminal and base stations to transmit and receive data symbols for G time slots, and to transmit and receive a reconfiguration signal for an additional one time slot.

Abstract: A CSI feedback method includes steps of: performing, by a terminal, channel estimation on a received pilot signal to acquire channel estimation values of A antenna ports for transmitting the pilot signal to a network device; determining, by the terminal, Q antenna ports based on the channel estimation values of the A antenna ports, L?Q?A, L representing a value of a RI adopted by the network device in the case of transmitting downlink data to the terminal or a value of a RI of a channel determined by the terminal; and determining, by the terminal, a first-level PMI based on the Q antenna ports, and feeding back CSI containing the first-level PMI to the network device, the first-level PMI being used to indicate indices of the Q antenna ports among the A antenna ports for transmitting the pilot signal.

Abstract: A UE may receive a beam modification command that indicates a set of transmit beam indexes corresponding to a set of transmit beams of a base station, and each transmit beam index of the set of transmit beam indexes may indicate at least a transmit direction for transmitting a transmit beam by the base station. The UE may determine a set of receive beam indexes corresponding to receive beams of the UE based on the set of transmit beam indexes, and each receive beam index of the set of receive beam indexes may indicate at least a receive direction for receiving a receive beam by the UE. The UE may receive, from the base station, a signal through at least one receive beam corresponding to at least one receive beam index included in the set of receive beam indexes.

Abstract: An interference cancellation repeater for canceling an interference signal included in an input signal including a first adaptive filter configured to generate a first estimated signal; a second adaptive filter configured to generate a second estimated signal; a first scaler configured to scale the first estimated signal based on a first scale factor determined according to a channel state; a second scaler configured to scale the second estimated signal based on a second scale factor determined according to the channel state; a first canceller configured to generate a first interference canceled signal based on the input signal and the scaled first estimated signal; and a second canceller configured to generate a second interference canceled signal based on the first interference canceled signal and the scaled second estimated signal.