Patents Issued in February 21, 2019
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Publication number: 20190056917Abstract: Disclosed are systems, media, and methods for automatically and intelligently redesigning a web presence by: ingesting files of an existing web site; extracting content from the ingested files; surveying a user for user preferences; determining a style package based on the user preferences; selecting a web site skeleton from a plurality of preconfigured web site skeletons based on the user preferences, the web site skeleton having a plurality of hierarchical blocks; applying a machine learning system to rank the extracted content; populating the content into the hierarchy of blocks based on the rank; automatically generating a redesigned web site by applying the style package to the populated web site skeleton; and providing an interface allowing the user to edit the style package, the content, and the web site skeleton.Type: ApplicationFiled: August 17, 2018Publication date: February 21, 2019Inventors: Eric George BERNAL, Scott Eric BERNAL, Cary Michael LEVINE, Thomas William RICH, Shanket Rajendra PATEL
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Publication number: 20190056918Abstract: A computing device for interpreting a data model algorithm includes an object searcher, an interpreter, and a translator. The object searcher is configured to search for attributes within datasets generated from at least one method of an instantiation of the data model algorithm in a development mode workflow. The interpreter is configured to evaluate the attributes, identify attributes having a use type, identify the type information of the identified attribute, and create data schema using the identified attributes and type information. The use type can be determined based on attribute values or an interface type associated with an identified attribute. The translator is configured to compare the data schema with another data schema in response to selecting the data model algorithm for inclusion in a production mode workflow.Type: ApplicationFiled: August 16, 2018Publication date: February 21, 2019Inventor: Andrew LANGDON
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Publication number: 20190056919Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
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Publication number: 20190056920Abstract: Provided is a vectorization device 30 comprising: a unit 31 that detects a configuration in which the inner loop length depends on the outer loop variable, and in which a first array indicating the results of dual-loop processing does not contain the inner loop variable as an index value; an unit 32 that, when the configuration is detected, determines a fixed value as the inner loop length; an unit 33 that expands the array size of a second array used in the calculation of the first array value, and thereby enables dual-loop processing of the inner loop; an unit 34 that sets an element value for an added element of the second array, and thereby, before and after such processing is carried out, enables the results of the dual-loop processing to be made equal; and an unit 35 that updates the software on the basis of such processing results.Type: ApplicationFiled: November 17, 2016Publication date: February 21, 2019Applicant: NEC CorporationInventor: Yoshiyuki OHNO
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Publication number: 20190056921Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.Type: ApplicationFiled: November 16, 2017Publication date: February 21, 2019Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
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Publication number: 20190056922Abstract: A method of administering a computing system, including a plurality of computing devices. The method includes selecting an application for download to a computing device, prior to downloading the application, decompiling the application, searching for string patterns in the decompiled application, replacing the string patterns in the decompiled application with another string pattern, the another string pattern being configured to intercept at least one of a system event or an Application Programming Interface (API) call, and associating logic with the application. The logic is configured to interact with the application via the at least one system event or API call, the logic is configured to provide additional functions to the application, the logic is configured to be shared between the application and at least one other application, and the logic is stored separate from the application.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Adam Charles Cooper, George Thucydides, Geoff Ross Mair, Caleb Peter Buxton
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Publication number: 20190056923Abstract: A communication unit receives, from a terminal device, installed application information indicating an input/output schedule of input of input information to be used for computation by an installed application program installed in the terminal device and output of a result of computation by the installed application program. A determination unit analyzes the input/output schedule of the installed application program indicated by the installed application information and an input/output schedule of input of input information to be used for computation by a non-installed application program not yet installed in the terminal device and output of a result of computation by the non-installed application program, and determines whether or not the installed application program and the non-installed application program can be executed by the terminal device.Type: ApplicationFiled: December 10, 2015Publication date: February 21, 2019Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Madoka BABA, Daisuke KAWAKAMI, Yuta ATOBE
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Publication number: 20190056924Abstract: The present invention discloses a node upgrading method and system in a mesh network. The node upgrading method in the mesh network comprises: performing the wireless firmware OTA upgrade by the first node according to the terminal instruction; simultaneously performing OTA upgrade on at least part of the second nodes in the mesh network by the first node using the broadcast channel after completion of the OTA upgrade, wherein the second node is a node other than the first node in the mesh network. Embodiments of the invention also provide a node upgrading system in the mesh network.Type: ApplicationFiled: December 27, 2017Publication date: February 21, 2019Applicant: TELINK SEMICONDUCTOR (Shanghai) CO., LTD.Inventors: Guohua JIANG, Qifa SHANG, Haipeng JIN, Mingjian ZHENG
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Publication number: 20190056925Abstract: According to an embodiment, an update control apparatus is to control update of software in a terminal connected to a network. The update control apparatus includes a first communication circuit, a second communication circuit, and a processor. The first communication circuit is configured to communicate with a server located outside the network. The second communication circuit is configured to communicate with the terminal through the network. The processor is configured to: receive update data to update the software from the server using the first communication circuit; transmit the update data to the terminal, as well as receive an update result indicating whether update of the software has succeeded, together with verification data, from the terminal using the second communication circuit; and verify, using the verification data, whether the update result is proper data.Type: ApplicationFiled: February 14, 2018Publication date: February 21, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Yuichi KOMANO, Zhengfan XIA, Takeshi KAWABATA
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Publication number: 20190056926Abstract: In accordance with an embodiment, described herein is a system and method for providing support for custom hooks during patching in an application server, enterprise, cloud computing, or other computing environment. A patch orchestration engine generates a patching workflow including a series of steps that apply patches to update one or more targeted nodes in a controlled manner with minimal downtime. Custom hooks provide a flexible mechanism that enables modifying phases of the patching workflow that can be associated with extension points. When an extension, for example an additional Java software code, script or other command, is specified to be run at a particular extension point associated with a particular phase of a patching workflow, the patch orchestration engine causes the extension to be inserted into the patching workflow, for execution during patching of the targeted nodes, to modify that phase of the patching workflow.Type: ApplicationFiled: July 6, 2018Publication date: February 21, 2019Inventors: Jacob Lindholm, Yamini Kalyandurga Balasubramanyam
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Publication number: 20190056927Abstract: A communication system includes a first node and a second node, the first node is configured to obtain first information indicating reachability of data to the second node, specify a number of frames when transmitting, to the second node, a file to be used for updating of software at the second node, specify, based on the first information and the number of frames, a transmission method candidate to transmit the file, and notify the second node of the specified transmission method candidate, the second processor is configured to, generate updating information indicating whether the software can be updated based on the file to be transmitted by the transmission method candidate, and notify the first node of the updating information, the first processor is configured to, specify a transmission method of the file, based on the updating information, transmit the file to the second node by using the specified transmission method.Type: ApplicationFiled: August 8, 2018Publication date: February 21, 2019Applicant: FUJITSU LIMITEDInventor: Fuyuta SATO
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Publication number: 20190056928Abstract: A method of manufacturing a robot comprising the steps of discovering a plurality of generic components, the generic components being interconnected and non-functional in the robot; determining the spatial position of each generic component in the robot; retrieving respective firmware associated with each generic component; modifying a generic component into a specified component, by programming the firmware of the generic component with a retrieved firmware. The use of encryption mechanisms, the use of one or more bootloaders, the use of decentralized or distributed storage of firmware and the use of predefined hardware abstraction layers. Software and system aspects (e.g. multi-masters architectures) are provided.Type: ApplicationFiled: March 7, 2017Publication date: February 21, 2019Inventors: Ludovic SMAL, Julien SERRE
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Publication number: 20190056929Abstract: The present invention discloses a data transmission method, comprising: adopting a first electronic device to obtain a first file from a third electronic device, and the first file having a first data; using at least one of the first electronic device and a second electronic device to compare the first data with a second data of the second electronic device and generate a first result, while the first electronic device and the second electronic device are electrically connected; and determining whether the first result meets a condition, and if yes, replacing the second data of the second electronic device with the first data.Type: ApplicationFiled: August 17, 2018Publication date: February 21, 2019Inventor: Shiu-Yung LIN
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Publication number: 20190056930Abstract: Enterprise Content Management systems are built using Apache Sling web framework for storing and retrieving content from Java Content Repository API (JCR), A plurality of data structures is stored and retrieved using Sling Servlet method by JCR. A plurality of scripting engines (Freemarker, Groovy, HTL, Java, Javascript, JSP, JST, Python, Ruby, Scala, Thymeleaf, Velocity and XProc are used to dynamically render the content retrieved using the Sling Servlet method. This invention enables Apache Sling Web Framework executing on a single webserver to service requests, as deemed necessary, by either a Sling Servlet method or a faces servlet method, where both the said methods are hosted and co-located on the same webserver. The Apache Sling Framework so enabled empowers corporations to build enterprise grade Java/J2EE architecture applications and Content Management System (CMS) features for on-premise and Cloud based applications and host such applications on a single webserver.Type: ApplicationFiled: August 16, 2017Publication date: February 21, 2019Applicant: Singareddy Information Technologies, Inc.Inventor: Ravindra Reddy Singareddy
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Publication number: 20190056931Abstract: Systems and methods for computationally generating a set of more “stable” configuration default values that are used for traceability and improving reproducibility of machine learning approaches. Hash values are generated based on a merged/modified configuration and both configuration content and hash are stored together in one or more data structures. These data structures can be used to link back to the actual values used in experiments.Type: ApplicationFiled: August 21, 2018Publication date: February 21, 2019Inventors: Weiguang DING, Yanshuai CAO
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Publication number: 20190056932Abstract: Systems, methods, apparatuses, and software for data systems are provided herein. In one example, a data system is presented. The system includes a processing system configured to execute an operating system that comprises a network module for handling data frames directed to a plurality of kernel threads and received over one or more network interfaces of the data system. The network module is configured to establish a plurality of data buffers individually associated with the kernel threads, store associated ones of the data frames for the kernel threads in the data buffers as the data frames are processed through a network stack of the data system, and maintain data exclusivity locks for the plurality of data buffers and individually associate the data exclusivity locks with the kernel threads.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Applicant: Liqid Inc.Inventor: James Scott Cannata
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Publication number: 20190056933Abstract: Processing circuitry (4) performs multiple beats of processing in response to a vector instruction, each beat comprising processing corresponding to a portion of a vector value comprising multiple data elements. The processing circuitry (4) sets beat status information (22) indicating which beats of a group of two or more vector instructions have completed. In response to a return-from-event request indicating a return to processing of the given vector instruction, the processing circuitry (4) resumes processing of the group of uncompleted vector instructions while suppressing beats already completed, based on the beat status information (22).Type: ApplicationFiled: March 17, 2017Publication date: February 21, 2019Inventor: Thomas Christopher GROCUTT
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Publication number: 20190056934Abstract: Techniques for providing high-performance buffer caches for transactional input/output (I/O) systems are disclosed. The techniques include obtaining a first logical creation time of a resource to be acquired by the first transaction during a pre-commit phase of a first transaction with an I/O system. When the first logical creation time exceeds a latest logical creation time from a set of resources previously acquired by the first transaction, the first logical creation time of the resource is compared with an earliest logical termination time from the set of resources. When the first logical creation time of the resource exceeds the earliest logical termination time from the set of resources, a conflict between the resource and the set of resources is detected, and a restart of the first transaction is triggered.Type: ApplicationFiled: August 15, 2017Publication date: February 21, 2019Applicant: Oracle International CorporationInventors: Unmesh Rathi, Arjun Sharma, Suresh Kumar Neelakanda Iyer, Vijayan Satyamoorthy Srinivasa
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Publication number: 20190056935Abstract: Detecting that a sequence of instructions creates an affiliated relationship. A determination is made that a sequence of instructions creates an affiliated relationship. Based on determining that the sequence of instructions creates the affiliated relationship, a sequence of operations is generated. The sequence of operations provides a predicted target address to be included in a selected register and to be used in branching.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056936Abstract: A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056937Abstract: Detecting that a sequence of instructions creates an affiliated relationship. A determination is made that a sequence of instructions creates an affiliated relationship. Based on determining that the sequence of instructions creates the affiliated relationship, a sequence of operations is generated. The sequence of operations provides a predicted target address to be included in a selected register and to be used in branching.Type: ApplicationFiled: November 17, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056938Abstract: A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents.Type: ApplicationFiled: November 17, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056939Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.Type: ApplicationFiled: March 12, 2018Publication date: February 21, 2019Inventor: Ahmad Yasin
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Publication number: 20190056940Abstract: Code-specific affiliated register prediction. A determination is made as to whether a unit of code is a candidate for affiliated register prediction. The determining employs a code specific indicator specific to the unit of code. Based on determining the unit of code is a candidate for affiliated register prediction, an indication of an affiliated register is loaded into a selected location. Based on the loading, the affiliated register is employed in speculative processing.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056941Abstract: A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module.Type: ApplicationFiled: October 23, 2018Publication date: February 21, 2019Inventors: Xiaolin Wang, Qian Wu
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Publication number: 20190056942Abstract: In a distributed computing system comprising multiple processor types, a method of provisioning includes receiving a request from a client device for execution of a function. A first data structure identifies implementations of the function and compatible processor types for each implementation. A second data structure identifies available processors in the system. Compatible processor types matching available processors are candidates for execution of the function. A provisioning instruction is created for allocating resources for execution of the function.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Inventors: Yuanxi CHEN, Jack Hon Wai NG, Craig DAVIES, Reza AZIMI
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Publication number: 20190056943Abstract: A fusion opportunity is detected for a sequence of instructions. The sequence of instructions include an indication of an affiliated location and an indication of an affiliated derived location. Based on the detecting, a value to be stored in the affiliated derived location is generated. The value is a predicted value. The value is stored in the affiliated derived location, and the affiliated derived location is accessed to use the value by one or more instructions executing within the computing environment.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056944Abstract: Predicting a predicted value to be used in register-indirect branching. The predicted value is stored in a first selected location and a second selected location accessible to one or more instructions of a computing environment. The storing is performed concurrently to processing a register-indirect branch. Further, the first selected location and the second selected location is in addition to another location used to store an instruction address. The predicted value is used in speculative processing that includes the register-indirect branch.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056945Abstract: A determination is made as to whether an instruction is an affiliation-creating instruction that provides an affiliation between a plurality of registers. Based on determining the instruction is an affiliation-creating instruction, an affiliation is specified. Further, a branch instruction is obtained. The branch instruction is separated from the instruction by one or more instructions. Based on the branch instruction and specifying the affiliation, processing is performed.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056946Abstract: A predicted value to be used in register-indirect branching is predicted. The predicted value is to be stored in one or more locations based on the prediction. An offset for a predicted derived value is obtained. The predicted derived value is to be used as a pointer to a reference data structure providing access to variables used in processing. The predicted derived value is generated using the predicted value and the offset. The predicted derived value is used to access the reference data structure during processing.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056947Abstract: Prediction of an affiliated register. A determination is made as to whether an affiliated register is to be predicted for a particular branch instruction. The affiliated register is a register, separate from a target address register, selected to store a predicted target address based on prediction of a target address. Based on determining that the affiliated register is to be predicted, predictive processing is performed. The predictive processing includes providing the predicted target address in a location associated with the affiliated register.Type: ApplicationFiled: August 18, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056948Abstract: A predicted value to be used in register-indirect branching is predicted. The predicted value is to be stored in one or more locations based on the prediction. An offset for a predicted derived value is obtained. The predicted derived value is to be used as a pointer to a reference data structure providing access to variables used in processing. The predicted derived value is generated using the predicted value and the offset. The predicted derived value is used to access the reference data structure during processing.Type: ApplicationFiled: November 21, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056949Abstract: A fusion opportunity is detected for a sequence of instructions. The sequence of instructions include an indication of an affiliated location and an indication of an affiliated derived location. Based on the detecting, a value to be stored in the affiliated derived location is generated. The value is a predicted value. The value is stored in the affiliated derived location, and the affiliated derived location is accessed to use the value by one or more instructions executing within the computing environment.Type: ApplicationFiled: November 21, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056950Abstract: A determination is made as to whether an instruction is an affiliation-creating instruction that provides an affiliation between a plurality of registers. Based on determining the instruction is an affiliation-creating instruction, an affiliation is specified. Further, a branch instruction is obtained. The branch instruction is separated from the instruction by one or more instructions. Based on the branch instruction and specifying the affiliation, processing is performed.Type: ApplicationFiled: November 21, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056951Abstract: Predicting a predicted value to be used in register-indirect branching. The predicted value is stored in a first selected location and a second selected location accessible to one or more instructions of a computing environment. The storing is performed concurrently to processing a register-indirect branch. Further, the first selected location and the second selected location is in addition to another location used to store an instruction address. The predicted value is used in speculative processing that includes the register-indirect branch.Type: ApplicationFiled: November 21, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056952Abstract: Prediction of an affiliated register. A determination is made as to whether an affiliated register is to be predicted for a particular branch instruction. The affiliated register is a register, separate from a target address register, selected to store a predicted target address based on prediction of a target address. Based on determining that the affiliated register is to be predicted, predictive processing is performed. The predictive processing includes providing the predicted target address in a location associated with the affiliated register.Type: ApplicationFiled: November 27, 2017Publication date: February 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190056953Abstract: A device protects data dependency for memory access. The device includes a memory and a processor. The processor executes memory access instructions including load instructions and store instructions. The processor includes load circuitry to execute the load instructions; and store circuitry to execute the store instructions. Each memory access instruction includes a token index field containing a token index that associates the memory access instruction with a memory location. The processor further includes dispatch circuitry to dispatch instructions to the load circuitry and the store circuitry; and a token registry to record used token indices according to token index fields in the memory access instructions dispatched by the dispatch circuitry.Type: ApplicationFiled: May 1, 2018Publication date: February 21, 2019Inventors: Steve Hengchen Hsu, Hsiao-Han Ma, Chia-An Lin, Wei-Lun Hung, Dan MingLun Chuang
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Publication number: 20190056954Abstract: A method for encoding multiple descriptions for a media stream includes: determining, for a current block of the media stream, a first number of duplicate blocks, determining, for the current block, a plurality of complementary forward gain factors, and determining a first number of descriptions for the current block by applying the plurality of complementary forward gain factors to the first number of duplicate blocks. A method for decoding multiple descriptions for a media stream includes: determining, for a current block of the media stream, a first number of descriptions from the media stream, in which each description comprises a scaled block corresponding to the current block, determining backward gain factors for the first number of scaled blocks, and determining the current block by applying the backward gain factors to the first number of scaled blocks.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Inventors: Zehua Gao, Ruofei Chen, Siqiang Yao, Shie Qian
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Publication number: 20190056955Abstract: A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.Type: ApplicationFiled: July 27, 2018Publication date: February 21, 2019Applicant: Arm LimitedInventors: Jussi Tuomas Pennala, Robert John Rees, Hakan Lars-Goran Persson
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Publication number: 20190056956Abstract: A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.Type: ApplicationFiled: April 10, 2018Publication date: February 21, 2019Applicant: SK hynix Inc.Inventors: Chul Moon JUNG, Joo Hyeon LEE, Sung Nyou YU
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Publication number: 20190056957Abstract: In one embodiment, an operating system is booted based on results of boot-up operations performed during a shutdown. In operation, during a shutdown phase of an operating system, one or more boot-up operations are performed, and the results of these operations are stored in memory. During a boot-up phase of the operating system, the results are received, and the operating system is booted based on the one or more results.Type: ApplicationFiled: October 16, 2017Publication date: February 21, 2019Inventors: Rohit MEWAR, Eugine VARGHESE
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Publication number: 20190056958Abstract: Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. The shader may reference a particular slot of the descriptor set using an offset, and may change shader resources by referencing a different slot of the descriptor set or by binding or rebinding a new descriptor set. A graphics pipeline may be specified by creating a pipeline object which specifies a shader and a rendering context object, and linking the pipeline object. Part or all of the pipeline may be validated, cross-validated, or optimized during linking.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Guennadi Riguer, Brian K. Bennett
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Publication number: 20190056959Abstract: An example system includes a processor. The system also includes a peripheral interface that includes a controller communicatively coupled to the processor. The controller is to request information from a plurality of devices connected to the peripheral interface prior to the processor requesting the information. The controller is to provide the information to the processor.Type: ApplicationFiled: August 22, 2016Publication date: February 21, 2019Applicant: Hewlett-Packard Development Company, L.P.Inventors: Mark A. PIWONKA, Michael R. DURHAM, Nam H. NGUYEN
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Publication number: 20190056960Abstract: An online virtual computer system provides a browser-accessible virtual computer via the Internet. The virtual computer appears to the user to have a hard drive with selected capacity, a selected type of processor, RAM of selected size, and a selected virtual operating system. In a preferred embodiment, the virtual hardware and software specifications are selected by the user during a setup procedure. Because the virtual machine is always up-to-date with the latest hardware and software, the system relieves the user from concern about computer components becoming obsolete. Thus, the user does not have to worry about upgrading to a new computer and moving the user's data over to a new computer.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Inventor: William B. Potter
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Publication number: 20190056961Abstract: A server receives a web-protocol request from a client that triggers a server-side operation in response to the request. Based on a result of the operation, the server identifies first text information to be returned to the client. A language associated with the client device is determined. A determination is made as to whether a resource file corresponding to the determined language is loaded in a volatile memory on the server. In a case where a resource file corresponding to the determined language is not loaded in the volatile memory, the resource file corresponding to the determined language is loaded from a non-volatile memory into the volatile memory on the server. Second text information which corresponds to the first text information to be returned to the client device is retrieved from the resource file in the volatile memory. The second text information is transmitted to the client.Type: ApplicationFiled: August 15, 2017Publication date: February 21, 2019Inventor: Stefan Dimov
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Publication number: 20190056962Abstract: A system module applied to the machine controller for simulating a machine operation screen based on a non-invasive data-extraction system, is disclosed. An image capture device of the system module can receive an original operation screen outputted from the machine controller, and transmit the original operation screen to the non-invasive data-extraction system and a high-speed image process unit for extraction of the information shown on the operation screen. The software control system can extract the operational information of the machine controller in real time, to create a machine operation flow for generating a simulated machine operation screen which is then outputted to a screen of the machine controller. As a result, the site working staff can be provided with operational information associated with the machine in real time, for example, the operational information includes currently executed operation screen, position of mouse cursor and pop-up window detection result.Type: ApplicationFiled: July 20, 2018Publication date: February 21, 2019Inventors: Chua-Hong NG, Chao-Tung YANG, Wei-Hung CHEN, Tsan-Ming YU, Shih-Hsun LIN, Yang-Chung TSENG, Chih-Fu HSU, Chien-Hsun TU, Ren-Yu WU, Chieh-Yuan LO, Chih-Kai SHIAO, Hsiao-Ling CHANG, Te-Cheng TSENG, Chun-Liang CHEN
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Publication number: 20190056963Abstract: Disclosed are systems and methods for emulating execution of a file. An image of a file is formed, which is comprised of instructions read from the file. An analysis module detects at least one known set of instructions in a portion read from the file, and inserts a break point into a position in the generated image of the file corresponding to a start of the detected set of instructions. An emulation module emulates execution of the file by emulating execution of instructions from the generated image of the file and adding corresponding records to an emulation log associated with the emulated execution of the at least one known set of instructions.Type: ApplicationFiled: October 12, 2017Publication date: February 21, 2019Inventors: Alexander V. Liskin, Vladimir V. Krylov
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Publication number: 20190056964Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.Type: ApplicationFiled: October 19, 2018Publication date: February 21, 2019Inventors: Mohammad Abdallah, Ankur Groen, Erika Gunadi, Mandeep Singh, Ravishankar Rao
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Publication number: 20190056965Abstract: A first execution of an application is performed on a virtual machine. A set of virtual machine parameters associated with the first execution is determined. One or more command lines of the application are mapped to the set of virtual machine parameters. The mapping is stored in a cache. A second execution of the application is performed on the virtual machine. The second execution retrieves the set of virtual machine parameters from the cache.Type: ApplicationFiled: August 15, 2017Publication date: February 21, 2019Inventors: Daniel Heidinga, Peter D. Shipton, Aleksandar Micic, Devarghya Bhattacharya, Kenneth B. Kent
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Publication number: 20190056966Abstract: Systems and methods for operating a cloud based computing system. The methods comprise: receiving, by a cloud server, a request for accessing Virtual Hard Disk (“VHD”) data associated with a first location in the VHD of a Virtual Machine (“VM”) hosted by a remote computing device; extracting, by the cloud server, at least a first address specifying the first location from the request; translating, by the cloud server, the first address into a second address specifying a second location in a cloud storage where the VHD data is stored; and communicating from the cloud server the second address to the remote computing device for facilitating access to the VHD data stored in the cloud storage.Type: ApplicationFiled: August 15, 2017Publication date: February 21, 2019Inventors: John Baboval, Thomas Goetz, Simon P. Graham