Patents Issued in March 21, 2019
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Publication number: 20190087081Abstract: The system and method for application re-creation centers on the need for the rapid recreation of applications and playable media for uses in testing, simulation, sampling, marketing, and feature optimization. Using a video-tree system, this disclosure allows for application reproduction, simulation and playback by first and third parties with a high degree of accuracy. The underlying method for reproduction centers on a branching approach to recording applications (i.e., digital video formats), and the stitching of the sampled digital video using a taxonomical branching of user journeys. The technology simplifies the process of providing accurate, high efficacy samples and reproductions of applications. The sample experiences are provided via a scripting and configuration file linked to a plurality of video branches. The video branches are stitched in a method to mimic the look and feel of the original application.Type: ApplicationFiled: October 30, 2018Publication date: March 21, 2019Inventors: Jonathan Lee Zweig, Adam Piechowicz
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Publication number: 20190087082Abstract: An electronic device with improved methods and interfaces for messaging displays a messaging user interface that includes a conversation transcript of a messaging session between a user of the electronic device and at least one other user. A first message that includes foreign language text is received from a remote device that corresponds to another user included in the messaging session. In response to receiving the first message, the electronic device displays the first message in the conversation transcript. In response to detecting a first input at a location that corresponds to the foreign language text in the first message: in accordance with a determination that the first input meets translation criteria, the electronic device performs a foreign-language-text-translation action; and in accordance with a determination that the first input does not meet the translation criteria, the electronic device forgoes performance of the foreign-language-text-translation action.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: Imran A. Chaudhri, Tiffany S. Jon, Chanaka G. Karunamuni, William M. Tyler, Darin B. Adler, Bethany Bongiorno, Justin N. Wood
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Publication number: 20190087083Abstract: Techniques for providing multi-user multi-touch projected capacitive touch sensors are disclosed herein. Some embodiments may include a method that includes receiving a first sense signal from a first sensing array, the first sensing array configured to provide the first sense signal indicating a first touch on a first touch surface of a touch substrate as well as receiving a second sense signal from a second sensing array, the second sensing array configured to provide the second sense signal indicating a second touch on a second touch surface of a second touch substrate occurring concurrently to the first touch. The method may further include determining whether the first touch and the second touch share at least one anti-ghost. The method may also include associating the first touch and the second touch with a common touch entity in response to determining that the first touch and the second touch share the at least one anti-ghost.Type: ApplicationFiled: November 19, 2018Publication date: March 21, 2019Applicant: EL TOUCH SOLUTIONS, INC.Inventors: Damien BERGET, Kenneth Andrew Feehan, Paul Leonard Futter, David Samuel Hecht, Joel Christopher Kent, Robert William Kitchin, Kenneth John North, James Roney, Kyu-Tak Son, Jung Verheiden, Forrest Kim Wunderlich
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Publication number: 20190087084Abstract: An apparatus and method are disclosed for providing feedback and guidance to touch screen device users to improve text entry user experience and performance by generating input history data including character probabilities, word probabilities, and touch models. According to one embodiment, a method comprises receiving first input data, automatically learning user tendencies based on the first input data to generate input history data, receiving second input data, and generating auto-corrections or suggestion candidates for one or more words of the second input data based on the input history data. The user can then select one of the suggestion candidates to replace a selected word with the selected suggestion candidate.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Applicant: Microsoft Technology Licensing, LLCInventors: Eric Norman Badger, Drew Elliott Linerud, Itai Almog, Timothy S. Paek, Parthasarathy Sundararajan, Dmytro Rudchenko, Asela J. Gunawardana
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Publication number: 20190087085Abstract: Disclosed herein are system, method, and computer program product embodiments providing an ergonomic user interface keyboard. An embodiment operates by obtaining an accessibility measure corresponding to a finger of a user. An interface keyboard is configured based on an accessibility map corresponding, to the accessibility measure of the finger. The interface keyboard associated with a device is displayed.Type: ApplicationFiled: September 20, 2017Publication date: March 21, 2019Inventor: Wojciech Koszek
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Publication number: 20190087086Abstract: A method for providing context based multimodal predictions in an electronic device is provided. The method includes detecting an input on a touch screen keyboard displayed on a screen of the electronic device. Further, the method includes generating one or more context based multimodal predictions based on the detected input from a language model. Furthermore, the method includes displaying the one or more context based multimodal predictions in the electronic device. An electronic device includes a processor configured to detect an input through a touch screen keyboard displayed on a screen of the electronic device, generate one or more context based multimodal predictions in accordance with the detected input from a language model, and cause the screen to display the one or more context based multimodal predictions in the electronic device.Type: ApplicationFiled: August 29, 2018Publication date: March 21, 2019Inventors: Barath Raj KANDUR RAJA, Arko SABUI, Ayan PAUL, Ketki Aniruddha GUPTE, Himanshu ARORA, Vibhav AGARWAL, Yellappa DAMAM
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Publication number: 20190087087Abstract: A non-volatile recording medium has recorded thereon a program for causing a computer of an information processing apparatus to, when displaying a virtual electronic apparatus on a first display, display a first display area and a second display area on the first display, the first display area and the second display area each respectively capable of displaying at least part of contents stored as a display target in a virtual memory of the virtual electronic apparatus, the first display area being displayed on the first display as a virtual display of the virtual electronic apparatus, and the second display area being capable of displaying, within one screen in the second display area, more contents than a maximum amount displayable within one screen in the first display area from among the stored contents of the display target.Type: ApplicationFiled: August 31, 2018Publication date: March 21, 2019Applicant: CASIO COMPUTER CO., LTD.Inventor: Manato ONO
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Publication number: 20190087088Abstract: Provided is a keyboard for typing Chinese character, which includes a first base unit key group including subgroups of base unit keys having similar shapes to each other, a second base unit key group including base unit keys having symmetrical shapes with each other, and a third base unit key group including subgroups of base unit keys which are different from the base unit keys included in the first base unit key group and having similar shapes to each other.Type: ApplicationFiled: September 18, 2018Publication date: March 21, 2019Inventors: Kunsoo PARK, Hyunjoon KIM, Hyun-Kyung NOH
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Publication number: 20190087089Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.Type: ApplicationFiled: March 7, 2018Publication date: March 21, 2019Inventors: Hideki Yoshida, Shinichi Kanno
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Publication number: 20190087090Abstract: Embodiments of the present application relate to a method for scheduling virtual disk input and output (I/O) ports, a device for scheduling virtual disk I/O ports, and a computer program product for scheduling virtual disk I/O ports. A method for scheduling virtual disk I/O ports is provided. The method includes assigning a set of service quality ratings to a corresponding set of virtual disk I/O ports based on a set of reading-writing bandwidth quotas associated with the corresponding set of virtual disk I/O ports in a physical machine, determining a total forecast value of a data bandwidth to be used by reading-writing requests and determining virtual disk I/O ports, allocating reading-writing bandwidth limits to the virtual disk I/O ports, and scheduling virtual disk I/O ports on the physical machine.Type: ApplicationFiled: September 17, 2018Publication date: March 21, 2019Inventors: Xiaobo Li, Weicai Chen, Bo Chen
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Publication number: 20190087091Abstract: A method of managing memory descriptors for a plurality of commands to a non-volatile semiconductor storage device includes requesting memory descriptors from a host system for each of the plurality of commands stored in a first memory, storing the memory descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in a second memory of the non-volatile semiconductor storage device, and maintaining a dynamic descriptor list in the second memory for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the second memory having associated memory descriptors. At least one of the occupied descriptor regions includes multiple memory descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.Type: ApplicationFiled: November 5, 2018Publication date: March 21, 2019Inventor: Sancar Kunt OLCAY
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Publication number: 20190087092Abstract: In an embodiment of the invention, a method comprises: recording application-level heuristics and IO-level (input/output-level) heuristics; correlating and analyzing the application-level heuristics and IO-level heuristics; and based on an analysis and correlation of the application-level heuristics and IO-level heuristics, generating a policy for achieving optimal application performance. In another embodiment of the invention, an apparatus comprises: a system configured to record application-level heuristics and IO-level heuristics, to correlate and analyze the application-level heuristics and IO-level heuristics, and based on an analysis and correlation of the application-level heuristics and IO-level heuristics, to generate a policy for achieving optimal application performance.Type: ApplicationFiled: November 19, 2018Publication date: March 21, 2019Inventor: Murali Nagaraj
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Publication number: 20190087093Abstract: A computing device includes a first processor; a second processor; a network interface communicably coupling the first and second processors to a network; an interface bus communicably coupling the first processor to the second processor; a first interface communicably coupling the second processor to the interface bus; a second interface communicably coupling the second processor to the interface bus, the second interface being separate from the first interface, wherein the second interface is configured to provide the second processor with management functionality over one or more hardware components of the computing device; and storage means communicably coupled to the second processor, wherein the second processor regulates access of the first processor to the storage means.Type: ApplicationFiled: November 6, 2018Publication date: March 21, 2019Inventor: Keicy Chung
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Publication number: 20190087094Abstract: A storage controller coupled to a storage array comprising one or more storage devices initiates a transformation of data from a block-based storage system resident on the storage array to a file-based storage system resident on a storage array. The storage controller identifies a plurality of data blocks to be transformed from the block-based storage system and generates metadata for a file in the file-based storage system, the metadata to associate the plurality of data blocks with the file.Type: ApplicationFiled: November 19, 2018Publication date: March 21, 2019Inventors: Ethan Miller, Lydia Do, John Colgrove
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Publication number: 20190087095Abstract: Provided are a computer program product, system, and method for managing point-in-time copies for extents of data. A point-in-time copy for at least one range of extents in at least one volume for a point-in-time copy identifier is established. Change recording information is generated indicating each of the at least one range of extents less than all of the extents in the at least one volume. An update to data in the at least one range of extents in the point-in-time copy is received and data in the source storage in the at least one range of extents to be updated is copied as changed data to the target storage. Indication is made in the change recording information of the data in the at least one range of extents that has been updated.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Inventors: Richard M. Abbott, Theresa M. Brown, Preston A. Carpenter, Ben Esparza
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Publication number: 20190087096Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Raj RAMANUJAN, Kuljit Singh BAINS, Liyong WANG, Wesley QUEEN
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Publication number: 20190087097Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory using first data. The controller is configured to write either the first data or second data into the nonvolatile memory based on a total write amount of user data into the nonvolatile memory. The second data is compressed data of the first data.Type: ApplicationFiled: March 2, 2018Publication date: March 21, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shingo KIKUKAWA, Satoshi KABURAKI
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Publication number: 20190087098Abstract: Read-only or pseudo table of contents (TOC) register. A value for a register to be used to access a reference data structure for a given module is obtained. The register is a virtual register that provides the value for the given module absent backing the register in memory. The value is used to access the reference data structure to obtain a variable address to be used by the given module.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190087099Abstract: Read-only or pseudo table of contents (TOC) register. A value for a register to be used to access a reference data structure for a given module is obtained. The register is a virtual register that provides the value for the given module absent backing the register in memory. The value is used to access the reference data structure to obtain a variable address to be used by the given module.Type: ApplicationFiled: November 27, 2017Publication date: March 21, 2019Inventors: Michael K. Gschwind, Valentina Salapura
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Publication number: 20190087100Abstract: A storage device includes a first non-volatile memory comprising a plurality of first banks having a plurality of first addresses and a second non-volatile memory comprising a plurality of second banks having a plurality of second addresses assigned to each according to different assignment policies, and a controller. The plurality of second addresses corresponds to the plurality of first addresses. The second non-volatile memory mirrors data items stored in the first addresses to store them in the second addresses. The controller is configured to receive a command from a host to control the first non-volatile memory and the second non-volatile memory. The controller provides a read command received from the host simultaneously to first and second non-volatile memories, and outputs to the host an earlier one between data provided from the first non-volatile memory and data provided from the second non-volatile memory based on the read command.Type: ApplicationFiled: May 22, 2018Publication date: March 21, 2019Inventor: Byoung Geun Kim
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Publication number: 20190087101Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.Type: ApplicationFiled: September 7, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Shizuka ENDO, Riki SUZUKI, Yoshihisa KOJIMA
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Publication number: 20190087102Abstract: Embodiments of the disclosure provide a method, apparatus, and computer readable medium for optimizing memory card performance.Type: ApplicationFiled: July 15, 2018Publication date: March 21, 2019Inventors: Jinsuo Yu, Xuewu Zhang
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Publication number: 20190087103Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Inventor: Toru Tanzawa
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Publication number: 20190087104Abstract: A system maintains a consistency database that maintains a status (current, down, stale) for copies of logical storage volumes stored on storage nodes. As failures are detected, the consistency database is updated. Copies are synchronized with one another using information in the consistency database. Write operations on a primary node for a slice of a logical storage node are assigned a virtual block address (VBA) that is mapped to a logical block address (LBA) within the slice. Consistency of the VBAs of the primary node and that of a secondary node is evaluated and used to detect currency. VBA holes are detected and corresponding write commands resent to maintain currency. Physical segments on the primary node are assigned virtual segment identifiers (VSID) that are maintained consistent with VSIDs on clone nodes so that they can be used for garbage collection and synchronization.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Inventors: Gurmeet Singh, Ripulkumar Hemantbhai Patel, Partha Sarathi Seetala
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Publication number: 20190087105Abstract: A system maintains a consistency database that maintains a status (current, down, stale) for copies of logical storage volumes stored on storage nodes. As failures are detected, the consistency database is updated. Copies are synchronized with one another using information in the consistency database. Write operations on a primary node for a slice of a logical storage node are assigned a virtual block address (VBA) that is mapped to a logical block address (LBA) within the slice. Consistency of the VBAs of the primary node and that of a secondary node is evaluated and used to detect currency. VBA holes are detected and corresponding write commands resent to maintain currency. Physical segments on the primary node are assigned virtual segment identifiers (VSID) that are maintained consistent with VSIDs on clone nodes so that they can be used for garbage collection and synchronization.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Inventors: Gurmeet Singh, Ripulkumar Hemantbhai Patel, Partha Sarathi Seetala
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Publication number: 20190087106Abstract: A memory system includes a nonvolatile memory device and a controller circuit. The nonvolatile memory device includes a plurality of physical blocks, each including a storage area which is accessible in units of pages. The controller circuit is configured to control reading and writing of data which are performed on the plurality of physical blocks in units of pages. The controller circuit is also configured to execute a first process on the plurality of physical blocks by performing a second process of reading and a third process of data verification on a first page across each of the plurality of physical blocks and then performing the second process of reading and the third process of data verification on a second page across each of the plurality of physical blocks.Type: ApplicationFiled: February 27, 2018Publication date: March 21, 2019Inventor: Takahiro MASAKAWA
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Publication number: 20190087107Abstract: According to one embodiment, a memory system includes an intermediate value memory that holds decoded words of first and second component codes and reliability information and calculates a soft-input value of the first component code based on at least a decoded word concerning the second component code and reliability information and read information, decodes the soft-input value of the first component code, thereby calculating a decoded word of the first component code and reliability information, updates the intermediate value memory with the calculated decoded word and reliability information, calculates a soft-input value of the second component code based on at least the decoded word of the first component code and the reliability information and read information, decodes the soft-input value of the second component code, thereby calculating a decoded word of the second component code and reliability information, and updates the intermediate value memory with the calculated decoded word and reliability iType: ApplicationFiled: March 7, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventor: Daiki WATANABE
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Publication number: 20190087108Abstract: Systems and methods for performing file-level restore operations for block-level data volumes are described. In some embodiments, the systems and methods restore data from a block-level data volume contained in secondary storage by receiving a request to restore one or more files from the block-level data volume, mounting a virtual disk to the block-level data volume, accessing one or more mount paths established by the virtual disk between the data agent and the block-level data volume, and browsing data from one or more files within the block-level data volume via the established one or more mount paths provided by the virtual disk.Type: ApplicationFiled: November 6, 2018Publication date: March 21, 2019Inventors: Sri Karthik Bhagi, Sunil Kumar Gutta, Vijay H. Agrawal, Rahul S. Pawar
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Publication number: 20190087109Abstract: Methods and apparatus for efficiently storing and accessing secure data are disclosed. The method of storing includes encrypting data utilizing an encryption key to produce encrypted data, performing deterministic functions on the encrypted data to produce deterministic function values, masking the encryption key utilizing the deterministic function values to produce masked keys and combining the encrypted data and the masked keys to produce a secure package. The method of accessing includes de-combining a secure package to reproduce encrypted data and masked keys, selecting a deterministic function, performing the selected deterministic function on the reproduced encrypted data to reproduce a deterministic function value, de-masking a corresponding masked key utilizing the reproduced deterministic function value to reproduce an encryption key, and decrypting the reproduced encrypted data utilizing the reproduced encryption key to reproduce data.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventor: Jason K. Resch
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Publication number: 20190087110Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Yung-Chun Li, Ping-Hsien Lin, Yu-Ming Chang
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Publication number: 20190087111Abstract: A method of managing data in a redundant array of independent disks (RAID) system includes receiving data and allocating a first storage space on a first storage medium at a data management layer based on received data. The method also includes instantiating a data translation layer based on the data management layer configured to communicate with a data protection layer. The method also includes translating the received data from the first storage space on the first storage medium using the data translation layer to a second storage space on a second storage medium and transmitting the data.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventor: Chetan Bendakaluru Lingarajappa
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Publication number: 20190087112Abstract: An information system according to one embodiment of this invention includes a first computer which is an SDS (Software Defined Storage) having a virtualization function and a second computer which is an SDS. The first computer can provide a logical volume using a volume in the second computer as a storage region by the virtualization function. When the information system receives a direction to install a storage control program to the second computer, the information system specifies the logical volume using the volume of the second computer as the storage region among logical volumes in the first computer, and then moves data stored in the volume of the second computer used by the specified logical volume as the storage region to a storage device in the first computer. Thereafter, the storage control program is installed in the second computer.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: Akira YAMAMOTO, Takahiro YAMAMOTO
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Publication number: 20190087113Abstract: According to one embodiment, a storage device is configured to store unencrypted user data. The user data is erased according to at least one data erasure mechanism. The storage device comprises a receiver configured to receive an inquiry from a host device, and a transmitter configured to transfer response information indicating the at least one data erasure mechanism to the host device.Type: ApplicationFiled: March 14, 2018Publication date: March 21, 2019Inventors: Hiroshi Isozaki, Teruji Yamakawa
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Publication number: 20190087114Abstract: A data processing system includes: a host suitable for managing a plurality of data in a tree structure including pointer values and key values, each of the data including distinction information for distinguishing between the pointer values and the key values; and a memory system including a controller for controlling a first memory device and a second memory device, wherein the controller divides each of the data applied from the host into the pointer values and the key values based on the distinction information and subsequently, stores the pointer values of the data in the first memory device and the key values of the data in the second memory device.Type: ApplicationFiled: April 6, 2018Publication date: March 21, 2019Inventor: Hae-Gi CHOI
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Publication number: 20190087115Abstract: One embodiment facilitates in-line deduplication in a storage device. During operation, the system receives, by a controller of the storage device, data to be stored. The system generates a key for the data based on a hash associated with the data. The system stores the key in a first data structure based on a logical block address of the data. In response to determining that an entry corresponding to the key exists in a second data structure, wherein the entry indicates a physical block address at which the data is stored, the system modifies metadata associated with the key and the logical block address, thereby facilitating the storage device to determine duplicate data and store the duplicate data at only one location on the storage device.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Applicant: Alibaba Group Holding LimitedInventor: Shu Li
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Publication number: 20190087116Abstract: A management apparatus, which is configured to manage at least one storage system, includes a processor and a memory. Each of the at least one storage apparatus includes a plurality of volumes, each of which stores at least one OS. The processor is configured to: determine, for each of the plurality of volumes, an OS type and version of a representative OS of the each of the plurality of volumes; select, from among the plurality of volumes, a plurality of volumes having representative OSes that share the same OS type and major version; and include the selected plurality of volumes in one deduplication group made up of volumes among which deduplication is to be executed.Type: ApplicationFiled: June 3, 2016Publication date: March 21, 2019Applicant: HITACHI, LTD.Inventors: Atsushi TSUDA, Masakazu KOBAYASHI, Yuichiro NAGASHIMA, Tetsuya UEHARA, Yohei TSUJIMOTO
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Publication number: 20190087117Abstract: Systems and method for implementing deduplication process based on performance analyses. The system may include a processing device to determine a first performance metric associated with retrieving a second stored data block that is within a specified range of a duplicate of the first data block and a second performance metric associated with retrieving a hash value corresponding to the second stored data block. The processing device further to retrieve the second stored data block within a specified range of the duplicate of the first data block in response to the first performance metric not exceeding the second performance metric.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: John Colgrove, Ronald Karr, Ethan L. Miller
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Publication number: 20190087118Abstract: The disclosed computer-implemented method for performing live migrations of software containers may include (i) identifying a request to migrate a software container from a source computing system to a target computing system while a process executes within the software container, (ii) creating a checkpoint of the process in execution (iii) transferring the checkpoint to the target computing system, (iv) updating the checkpoint recurrently by recurrently creating an incremental checkpoint of the process and merging the incremental checkpoint into the checkpoint, (v) predicting, before updating the checkpoint with an iteration of the incremental checkpoint and based on a size of the iteration of the incremental checkpoint, that finalizing a migration of the software container to the target computing system would meet a predetermined time objective, and (vi) finalizing the migration of the software container to the target computing system.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Inventors: Gaurav Makin, Kody Kantor, Hao Wen, Zhichao Cao, Vallari Mehta
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Publication number: 20190087119Abstract: A characteristic data pre-processing system includes a data acquisition device that collects characteristic data including first cell distribution data defined according to first default read levels, and second cell distribution data defined according to second default read levels, a data pre-processing apparatus that merges the first cell distribution data and the second cell distribution data according crop ranges to generate training data, wherein the crop ranges are defined according to the first default levels and the second default levels, and a database that stores the training data communicated from the data pre-processing apparatus.Type: ApplicationFiled: April 16, 2018Publication date: March 21, 2019Inventors: HYUN KYO OH, SEUNG KYUNG RO, HYE RY NO, JIN BAEK SONG, DONG GI LEE, HEE WON LEE, DONG HOO LIM
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Publication number: 20190087120Abstract: A method for execution by a computing device of a dispersed storage network. The method begins by determining whether frequency of access to a set of encoded data slices exceeds a frequently accessed threshold. The method continues, when the frequency of access exceeds the frequently accessed threshold, by determining an access amount indicative of a degree that the frequency of access exceeds the frequently accessed threshold. The method continues by generating a number of additional encoded data slices and storing the number of additional encoded data slices in a number of additional storage units, wherein the set of storage units and the number of additional storage units produce an expanded set of storage units. The method continues by sending a plurality of data access requests to subsets of the expanded set of storage units in a distributed manner to improve processing efficiency of the plurality of data access requests.Type: ApplicationFiled: November 15, 2018Publication date: March 21, 2019Inventor: Andrew G. Peake
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Publication number: 20190087121Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.Type: ApplicationFiled: February 27, 2018Publication date: March 21, 2019Inventors: Hiroyuki KOBAYASHI, Jun DEGUCHI, Junji WADATSUMI, Takashi TOI
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Publication number: 20190087122Abstract: A controller is configured to receive a write request from a host, and send an intermediate parity generation command corresponding to a specified address indicated by the write request to a first storage device in storage devices. The intermediate parity generation command instructs generation of an intermediate parity from new data at the specified address and old data that is updated to the new data. The intermediate parity generation command includes a first address in the memory area at which the new data is stored and a second address in the memory area for storing the intermediate parity. The first storage device is configured to receive the intermediate parity generation command, acquire the new data from the first address, generate the intermediate parity from the new data and the old data stored in the first storage device, and store the intermediate parity at the second address.Type: ApplicationFiled: September 16, 2016Publication date: March 21, 2019Inventors: Kenta SHINOZUKA, Takahiko TAKEDA, Isamu KUROKAWA, Sho SAWADA
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Publication number: 20190087123Abstract: Techniques are provided in which a ring buffer comprises multiple slots for a queued sequence of data items. New data items are sequentially added to the queued sequence and sequentially removed for further processing. A base record comprises a reference indicator, wherein a value of the reference indicator is indicative of a current slot of the multiple slots of the ring buffer. A pending update record is provided comprising a subject slot indicator, an update slot indicator, and a next update pointer for pointing to another pending update record. The base record further comprises a pending update record pointer. When there is an update to be applied to the value of the reference indicator of the base record, but the update is out-of-order, i.e. references a different slot to the current slot, a new pending update record is generated indicative of the update. Techniques for allocating and releasing elements in an array shared by multiple threads are also disclosed.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Inventor: Eric Ola Harald LILJEDAHL
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Publication number: 20190087124Abstract: Embodiments described herein relate to adjusting performance of a virtualization layer to reduce underutilization of a physical device. The virtualization layer virtualizes access to the device for a VM. When a guest in the VM makes a request to a virtual device, the virtualization layer and the device work together to satisfy the request. Some time is spent by the virtualization layer (software/CPU time), for instance delivering the request from the VM to the physical device, mapping the request from the virtual device to the physical device, etc. Additional time is spent by the device in performing the request (device time). The software/CPU time relative to the device time serves as a basis for deciding whether to increase or decrease processing capacity of the virtualization layer (or a component thereof), thus reducing underutilization of the device and over-provisioning of processing capacity to the virtualization layer.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Inventors: Attilio Mainetti, Murtaza Ghiya
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Publication number: 20190087125Abstract: A memory system includes a non-volatile memory device and a memory controller. The memory controller includes a first counting circuit configured to count a number of times reading is performed on a first unit of data, a second counting circuit configured to count a number of times reading is performed on a second unit of data, which has a size smaller than that of the first unit of data and is a part of the first unit of data, when the number of times reading has been performed on the first unit of data exceeds a first threshold value, and a cache control circuit configured to cache the second unit of data in response to a read request for the second unit of data, when the number of times reading has been performed on the second unit of data exceeds a second threshold value.Type: ApplicationFiled: March 1, 2018Publication date: March 21, 2019Inventors: Mariko MATSUMOTO, Masaaki TAMURA, Takamasa HIRATA
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Publication number: 20190087126Abstract: A memory system includes: one or more memory devices each including a plurality of memory dies each having a plurality of planes; and a controller including: a random command queue suitable for queueing a plurality of random read commands; a multi-read command queue suitable for queueing at least merged random read commands; a read rule checker suitable for storing a multi-read rule representing a direction for selecting two or more among the planes; a command arbitrator suitable for merging two or more random read commands satisfying the multi-read rule among the random read commands queued in the random read commands, and queueing at least the merged random read commands in the multi-read command queue; and a processor suitable for controlling the memory devices to perform a multi-plane read operation according to the merged random read commands in the multi-read command queue.Type: ApplicationFiled: March 27, 2018Publication date: March 21, 2019Inventor: Dong-Yeob CHUN
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Publication number: 20190087127Abstract: A memory system includes: a memory device including a plurality of banks; and a memory controller suitable for: controlling an operation of the memory device, calculating row hammer information for each of the banks for each program having a command set requested from a host, and scheduling the banks based on the row hammer information for each of the banks corresponding to a specific program when the specific program is requested from the host.Type: ApplicationFiled: March 29, 2018Publication date: March 21, 2019Inventor: Woong-Rae KIM
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Publication number: 20190087128Abstract: A memory system includes a memory device including blocks each having pages, planes each having the blocks and dies each having the planes; and a controller for managing the blocks grouped in units of super blocks, wherein the controller includes command queues in which commands for controlling command operations of the dies are stored, and when an erase operation is performed on a second super block in a time period where a program operation including “M” super block page unit program operations is performed on a first super block, divided erase commands obtained by dividing erase commands for the second super block in units of dies are distributed and stored in locations corresponding to discontinuous “N” moments among successive M+1 moments so that the erase operation is distributed and performed on the second super block at the discontinuous “N” moments by being divided in units of dies.Type: ApplicationFiled: April 19, 2018Publication date: March 21, 2019Inventor: Beom-Ju SHIN
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Publication number: 20190087129Abstract: A memory system includes a plurality of memory devices configuring a plurality of ways, and a memory controller communicating with the plurality of memory devices through a channel, wherein each of the plurality of memory devices includes a device queue, and wherein the device queue queues a plurality of controller commands inputted from the memory controller.Type: ApplicationFiled: April 24, 2018Publication date: March 21, 2019Inventor: Byoung Sung YOU
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Publication number: 20190087130Abstract: A method of operating a key-value storage device includes a key-value storage device receiving from a host a first command including a first key, a first value, and a first snapshot identification (ID), the key-value storage device generating a first snapshot entry including the first snapshot ID, the first key, and a first physical address in a non-volatile memory device at which the first value is written, in response to the received first command, receiving from the host a second command including the first key, a second value, and a second snapshot ID, and in response to the received second command, the key-value storage device generating a second snapshot entry including the second snapshot ID, the first key, and a second physical address in the non-volatile memory device at which the second value is written.Type: ApplicationFiled: August 6, 2018Publication date: March 21, 2019Inventors: YONG-HWA LEE, YOUNG-HO PARK, BYUNG-KI LEE, HYUNG-CHUL JANG, JE-KYEOM JEON, SUNG-KUG CHO