Abstract: A configurable processor comprises a processor substrate with a front side and a backside. A programmable memory array is disposed on the backside for storing a look-up table (LUT) for a mathematical function, while an arithmetic logic circuit (ALC) is disposed on the front side for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.

Abstract: An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

Abstract: An arithmetic processor includes a plurality of arithmetic circuits that individually execute an arithmetic operation for fixed point data; and at least one of first and second statistical information is acquired regarding a plurality of fixed point data that are results of arithmetic operation executed by the plurality of arithmetic circuits. The first statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from a least-significant-bit position to a highest-order bit position for each of the digits corresponding to the bit positions, and the second statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order-bit position for each of the digits corresponding to the bit positions.

Abstract: A random number generating system and a random number generating method thereof are provided. The random number generating system includes a random number generator, a random mask circuit, a bit reduction logic circuit and a receiver. The random number generator provides a random number sequence. The random mask circuit receives the random number sequence to provide a random number mask sequence and a random mask indication sequence, wherein bits of the random mask indication sequence in a first logical level corresponded to bits of the random number mask sequence in the high impedance state. The bit reduction logic circuit receives the random number sequence and the random mask indication sequence to provide the comparison key. The receiver receives a random number mask sequence to provide a verification key, where the verification key is the same as the comparison key.

Abstract: A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.

Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.

Abstract: The present invention provides methods and apparatus to generate a statistical object, the deterministic statistical representation of an original object, using a Deterministic Random Bit Generator (DRBG) (10). Multiple DRBG Statistical Object Generators (10) may be chained together to increase security by using independent security configurations (22) for each DRBG Statistical Object Generator (10).

Abstract: A method operating a memory system, can be provided by reading a plurality of data words from a memory system, where each of the plurality of data words is stored in the memory system in a first dimension-major order. The plurality of data words can be shifted into a transpose memory system in the first dimension in parallel with one another using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimension-major order in the transpose memory system relative to the memory system. The plurality of transposed data words can be shifted out of the transpose memory system in the second dimension using second directly time adjacent clock edges.

Abstract: Apparatus and methods for an intelligent audit engine are provided. Product development artifacts may be associated with artifact tags and stored in an artifact repository. The audit engine may retrieve an artifact for audit. The audit engine may identify a set of development guidelines in a rule repository based on their artifact tags. The audit engine may determine whether the development guidelines have been satisfied based on stored product testing data. A failed development guideline may initiate a workflow that includes notification of a project stakeholder regarding the failure. The notification may include remediation measures to be taken by the stakeholder. The validation process may iterate until all guidelines have passed validation. A machine-learning algorithm may prioritize a development guideline for future audits to increase efficiency. The machine learning algorithm may educate stakeholders to reduce audit failures.

Abstract: A system and method for feature switching in software applications. A feature switching action (FSA) is received and at least one user device is identified based on the received FSA. At least one feature switching instruction (FSI) is generated based on the received FSA and the FSI is sent to at least one of the identified user devices. A feature switching instruction response (FSIR) is received from each user device that received a FSI and a feature switching action response (FSAR) is generated based on the received FSIRs.

Abstract: A method, an apparatus, and a computer program product for optimizing variable size arguments in a programming language are provided. The method includes finding, in a target program, a call site having a variable-length argument. The method also includes generating a converted code for a callee of the call site, the generating including converting the variable-length argument to a plurality of arguments. The method further includes translating the call site to a call code for calling the converted code with the plurality of arguments instead of the variable-length argument.

Abstract: Application personalization techniques and systems are described that leverage an embedded machine learning module to preserve a user's privacy while still supporting rich personalization with improved accuracy and efficiency of use of computational resources over conventional techniques and systems. The machine learning module, for instance, may be embedded as part of an application to execute within a context of the application to learn user preferences to train a model using machine learning. This model is then used within the context of execution of the application to personalize the application, such as control access to digital content, make recommendations, control which items of digital marketing content are exposed to a user via the application, and so on.

Abstract: Systems and methods relate to creating applications using building blocks linked together with metadata. A user interface can enable a user to create an application. Creating the application can include defining a new building block configured to generate output data. The new building block can include one or more existing building blocks and the metadata associated with the existing building blocks. For example, a building block can include at least one input/output (I/O) feature configured to receive inputs and/or generate outputs. Further, the existing building block can correspond to a data structure including external I/O features. The new building block can be linked to an existing building block by mapping an external I/O feature of the existing building block to an open I/O feature of the new building block. The mapping can be stored in metadata associated with the new building block.

Abstract: Embodiments of systems and methods disclosed herein provide an application development platform in an enterprise computing environment. More specifically, in certain embodiments, systems and methods are disclosed that enable an application development platform to reuse, extend, and/or customize entity-based applications in an enterprise computing environment. The application development platform can extend an entity to include user configured settings including zero or at least one of a property, a permission, an action, a behavior, or a resource to the entity to generate user customized versions of the entity. The applications may be customized by an end user, while allowing the underlying application to be updated without losing any user customizations.

Abstract: A system may determine one or more data sources which the system is configured to access. The system may provide a set of application programming interfaces (APIs) for interacting with data stored in one or more data sources. The APIs may be accessible to one or more web applications which the system is configured to serve. The system may determine that a web application has requested an operation for interacting with the data through one or more APIs in the set of APIs. The system may determine one or more responses based at least in part on the operation requested by the web application. The system may provide the response(s) to the web application.

Abstract: A system constituting an application platform, comprising: an application content manager that: causes developers to register filters in a filter store; enables a user who uses an AppWriter to use the registered filters; causes the AppWriter to provide a method for configuring a content process pipeline without coding; automatically processes the content while periodically executing the configured pipeline; and causes a general-purpose repository to store different kinds of contents, and an application generator that: causes a resource store to provide resources necessary for app-writing and operation; causes the AppWriter to provide a WYSIWYG-type UI capable of producing an application that provides a desired function and UI without a prior knowledge for creation of the application; causes an application renderer to output an application source to an UI adapted to the platform; and causes the content pipeline to provide a repository that stores the created content and operate repositories.

Abstract: Techniques for identifying similar software code are provided. In one example, a computer-implemented method comprises: based on detection of an input, determining, by a device operatively coupled to a processor, a user interface functionality associated with a website; and based on a likelihood that the user interface functionality and a result of a query have a defined level of correlation, matching, by the device, the result of the query to the user interface functionality. The computer-implemented method can further comprise mapping, by the device, a vector associated with the website, to an integer value, employing a hash function.

Abstract: A method and apparatus are disclosed for enhancing operable functionality of input source code files from a software program by identifying a first code snippet and a first library function which generate similar outputs from a shared input by parsing each and every line of code in a candidate code snippet to generate a templatized code snippet data structure for the first code snippet, and then testing the templatized code snippet data structure against extracted library function information to check for similarity of outputs between the first code snippet and the first library function in response to a shared input so that the developer is presented with a library function recommendation which includes the first code snippet, the first library function, and instructions for replacing the first code snippet with the first library function.

Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Abstract: Embodiments described herein provide a solution for optimizing a compiling of program code. A proposed state pointer, which corresponds to a current state pointer to a current state node that represents a section of the program code, is added in an intermediate language (IL) representation of the program code. When the optimizing compiler determines that an optimization should be made to a section of code, the current state node is copied to create a proposed state node, which is then referenced by the proposed state pointer. The proposed state node is edited to include the optimization while the current state node remains unchanged. The success of the optimization is evaluated, and an updated IL representation is generated in which any references to nodes that are no longer included in the flow of the former IL representation are removed.

Abstract: Systems, methods, devices and non-transitory, computer-readable storage mediums are disclosed for automated mobile app integration.

Abstract: In response to an attempt to install an instance of a container in a production environment, a set of security criteria associated with the container and features of the production environment are compared. Based on the comparison, a determination is made as to whether the features of the production environment satisfy the set of security criteria.

Abstract: A control apparatus according to one aspect of the present disclosure is a control apparatus configured to control updating of a control program to be used to control a target device installed in a vehicle by an on-vehicle control device for controlling the target device. This control apparatus includes: a prediction unit configured to predict a parking/stopping time period of the vehicle to obtain a first time period as a predicted time period; and an updating control unit configured to control, based on the first time period, a process regarding updating of the control program.

Abstract: Systems and methods are provided for obtaining a build object over a communication network, the build object comprising at least a portion of a first build. The build object is stored locally. A build modification object is obtained over the communication network, the build modification object comprising a change between the first build and a second build. The build object updated using the build modification object obtained over the communication network. At least a portion of the updated build object is provided to a first peer build system over the communication network.

Abstract: A facility is provided for automatically updating a version of a base image included within an application container of a container-based processing environment. The facility includes providing an application container having an associated configuration file with automatic update specified in connection with a referenced based image. The application container includes an existing version of the referenced base image. Availability of an updated version of the base image with the container-based processing environment is identified, and based on identifying availability of the updated version of the base image, the application container is automatically updated to an updated container, which includes the updated version of the base image.

Abstract: Forward and/or backward compatibility between an invoking program and the invoked program can be maintained by using compatibility indicators and/or annotations to configuration settings that specify the desired behavior of the invoked program. Compatibility indicators and/or annotations can be used to override default behavior to ensure compatibility between a version of a program and a version or revision of a dependency of the program. Annotations can be made to configuration settings or to initialization programs and/or files. Configuration and/or initialization settings for the program can be annotated to indicate when default behavior of the dependency is to be overridden to provide alternate behavior. Configuration settings for the program can be annotated to indicate when future revisions to the dependency are to be applied.

Abstract: Tracking a function in a source code file includes determining an author of an initial version of the source code file, and generating a data structure for one or more functions in the initial version. The determined author is associated as a function author of the one or more functions. In response to a new version of the source code file being committed, one or more added or changed functions are identified, and an author of the new version of the source code file is determined. The data structure for each changed function is updated to associate the author of the new version of the source code file as the function author for a new version of the changed function, and a new data structure is generated for each added function associating the author of the new version as a function author of the added function.

Abstract: In response to detecting a code change request for a particular file of multiple files of a software build during testing, a computer generates a sensitivity rating of the particular file to cause breaks in the software build based on a relative level of failure of the particular file as compared to the multiple files based on one or more factors. The computer outputs a response to the code change request based on the sensitivity rating to one or more integrated development environment interfaces with access to the particular file of the software build. The computer uses the sensitivity rating to determine whether to grant the code change request.

Abstract: The example embodiments are directed to a framework that supports multiple runtime environments. In one example, a method includes exporting a software application to a runtime environment via a framework that supports multiple runtime environments, selecting a runtime template based on the export runtime environment, wherein the selected runtime template transforms data being ingested by the software application based on the export runtime environment, executing the software application in the export runtime environment, and controlling data ingestion into the executing software application based on the selected runtime template. According to various aspects, the software application may be developed using a programming language that is designed for use with a particular runtime environment, while the runtime template can enable the software application to be executed in a different runtime environment.

Abstract: An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.

Abstract: Instead of logic-based computation (LBC), the preferred processor disclosed in the present invention uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising a memory array on a memory level for storing a look-up table (LUT) and an arithmetic logic circuit (ALC) on a logic level for performing arithmetic operations on selected LUT data. The memory level and the logic level are different physical levels.

Abstract: An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.

Abstract: An apparatus and method are provided for managing address collisions when performing vector operations. The apparatus has a register store for storing vector operands, each vector operand comprising a plurality of elements, and execution circuitry for executing instructions in order to perform operations specified by the instructions. The execution circuitry has access circuitry for performing memory access operations in order to move the vector operands between the register store and memory, and processing circuitry for performing data processing operations using the vector operands. The execution circuitry may be arranged to iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop.

Abstract: Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a memory operation whose execution order is constrained based on a hardware memory model of the first processor ISA. Based on an analysis of the block(s) of processor instructions, it is determined that the memory operation of the at least one instruction can be made order-independent in a hardware memory model of a second processor ISA. Based on the determination, one or more unbarriered processor instructions that are formatted according to the second processor ISA are emitted. The unbarriered processor instruction(s) are structured to perform the memory operation without ordering constraint.

Abstract: An apparatus for gating a load instruction is presented. The apparatus includes a memory to store a prediction table including an entry matching the load instruction. The matching entry includes a tag field to identify the load instruction, a distance field to indicate a distance of the load instruction to a prior aliasing store instruction, and a confidence field to indicate a prediction strength. The apparatus further includes a gating circuit operable to perform a look-up for the load instruction in the prediction table to find the matching entry and responsive to a determination of a valid prediction, retrieve a location of the prior aliasing store instruction using a value of the distance field of the matching entry, and perform a gating operation on the load instruction. The apparatus further includes a load store queue operable to provide feedback for updating the matching entry after the load instruction has executed.

Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

Abstract: A data storage device waking up from a sleep mode rapidly is disclosed. The data storage device uses a controller to operate a non-volatile memory. The controller has a microprocessor and a volatile memory. The microprocessor loads boot code from the non-volatile memory to a not-always-on area of the volatile memory according to a script loaded on an always-on area of the volatile memory. The microprocessor executes the boot code loaded on the not-always-on area to load an in-system program from the non-volatile memory to the not-always-on area for execution of the in-system program.

Abstract: A method and apparatus of installing an operating system are provided. According to an example of the method, a server reads an image file of an operating system from a system providing device, wherein the image file comprises address information corresponding to an automatic response script file, and the automatic response script file is not stored at a position corresponding to the address information. The server receives the automatic response script file provided by the system providing device in response to that the reading by the server advances to the position corresponding to the address information. The server installs the operating system by using the automatic response script file.

Abstract: A server for automatically determining whether to enable a remote control function and a method for automatically enabling the remote control function are provided. The method for automatically enabling the remote control function includes: executing, by a board management controller (BMC), a firmware program to determine a logic level of a general-purpose input/output (GPIO) pin of the BMC; enabling, by the BMC, a remote control function according to a first logic level of the GPIO pin; and skipping enabling, by the BMC, the remote control function according to a second logic level of the GPIO pin.

Abstract: Disclosed are ways to generate and present recommendations which provide a user with the ability to explore the follow-on consequences of accepting the recommendations. In some aspects, a method includes receiving a first user input including a recommendation topic, presenting, via a display, an exploration structure including a node corresponding to the recommendation topic, receiving data corresponding to the node from a knowledge repository, analyzing the received data to determine at least one follow-on recommendation based on the node, and presenting each determined follow-on recommendation in the exploration structure as a child node of the node corresponding to the recommendation topic.

Abstract: Methods, systems, and computer program products for user-initiated dynamic data application programming interface creation are provided herein. A computer-implemented method includes automatically transforming a user-provided query into one or more parameterized queries, generating a data application programming interface based on at least one of the parameterized queries, outputting the generated data application programming interface to the user providing the user-provided query, and storing the generated data application programming interface in a database accessible to one or more additional users.

Abstract: A balancing and control (B&C) system for API transactions is disclosed. The system may write a request confirmation and a request acknowledgement to a blockchain in response to an API request being transmitted from a consumer system to a provider system, with the request confirmation and the request acknowledgement each comprising a request hash of the API request. The system may also write a response confirmation and a response acknowledgement to the blockchain in response to an API response being transmitted from the provider system to the consumer system, with the response confirmation and the response acknowledgement each comprising a response hash of the API response. The blockchain may execute a smart contract to compare the request hashes from the request confirmation and the request acknowledgement and the response hashes from the response confirmation and the response acknowledgement to identify one or more out-of-balance events.

Abstract: A terminal configuration method and system based on a provision protocol for transmission are disclosed. The method comprises: receiving, by a first terminal, a configuration instruction used for configuring a second terminal to form a configuration file; sending, by the first terminal, the configuration file to the second terminal in the manner of a provision text message; and receiving the configuration file by the second terminal and installing the second terminal in terms of the configuration file when an instruction to install the configuration file is received. In this way, the first terminal can remotely assist the second terminal in configuration modification, and thus, the problem that users are unable to independently complete terminal configuration can be solved.

Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: A simulation device includes a hardware processer that simulates an apparatus. When an state of the apparatus does not satisfy a allowable condition, the hardware processor determines a group of the plurality of jobs being executed as an error group, and allows a virtual device to carry out a plurality of jobs that are generated when a parameter defined by at least one of the plurality of jobs included in the error group is changed. When a state of the virtual device satisfies the allowable condition, the hardware processor determines a group of the plurality of jobs executed as a change job group. When the apparatus carries out a plurality of new jobs, the hardware processor allows the apparatus to change each of parameters of the plurality of new jobs to a parameter defined by a change job included in the change job group.

Abstract: A device that includes a node engine configured to determine a core distance for a correlithm object core. The core distance identifies a maximum number of hops away from a root correlithm object. The node engine is further configured to select a correlithm object in an n-dimensional space and set the selected correlithm object as the root correlithm object. The node engine is further configured to identify a plurality of correlithm objects within the core distance from the root correlithm object and link the identified plurality of correlithm objects with the root correlithm object to generate the correlithm object core.

Abstract: A device that includes a node engine configured to define a number of child correlithm objects for a string correlithm object. The node engine is further configured to select a correlithm object from an n-dimensional space and set the selected correlithm object as a parent correlithm object. The node engine is further configured to iteratively identify the defined number of child correlithm objects, where identifying the defined number of child correlithm objects involves randomly selecting correlithm objects less than the standard distance away from the parent correlithm object and defining the selected correlithm objects as a child correlithm object. The node engine is further configured to link the defined child correlithm objects with the parent correlithm object in the node table to generate the string correlithm object.

Abstract: A device that includes a sensor engine and a node engine. The sensor engine is configured to receive an input signal representing a data sample and identify a real world value entry in a sensor table based on the input signal. The sensor engine is further configured to fetch an input correlithm object in the sensor table linked with the real world value entry and send the input correlithm object to a node engine. The node engine is configured to determine distances between the input correlithm object and each of the child correlithm objects in a node table in response to receiving the input correlithm object and identify a child correlithm object from the node table with the shortest distance. The node engine is further configured to fetch a parent correlithm object from the node table linked with the identified child correlithm object and output the identified parent correlithm object.