Patents Issued in June 25, 2019
  • Patent number: 10331347
    Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 25, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayasree Sankaranarayanan, Dipan Kumar Mandal
  • Patent number: 10331348
    Abstract: Communicating data with a medium is provided. A cache is provided for storing target data of a file identified by an access request from an application of a host. The cache is divided into a read cache, a write cache, and an index cache. Responsive to receiving the access request: the medium is loaded onto a drive using a file system; target data is stored to the write cache and to the read cache; and the index file stored in the index cache is updated to reflect position metadata about the target data stored in the write cache. Responsive to initiating unloading of the medium from the drive: the updated index file stored in the index cache is written to the index partition of the medium; and the target data stored in the write cache is written onto a data partition of the medium without using the file system.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ashida, Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe
  • Patent number: 10331349
    Abstract: The present disclosure introduces a method and an apparatus of shrinking virtual hard disk image file. The present techniques search a garbage data block in a file and revise a record of the garbage data block in a block allocation table (BAT). The file includes one or more data blocks and a BAT that records information of each data block. The garbage data block is a data block that does not store effective data. The present techniques move an effective data block subsequent to the garbage data block, revise a record of the effective data block in the BAT after the moving, and shrink a size of the file after the movement.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 25, 2019
    Inventors: Zhen-hua Song, Qian Wang, Jia Wan, Weicai Chen
  • Patent number: 10331350
    Abstract: A computer program product, system, and method for visiting each node of a snapshot tree within a content-based storage system having a plurality of volumes and/or snapshots; for each node, scanning an address-to-hash (A2H) table to calculate one or more resource usage metrics, wherein the A2H tables map logical I/O addresses to chunk hashes; and determining, based on the resource usage metrics, an amount of memory and/or disk capacity that would be freed by deleting one or more of the volumes and/or snapshots.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 25, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Anton Kucherov, Ophir Buchman, David Meiri
  • Patent number: 10331351
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
  • Patent number: 10331352
    Abstract: A device and method dynamically optimize processing of a storage command within a storage system. The device and method execute a rule based on predetermined criteria and internal operation parameters of the storage system. An extended application program interface within the storage system provides internal operation parameters for use in execution of the rule. Based on execution of the rule, the storage system optimizes processing of the storage command.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 25, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yaron Klein
  • Patent number: 10331353
    Abstract: A data access system has host computers having front-end controllers nFE_SAN connected via a bus or network interconnect to back-end storage controllers nBE_SAN, and physical disk drives connected via network interconnect to the nBE_SANs to provide a distributed, high performance, policy based or dynamically reconfigurable, centrally managed, data storage acceleration system. The hardware and software architectural solutions eliminate BE_SAN controller bottlenecks and improve performance and scalability. In an embodiment, the nBE_SAN (BE_SAN) firmware recognize controller overload conditions, informs Distributed Resource Manager (DRM), and, based on the DRM provided optimal topology information, delegates part of its workload to additional controllers. The nFE_SAN firmware and additional hardware using functionally independent and redundant CPUs and memory that mitigate single points of failure and accelerates write performance.
    Type: Grant
    Filed: April 8, 2017
    Date of Patent: June 25, 2019
    Inventor: Branislav Radovanovic
  • Patent number: 10331354
    Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-Soo Yu, Je-Min Ryu, Reum Oh, Pavan Kumar Kasibhatla, Seok-In Hong
  • Patent number: 10331355
    Abstract: A control device, including: a first processor; a second processor which has a higher performance than the first processor; and a storage in which data is stored so as to be readable and writable by the second processor, wherein a part of the storage is usable as a common storage area which is readable and writable by the first processor and the second processor, in reading operation, the second processor reads first data from out of the common storage area in the storage and writes the first data to the common storage area, and the first processor reads the first data from the common storage area, and in writing operation, the first processor writes second data to the common storage area, and the second processor stores the second data out of the common storage area in the storage.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Naoto Toda, Tatsuya Sekitsuka
  • Patent number: 10331356
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Patent number: 10331357
    Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 25, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Betty Ann McDaniel, Michael D. Achenbach, David N. Suggs, Frank C. Galloway, Kai Troester, Krishnan V. Ramani
  • Patent number: 10331358
    Abstract: An improved storage replication scheme removes the bottlenecks in the data replication path and allows for high performance replication, both synchronous and asynchronous. The scheme eliminates storage array controllers from the replication data path and provides an implementation of array based replication which can sustain much higher input/output (I/O) write bandwidth with much lower latency from the application's perspective.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 25, 2019
    Assignee: VEXATA, INC.
    Inventors: Shailendra Jha, Satsheel Altekar
  • Patent number: 10331359
    Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Qamrul Hasan, Shinsuke Okada, Yuichi Ise, Kai Dieffenbach, Kiyomatsu Shouji
  • Patent number: 10331360
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 10331361
    Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: June 25, 2019
    Assignee: National Instruments Corporation
    Inventors: Tai A. Ly, Swapnil D. Mhaske, Hojin Kee, Adam T. Arnesen, David C. Uliana, Newton G. Petersen
  • Patent number: 10331362
    Abstract: Described is a system for identifying data that may differ between files used as part of a replication process. The system may determine a type of segmentation used for segmenting data such as a variable size segmentation or a fixed size segmentation is used. Based on the segmentation of a file, the system may identify segments that may be modified. For example, the system may identify only the particular modified segments within a boundary when a fixed size segmentation is used identify all of the segments within a boundary as modified when a variable segmentation is used. Accordingly, depending on the scenario, the system may determine an efficient mechanism for identifying data to send to a target storage as part of a replication process.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 25, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Harshadrai Parekh
  • Patent number: 10331363
    Abstract: A node includes a controller that includes one or more processors. The controller may be configured to load data from a storage data block of a plurality of storage data blocks stored on one or more first data storage devices to a working data block stored on one or more second data storage devices. In response to a node experiencing a failure, the controller can be configured to determine a change value for the working data block. The controller can be configured to determine whether data stored in the working data block is different than data stored in the corresponding storage data block based on the determined change value and a provided change value that corresponds to the storage data block.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 25, 2019
    Assignee: Seagate Technology LLC
    Inventor: Nathaniel Rutman
  • Patent number: 10331364
    Abstract: A system configuration containing a host, solid state drive (“SSD”), and controller able to perform a hybrid mode non-volatile memory (“NVM”) access is disclosed. Upon receiving a command with a logical block address (“LBA”) for accessing information stored in NVM, a secondary flash translation layer (“FTL”) index table is loaded to a first cache and entries in a third cache is searched to determine validity associated with stored FTL table. When the entries in the third cache are invalid, the FTL index table in the second cache is searched to identify valid FTL table entries. If the second cache contains invalid FTL index table, a new FTL index table is loaded from NVM to the second cache. The process subsequently loads at least a portion of FTL table indexed by the FTL index table in the third cache.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: June 25, 2019
    Assignee: CNEX Labs, Inc.
    Inventor: Yiren Ronnie Huang
  • Patent number: 10331365
    Abstract: A removable non-volatile memory device durably stores a serial number or identifier, which is used to mark multimedia content legally stored on the removable non-volatile memory device. In order to retrieve the serial number, a host electronic system coupled to the removable non-volatile memory device sends a sequence of multiple file access commands to access a predefined target file stored on the removable non-volatile memory device. In accordance with the executed predefined sequence of multiple file access commands, a corresponding sequence of data access commands are received at the removable non-volatile memory device and are interpreted as a request by the host electronic device to read the serial number. The removable non-volatile memory device outputs the serial number in response to the sequence of data access commands.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 25, 2019
    Assignee: MO-DV, INC.
    Inventors: Robert D. Widergren, John L. Douglas, Eric R. Hamilton
  • Patent number: 10331366
    Abstract: A method of operating a data storage device configured to allow a plurality of non-volatile memory devices, including a first non-volatile memory device and second non-volatile memory devices, to lead control of power consumption. The method includes receiving, by each of the second non-volatile memory devices, a state signal indicating operation or non-operation of the first non-volatile memory device and determining, by each of the second non-volatile memory device, whether to operate based on the state signal.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Pil Lee, Seok Won Ahn, Hyun Ju Yi, Jun Ho Choi
  • Patent number: 10331367
    Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first memory and second memory. The first memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 25, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10331368
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: June 25, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10331369
    Abstract: An initializable array has a plurality of blocks each having an address word and a data word, a boundary indicative of a two-division position where the plurality of blocks is divided into two divided areas and an initial value for each element of the array is stored, the boundary is a position where a ratio for the number of unwritten blocks in a first area and the number of written blocks in a second area is an integer ratio. An array control program causes a computer to execute shifting the boundary to extend the first area and generating an initialized written block in the first area; in a case where a write destination block is an unwritten block in the second area, forming a link between the initialized written block in the first area and the write destination block; and writing a write value to the write destination block.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 25, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Katoh, Keisuke Goto, Hiroya Inakoshi
  • Patent number: 10331370
    Abstract: Performance tuning in a storage system that includes one or more storage devices, including: storing, by a primary controller of the storage system, data corresponding to one or more computer processes into one or more of the one or more storage devices, determining, by a secondary controller that is configured similarly to the primary controller, one or more utilization patterns of the data, and initiating, in dependence upon the one or more utilization patterns of the data, a modification to a manner in which the one or more computer processes access the data stored in the one or more storage devices.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Argenis Fernandez, Ronald Karr, David Whitlock, Sergey Zhuravlev
  • Patent number: 10331371
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include receiving a request including a specified number of logical volumes, and identifying, in a storage system including multiple storage pools having storage space, respective first amounts of the storage space that are available in the multiple storage pools. Based on the specified number of logical volumes and the first amounts of the storage space, a set of volume sizes indicating second amounts of the storage space are defined, and a given volume size indicating a maximum size for the specified number of logical volumes is identified. Upon conveying the maximum size to a user, and receiving, from the user, a specified size less than or equal to the maximum size, the specified number of the volumes having the specified size can be provisioned, wherein each of the volumes is stored in a given storage pool.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ohad Atia, Amalia Avraham, Ran Harel, Alon Marx
  • Patent number: 10331372
    Abstract: During conversion and transfer of data from a physical machine to a virtual hard disk, a transmuter generates a catalog of contents of the physical machine. Catalog entries are compared to a set of alterations templates which alter matching data. The altered data is then stored in the virtual hard disk. Alterations templates may include filters that exclude unwanted or duplicated catalog entries, mapping filters that transfer source catalog entries to target locations on the virtual hard disk, and add-on filters that add additional data or location references to catalog entries. The disclosed process allows modifications to be made in a systematic way during data transfer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 25, 2019
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: George Runcie, Derek Rodrigues
  • Patent number: 10331373
    Abstract: A data processing system includes at least one processor core each having an associated store-through upper level cache and an associated store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instructions and a plurality of paste-type instructions, the at least one processor core transmits a corresponding plurality of copy-type and paste-type requests to its associated lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the associated lower level cache copies a respective data granule from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, William J. Starke, Derek E. Williams
  • Patent number: 10331374
    Abstract: Techniques for providing high-performance writable snapshots in data storage systems are disclosed. The techniques include storing a set of snapshots containing changes to a data set over time in a set of allocation units containing a series of contiguous blocks. A set of metadata blocks in the allocation units is used to track a state of data stored in the series of contiguous blocks. Ownership of the allocation units by the snapshots is also tracked in a set of allocation unit mappings between the allocation units and a set of snapshot identifiers representing the snapshots. The allocation unit mappings and metadata blocks are then used to execute writes to the data set and free blocks in the snapshots.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 25, 2019
    Assignee: Oracle International Corporation
    Inventors: Unmesh Rathi, Santosh Sugur, Sridhar Valaguru
  • Patent number: 10331375
    Abstract: A block-level data storage system receives a request to delete a data storage volume. As a result, the data storage volume is deleted and the areas comprising the volume are released and reaped. The areas may contain non-zero data within a plurality of data storage chunks that comprise the areas. An area cleaner is configured to zero out the areas for allocation to a newly created data storage volume.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 25, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Nandakumar Gopalakrishnan, Kerry Quintin Lee, Danny Wei
  • Patent number: 10331376
    Abstract: A system and method for first changing the encryption key on a self-encrypting disk drive followed by a complete disk wipe. Either process can be separately performed, and they can be performed in any order. In fact, one embodiment of the invention, resets the symmetric key, wipes the disk a predetermined number of times with different predetermined data patterns, and then resets the key a second time. This assures that there is absolutely no way to recover the original key or to read the original plain text data, even if some of it's encrypted values remain on unallocated tracks after wiping. A user can be assured that in milliseconds after starting the wiping process, the entire disk is rendered unreadable and unrecoverable.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: June 25, 2019
    Assignee: Whitecanyon Software, Inc.
    Inventors: Donald E. Griffes, Daniel S. Pedigo, Dean V. Nuttall
  • Patent number: 10331377
    Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
  • Patent number: 10331378
    Abstract: A method of operating a memory module can include receiving, at the memory module, an active command and an associated row address that indicates that the active command is directed to a volatile memory device included in the memory module or to a non-volatile memory device included in the memory module. The volatile memory device or the non-volatile memory device can be activated based on the associated row address in response to the active command. Status information can be provided at the memory module indicating readiness of the memory module for receipt of an operation command associated with the active command and the associated row address.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin Cho, Hee Hyun Nam, Hyo-Deok Shin, Junghwan Ryu
  • Patent number: 10331379
    Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai
  • Patent number: 10331380
    Abstract: An apparatus in one embodiment comprises at least one processing device having a processor coupled to a memory. The processing device is configured to distribute in-memory computations across a plurality of data processing clusters associated with respective data zones, and to combine local processing results of the distributed in-memory computations from the data processing clusters. The distributed in-memory computations utilize local data structures of respective ones of the data processing clusters. A given one of the local data structures in one of the data processing clusters receives local data of the corresponding data zone and is utilized to generate the local processing results of that data processing cluster that are combined with local processing results of other ones of the data processing clusters. The local data structures are configured to support batch mode extensions such as Spark SQL, Spark MLlib or Spark GraphX for performance of the distributed in-memory computations.
    Type: Grant
    Filed: April 30, 2017
    Date of Patent: June 25, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Patricia Gomes Soares Florissi, Ofri Masad, Ido Singer
  • Patent number: 10331381
    Abstract: A method and a device for recording memory access operation information are provided by the present disclosure. The method comprises: recording memory access operations between a processor and a memory during a target running process to form an memory access sequence information of the target running process, wherein each of the memory access operation information in the memory access sequence information includes a memory access type, a memory access address and a memory access data; and determining a final storage state of the memory during the target running process according to the memory access sequence information of the target running process. According to the embodiments of the present disclosure, the final storage state of the memory during the target running process may be obtained by using less storage resources, and the hardware overhead is reduced.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: June 25, 2019
    Assignee: Tsinghua University
    Inventors: Leibo Liu, Ao Luo, Shaojun Wei
  • Patent number: 10331382
    Abstract: Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: examining information of first through Nth storage volumes and based on the examining providing for each storage volume of the first through Nth storage volumes a predicted storage space savings value, the predicted storage space savings value indicating a predicted terabyte volume of storage space savings producible by performance of data compression of data stored on the storage volume; predicting a per terabyte compression cost savings associated with compressing one or more storage volume of the first through Nth storage volumes, and providing a ranking of storage volumes of the first through Nth storage volumes based on the examining and the predicting; and scheduling a compression of storage volumes of the first through Nth storage volumes based on the ranking of storage volumes of the first through Nth storage volumes.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: John J. Auvenshine, Per Lutkemeyer, Laura Richardson, David Schustek
  • Patent number: 10331383
    Abstract: A computer-implemented method includes identifying a storage migration. The storage migration is associated with a storage area network. The storage migration has a storage migration rate associated therewith. The method includes identifying an input/output throughput. The input/output throughput is associated with the storage area network. The input/output throughput stores a throughput rate for the storage area network. The method includes identifying a service level agreement rate for the input/output throughput. The method includes identifying a non-essential workload. The non-essential workload stores a non-essential workload rate associated therewith. The non-essential workload includes that portion of said input/output throughput that is for one or more background processes. The method includes determining an analyzed rate based on the throughput rate, the service level agreement rate, and the non-essential workload rate.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: John V. Delaney, Anthony M. Hunt, Maeve M. O'Reilly, Daniel P. Toulan, Clea A. Zolotow
  • Patent number: 10331384
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit of a dispersed storage network includes determining to store data in a storage pool utilizing a maximum accessibility approach. A storage unit performance factor is determined for a plurality of storage units of the storage pool. A number of instances of data storage per storage unit is established based on the storage unit performance factor. A replication factor across the plurality of storage units of the storage pool is also established. A total number C of storage instances for the data is determined based on the number of instances of data storage per storage unit and the replication factor. C number of source names for C storage instances of the data are generated. Storage of the C storage instances of the data is facilitated.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Asimuddin Kazi, Jason K. Resch
  • Patent number: 10331385
    Abstract: In one embodiment, a request to access a first storage location of a storage device may be received, wherein the storage device comprises a data storage and a cache. The cache may be accessed to obtain data for one or more second storage locations of the storage device, wherein the data for the one or more second storage locations has not been written to the data storage, and wherein the first storage location and the one or more second storage locations are located near each other on the data storage. The data storage may then be accessed in response to the request to access the first storage location of the storage device. The data storage may also be accessed to write the data for the one or more second storage locations obtained from the cache.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Andrzej Jakowski, Maciej Kaminski
  • Patent number: 10331386
    Abstract: A system and method of recognizing a hard disk movement, the system and method including recognizing hard disk information recorded in a hard disk in response to the hard disk being moved to a slot in a hard disk array, determining the movement type of the hard disk based on the recognized hard disk information, judging validity of the hard disk movement based on the movement type, and updating the hard disk information of the hard disk in response to the hard disk movement being judged as valid, wherein the hard disk information comprises position information of the hard disk in the hard disk array.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: June 25, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Hongpo Gao, Jamin Jianbin Kang, Huibing Xiao, Xinlei Xu
  • Patent number: 10331387
    Abstract: Sheet feeding has been started after storing image data for one page of a document. A control method for a printing apparatus includes feeding a sheet from a sheet holding unit by a feeding unit, reading an image of a document by a reading unit, storing image data of the document read by the reading unit in a storing unit, and reading out, before image data for one page of the document is stored in the storing unit, the image data of the document from the storing unit and printing, by a printing unit, the image based on the read image data to the sheet fed from the sheet holding unit by the feeding unit, in which the feeding unit is able to start to feed the sheet from the sheet holding unit before the image data for the one page of the document is stored in the storing unit.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 25, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Yoneyama
  • Patent number: 10331388
    Abstract: An image processing system includes at least one image processing apparatus, an information terminal, and an information processing device configured to communicate with the at least one image processing apparatus and the information terminal. The information terminal includes a specifying information transmitter configured to transmit, to the information processing device, specifying information for specifying, from the at least one image processing apparatus, a first image processing apparatus for inputting and a second image processing apparatus for outputting. The information processing device includes an input data retrieval unit configured to obtain input data from the first image processing apparatus for inputting based on the specifying information received from the information terminal, and an output data transmitter configured to transmit, based on the received specifying information, output data corresponding to the obtained input data to the second image processing apparatus for outputting.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 25, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Naoki Fukasawa
  • Patent number: 10331389
    Abstract: A remote communication control system includes a session relay system and a session management unit. The session relay system relays a session between an image forming apparatus and an electronic device by associating a connection established with the image forming apparatus with a connection established with the electronic device. The electronic device is located outside a network to which the image forming apparatus belongs. The session management unit manages the session. When the electronic device requests a start of the session, the session management unit causes the image forming apparatus to install an application required to establish the session.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 25, 2019
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventors: Koki Nakajima, Takeshi Nakamura, Keisuke Fukushima
  • Patent number: 10331390
    Abstract: Example systems and related methods may relate to controlling a printing device remotely during real-time communication session. Namely, a system may include a first server and a second server. The first server may include an application configured to provide a user interface. The second server may be configured to communicate with the first server and a plurality of printer devices according to a data transport protocol. A request that includes a printer device identifier may be received by a controller. Based on the printer device identifier, a target printer device may be determined from the plurality of printer devices. A communication session may be established between the first server, the second server, and the target printer device. The communication session is configured according to the data transport protocol. The controller may be configured to control the target printer device based on the communication session.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 25, 2019
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Oleg Y. Zakharov
  • Patent number: 10331391
    Abstract: An image recording apparatus includes a print engine, a sensor, a controller, and a memory. The print engine is configured to record an image on a recording medium. The sensor is configured to detect whether the image recording apparatus is moved. The memory is configured to store particular information. The memory stores instructions, the instructions, when executed by the controller, causing the controller to perform: a first deletion process of, in response to determining that a first condition is satisfied, deleting the particular information stored in the memory, the first condition being that movement of the image recording apparatus is detected by the sensor.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: June 25, 2019
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Tasuku Sugimoto
  • Patent number: 10331392
    Abstract: Example systems and related methods may relate to monitoring performance of an image forming operation. Namely, a system includes an image forming apparatus configured to execute an operation in response to receiving instructions to execute the operation. The system further includes an external sensor circuit that includes one or more sensors and a processor. The one or more sensors are configured to detect a status of an operational parameter of the image forming apparatus indicative of the image forming apparatus executing the operation and receive an instruction to exclude at least a portion of data used to detect the status of the operational parameter. The system further includes a host computing device. The host computing device is configured to generate a plurality of timestamps indicative of when the image forming apparatus executed the operation and a time frame when the external sensor circuit excluded data.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 25, 2019
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventors: Edwin Philip Lockwood, Neil-Paul Payoyo Bermundo, Luis David Barriere, Jr.
  • Patent number: 10331393
    Abstract: A vehicle-mounted terminal and a method for obtaining a resolution of a screen of a handheld terminal are disclosed. The method includes establishing a connection between a handheld terminal having a second screen and a vehicle-mounted terminal having a first screen, mapping a display of the second screen onto the first screen, obtaining a first coordinate difference between two coordinate points on the second screen and a second coordinate difference between two mapped points on the first screen that correspond to the two coordinate points respectively, and obtaining a resolution of the second screen using the relationship that a ratio of the first coordinate difference to the second coordinate difference is equal to a ratio of a mapped resolution of the second screen mapped onto the first screen to the resolution of the second screen, wherein the mapped resolution of the second screen mapped onto the first screen is a first resolution and the resolution of the second screen is a second resolution.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 25, 2019
    Assignee: AUTOCHIPS INC.
    Inventor: Xiaozhou Huang
  • Patent number: 10331394
    Abstract: A technique for sharing screen content of a host machine with a client machine includes identifying multiple screen regions formed by image features within screen content of the host machine and enabling a user of the client machine to move selected screen regions to desired screen locations on the client machine, while leaving unselected screen regions in place. For example, when the user of the client machine selects and drags a particular screen region, the client machine creates a new window and displays the screen contents of the selected screen region in the new window, which the user may place and resize as desired.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 25, 2019
    Assignee: LogMeIn, Inc.
    Inventors: David Sarfi, Botond Szentannai, Istvan Hoffmann
  • Patent number: 10331395
    Abstract: A roulette wheel display arrangement and system is disclosed for displaying a winning result from the roulette wheel. The arrangement comprises a display screen which is arranged to extend around a periphery of the wheel, and a plurality of screen facets, each facet being arranged to extend adjacent a corresponding player wagering position. The arrangement further comprises a plurality of image projection units which are separately arranged to project the winning result onto a respective facet of the display screen, the screen facets being inclined toward the roulette wheel away from the respective player wagering position, such that a player can view the winning result from the wagering position on the respective screen facet.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: June 25, 2019
    Assignee: NOVOMATIC AG
    Inventors: Andrew Dinning, Ronald Watts
  • Patent number: 10331396
    Abstract: A filter for generating an audio output signal includes a plurality of audio output signal samples based on two or more input microphone signals. The audio output signal and the two or more input microphone signals are represented in a time-frequency domain, wherein each of the plurality of audio output signal samples is assigned to a time-frequency bin of a plurality of time-frequency bins. The filter includes a weights generator being adapted to receive, for each of the plurality of time-frequency bins, direction-of-arrival information and weighting information. Moreover, the filter includes an output signal generator for generating the audio output signal.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: June 25, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung e.V.
    Inventors: Emanuel Habets, Oliver Thiergart, Sebastian Braun, Maja Taseska