Abstract: Embodiments of the invention are directed to methods for handling cache prefetch requests. The method includes receiving a request to prefetch data from main memory to a cache. The method further includes based on a determination that the prefetch request is a speculative prefetch request, determining if the cache is being used for transactional memory. The method further includes based on a determination that the cache is not being used for transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, rejecting the prefetch request.

Abstract: In general, embodiments of the technology relate to method for resolving a library path in a distributed system. The method includes receiving a path resolution request, issuing a first request to a first node server to obtain a first library name index (LNI) associated with a first portion of the library path, obtaining the first LNI, and generating, based on the first LNI, a second request to a second node server of the plurality of node servers, where the second request is associated with a second portion of the library path. The method further includes after not receiving a second response to the second request: issuing a request message to a set of node servers, receiving, from one of the node servers, a third response to the request message, and resolving the entire library path using, at least in part, the third response.

Abstract: Processors configured by aspects of the present invention optimize reference cache maintenance in a serialization system by serializing a plurality of objects into a buffer and determining whether any of the objects are repeated within the buffered serialized plurality. The configured processors insert an object repetition data signal within the serialized plurality of objects that indicates to a receiver whether or not any objects are determined to be repeated within the buffered serialized plurality of objects, and send the serialized plurality of objects with the inserted object repetition data signal as a single chunk to a receiver, wherein the inserted object repetition data signal conveys reference cache management instructions to the receiver.

Abstract: A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a respective number of edges associated with each vertex of a plurality of vertices included in a graph data structure, and sort the graph data structure using the respective number of edges. The circuit may be further configured to determine a reuse value for a particular vertex of the plurality of vertices using a respective address associated with the particular vertex in the sorted graph, and store data and metadata associated with the particular vertex in a particular line of the plurality of lines in the cache memory.

Abstract: Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If an access request does not correspond to any valid page addresses in the prediction table, the access request may be sent to the first memory. If the access request corresponds to a valid page address in the prediction table, the access request may be sent to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory.

Abstract: The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being the same as the write address.

Abstract: Embodiments of the present disclosure relate to a method and device for flushing pages from a solid-state storage device. Specifically, the present disclosure discloses a method of flushing pages from a solid-state storage device comprising: determining a first number based on a period length of one flushing cycle and a period length required for building one flushing transaction, the first number indicating a maximum number of flushing transactions that can be built in the flushing cycle; and flushing pages from the solid-state storage device with an upper limit of the first number in the flushing cycle. The present disclosure also discloses a device for flushing pages from a solid-state storage device and a computer program product for implementing steps of a method of flushing pages from a solid-state storage device.

Abstract: Provided are a computer program product, system, and method for considering a frequency of access to groups of tracks and density of the groups to select groups of tracks to destage. One of a plurality of densities for one of a plurality of groups of tracks is incremented in response to determining at least one of that the group is not ready to destage and that one of the tracks in the group in the cache transitions to being ready to destage. A determination is made of a group frequency indicating a frequency at which tracks in the group are modified. At least one of the density and the group frequency is used for each of the groups to determine whether to destage the group. The tracks in the group in the cache are destaged to the storage in response to determining to destage the group.

Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the list of the second type of tracks.

Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.

Abstract: A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.

Abstract: A system, method, and apparatus for operating system integrated application isolation. A snapshot manager creates a snapshot table including one or more pointers to a file system storage. Then an application is installed on an operating system and mapped to a snapshot table. The snapshot manager receives a request by the application to access a memory block. The snapshot manager determines whether the application has permission to access the memory block. Responsive to a determination that the application has permission to access the memory block, the snapshot manager permits access to the memory block.

Abstract: Data and power are transmitted a master to a peripheral, with power communicated from a controller circuit board to the peripheral circuit board across data lines. Power is transmitted from the voltage regulator of the controller circuit board to an SPI or SSI master. Power over Synchronous Serial Interface (SSI) and Serial Peripheral Interface (SPI) uses Ethernet cable or custom 2 to 4-pair cable to move power high speed data between a microprocessor and a peripheral.

Abstract: A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. The first transceiver is coupled between the first pin and a node and includes a first current limiter. The second connector is configured to couple to a peripheral device and includes a second pin. The second transceiver is coupled between the node and the second pin and includes a second current limiter. The voltage processor processes the voltage of the node to generate an operation voltage. The controller receives the operation voltage to determine whether to turn on at least one of the first and second transceivers.

Abstract: A memory system includes memory devices sharing a data bus and a control bus and controlling the memory devices through the control bus, wherein the memory devices have different latencies each other, and a controller transceiving a data with the memory devices through the data bus, wherein the controller may transceive a data with the memory devices during a time corresponding to a data burst length for a moment being the each latencies of the memory devices after transmitting same control signals to the memory devices.

Abstract: An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.

Abstract: Embodiments of a buffer device, an electronic system, and a method for operating a buffer device are disclosed. In an embodiment, a buffer device includes buffer bus connections, a peripheral bus interface connectable to a peripheral bus, a buffer memory module, and a buffer memory controller connected between the buffer bus connections, the peripheral bus interface, and the buffer memory module. Each of the buffer bus connections is connectable to a respective peripheral device. The buffer memory module comprises memory segments corresponding to the peripheral devices. The buffer memory controller is configured to control data communications between the buffer bus connections, the peripheral bus interface, and the buffer memory module.

Abstract: A bus traffic control apparatus includes a sizing block, a traffic request controller and a bus master engine. The sizing block is configured to determine a data transmitting size of a bus master based on bus traffic information. The traffic request controller is configured to control transmission of data from the bus master based on the data, a destination of the data, the data transmitting size. The bus master engine is configured to transmit the data to the destination in the data transmitting size based on the data, the destination of the data, the data transmitting size and a request received from the traffic request controller.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including a duty cycle logic to set a duty cycle having a cycle time formed of an active time window in which at least some of the plurality of cores are to be active and an idle time window in which the plurality of cores are to be in a low power state. The duty cycle logic may adjust a duration of at least one of an active time window and an inactive time window based on interrupt information to accommodate an impending interrupt within the active time window. Other embodiments are described and claimed.

Abstract: Migrating interrupts from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, interrupt mapping information, where the hypervisor supports operation of a logical partition executing and the logical partition is configured to receive interrupts from the source I/O adapter; configuring, by the hypervisor, the destination I/O adapter with the interrupt mapping information collected by the hypervisor; placing, by the hypervisor, the destination I/O adapter and the source I/O in an error state; deconfiguring the source I/O adapter from the logical partition; and enabling the logical partition and destination I/O adapter to recover from the error state.

Abstract: A method of real-time data acquisition in a processing component using chained direct memory access (DMA) channels includes receiving a DMA event signal in a DMA controller of the processing component, and executing, responsive to the DMA event signal, DMAs to read at least one data sample from a peripheral device. A last DMA performs a write operation to acknowledge completion of the DMA event.

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Abstract: A vehicle safety electronic control system (8) including a first microcontroller (11), a second microcontroller (12), and an inter-processor communication path (13) for bi-directional transfer of data between the microcontrollers (11,12). The system has a first mode of inter-processor communication in which the first microcontroller (11) acts as a master and the second microcontroller (12) acts as a slave, and a second mode of inter-processor communication in which the second microcontroller (12) acts as a master and the first microcontroller (11) acts as a slave. A mode selector (18-20) is provided to select and switch between the first and second modes.

Abstract: The present invention provides universal conversion system, comprising: at least one universal port connected with a connector to a smart X-bar, and at least one type of sensing circuitry connected with a connector to the smart X-bar, wherein each universal port is configured to connect with a connector to a transducer, each type of sensing circuitry is configured to measure a different type of electrical information, and the smart X-bar is configured to connect each universal port with each type of sensing circuitry. The present invention further provides a method for utilizing information accumulated in a database of a network for improving the mode of action of a plurality of universal conversion systems connected to the network.

Abstract: A system includes at least two ports (22, 24, 26) connected to particular electronic products. The system is able to intelligently detect the master/slave status of the electronic device and establish connecting routes among the ports (22, 24, 26) and the system accordingly. Each of the connecting route transfers at least electric power and optionally data. The system alleviates users' concern whether the electronic product to be connected to the system acts as a master or a slave. As such, electronic products can be connected to any port (22, 24, 26) available in the system.

Abstract: A switching fabric includes a plurality of buses and a plurality of switching devices. A method for operating the switching fabric includes assigning the plurality of buses to be a plurality of peripheral buses and a plurality of computer buses according to a predetermined configuration, establishing electrical connections between the plurality of computer buses and the plurality of peripheral buses according to the predetermined configuration, and when a first computer is coupled to a first computer bus of the plurality of computer buses and performs a peripheral component interconnect express scan function, transmitting types and/or utilization information of a plurality of first peripheral devices corresponding to the first computer bus to the first computer according to the predetermined configuration to make the first computer reserve memory segments required by the plurality of first peripheral devices.

Abstract: A method, apparatus and system for changing to which remote device a local device is in communication via a communication medium, communicates with a matrix switch forming part of the system by interruption of the communication medium by the local device. Upon receipt of a unit of information via interruption of the communication medium, the matrix switch causes the local device to be in communication with another remote device other than the remote device that it was previously in communication. In one embodiment, the switching is to a next available remote device of a plurality of remote devices while in another embodiment, the matrix switch switches the local device to a switch configuration device for further communication therewith via the communication medium, thereby allowing the local device to select which other remote device it desires to be in communication.

Abstract: A circuit for detecting charger connection through a universal serial bus (UBS) connector is disclosed. The circuit includes a comparator having a first input coupled to a fixed voltage reference and a second input coupled to D+ pin of the USB connector, a voltage controlled current source (VCCS) coupled having a first terminal coupled to a supply and a second terminal coupled to the D+ pin and a resistor coupled between the first terminal and the second terminal of the VCCS. The VCCS is configured to bring voltage at the D+ pin within a preselected voltage range at the D+ pin when the voltage at the D+ pin varies beyond the preselected voltage range.

Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

Abstract: Provided are a memory package, an expansion memory module, and a multi-module memory system. A base memory module, to/from which an expansion memory module is capable of being attached/detached, includes a module board, a plurality of module terminals arranged on the module board to be connected to a slot, and a plurality of memory packages, each of which including a first surface to be attached to the module board and a second surface opposite to the first surface facing away from the module board, wherein each of the plurality of memory packages includes a plurality of package terminals exposed on the second surface of the memory package to be connected to the expansion memory module.

Abstract: There is provided an electronic device that includes a plurality of disk drive units, a housing, a connection member, and a damping member. The housing houses the plurality of disk drive units. The connection member keeps a non-contact state between the plurality of disk drive units and connects the plurality of disk drive units. The damping member is arranged between the housing and the connection member and elastically supports the connection member to the housing in three-axis directions orthogonal to each other.

Abstract: A synchronous transmission device includes a first communication port, a first bus instance and a second bus instance. The first communication port is connected to the first endpoint and the second endpoint. The first bus instance executes a first data transmission with the first endpoint according to a first node of a first schedule list. The first node corresponds to the first endpoint, and the first bus instance corresponds to the first communication port. When the first data transmission is executed, the first bus instance is further configured to determine whether the second bus instance is idle. When the second bus instance is idle, the first bus instance controls the second bus instance to execute a second data transmission with the second endpoint according to a second node of the first schedule list. The second node of the first schedule list corresponds to the second endpoint.

Abstract: Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from another electronic device. The other electronic device is configured to provide a protocol indicator that indicates a particular communication protocol with which the other electronic device is configured to communicate through an electrical connector of the electronic device. A method includes receiving a protocol indicator from another electronic device through an electrical connector. The protocol indicator indicates a communication protocol. The method also includes communicating with the other electronic device through the electrical connector using the indicated communication protocol.

Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

Abstract: According to an embodiment, a system, a method, and/or a computer program product is provided to allow a choice of allocating resources of a processor host bridge (PHB) at initial setup of a computer system to a group of peripheral component interconnect express (PCI-E) slots via a PCI-E switch, or alternatively to allocate resources of the PHB directly to a single PCI-E slot. The system may include a PHB, a first switch connected to the PHB, where the first switch is a simple circuit, a second switch connected to the first switch, where the second switch is a simple circuit, a PCI-E switch connected to the first switch and connected to the second switch, and a first PCI-E slot connected to the second switch.

Abstract: The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for serial interface link assist. Another embodiment relates to a method of dynamic reconfiguration of transceiver settings. Another embodiment relates to a method of tuning a bidirectional serial link. Other features, aspects and embodiments are also disclosed.

Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.

Abstract: A circuit for enabling the communication of data in a communication link associated with a data communication network is described. The circuit comprises a data generation circuit configured to receive a plurality of data streams and generate an output data stream; a control signal generator configured to generate synchronization headers; a serializer circuit configured to receive the output data stream from the data generation circuit and the synchronization headers from the control signal generator, wherein the serializer circuit generates, at an output, an output data signal having data of the output data stream and the synchronization headers; and a control circuit configured to control the data generation circuit and the control signal generator, wherein the control circuit enables a selection of the synchronization headers of the output data signal to enable channel alignment of the communication link.

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A method includes transmitting a first command on a serial bus while operating in a first mode of operation, exchanging first data with the first device in accordance with a second protocol associated with the second mode of operation, and exchanging second data with the first device in accordance with the second protocol after the first period of time. The first command may be transmitted in accordance with a first protocol to cause a first device to operate in a second mode of operation. The first device may be idle for a first period of time after the first data has been exchanged.

Abstract: A parallel processing apparatus including a plurality of compute nodes and a management node including a first processor configured to execute a process including collecting failure information regarding a plurality of ports of the plurality of compute nodes, and transmitting, to the plurality of compute nodes, failed port information including information on a failed port of the plurality of ports when an update in the failure information is detected in the collecting, wherein each of the plurality of compute nodes includes a second processor configured to execute a process including determining a retransmission route based on the failed port information when an inter-compute node communication in a low-level communication library has failed, and re-executing the inter-node communication by using the determined retransmission route.

Abstract: A method of managing remote direct memory access (RDMA) to a virtual computing instance includes suspending locally initiated RDMA operations of the virtual computing instance executing on a first host prior to a migration of the virtual computing instance to a second host. The first host includes a first hypervisor and the second host includes a second hypervisor. The method further includes requesting a peer to suspend remotely initiated RDMA operations that target the virtual computing instance through a first channel, establishing after the migration, a second channel between the peer and the second hypervisor that supports execution of the virtual computing instance on the second host, configuring a virtual object of the second hypervisor on the second host to use the second channel for the locally initiated RDMA operations, and requesting the peer to resume the remotely initiated RDMA operations using the second channel.

Abstract: Methods and apparatuses relating to consistency in an accelerator are described. In one embodiment, request address file (RAF) circuits are coupled to a spatial array by a first network, a memory is coupled to the RAF circuits by a second network, a RAF circuit is to not issue, into the second network, a request to the memory marked with a program order dependency on a previous request until receiving a first token generated by completion of the previous request to the memory by another RAF circuit, and a second RAF circuit is to not issue, into the second network, a second request to the memory marked with a program order dependency on a first request until receiving a second token sent by a first RAF circuit when a predetermined time period has lapsed since the first request was issued by the first RAF circuit into the second network.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: A conversion unit acquires collected information from a plurality of customer servers and performs a plurality of conversions different with respect to each of the customer server on the acquired collected information to generate conversion data. An identification unit performs identification on information contained in each set of collected information in a state where, with respect to the conversion data generated by the conversion unit, information before the conversion performed by the conversion unit is secreted.

Abstract: A system and method for generating a submittal register for various construction projects or other items is disclosed. Among other things, the system and method include inputting the construction project specifications in a file format, such as PDF, into a web application interface to convert the same to a text file, applying an algorithm to the text file, identifying all required submittals into a spreadsheet, running a quality control check of the generated spreadsheet, applying an analysis program to the spreadsheet, generating final submittal register by the program, and delivering the final submittal register.

Abstract: A method for managing files is provided. The method includes steps of: a file managing device (a) detecting a system call corresponding to a file access request from a program executed by the device; and (b) performing, by referring to the detected system call and parameters thereof, at least one of (i) execution of a procedure corresponding to the system call and (ii) supporting execution of the procedure corresponding to the system call, based on at least one file management policy; wherein the policy includes a local file naming policy to determine at least one of a file name and a file path among the parameters, by referring to an attribute thereof, which has at least part of a creation date and time, a modification date and time, a type, a name, an owner, a creator, an access privilege, origin information, version, situational information, a keyword and a subtitle.

Abstract: In a cloud storage system, fast recovery from a crash of a cloud gateway or the cloud storage is afforded without the necessity of traditional garbage collection. Data objects are each broken up into a plurality of chunk objects that are prefixed with a unique non-repeating forever increasing generation number that is incremented for each different data object. The chunk objects of a particular data object are identified and listed in a manifest file that is also associated with that generation number. Upon a crash of either the cloud gateway or the cloud storage, a query identifies the cloud and deletes all orphaned chunk objects prefixed by and all manifest files associated with the prevailing generation number at the time of the crash. The deleted chunk objects and manifest files are regenerated and restored to cloud storage to return to consistency.