Abstract: Embodiments of the present invention provide a method, system and computer program product for assertion management in a dynamically assembled programmatic environment. In an embodiment of the invention, a method for assertion management in a dynamically assembled programmatic environment can include dynamically assembling different execution units into a dynamically assembled computer program, applying an assertion to at least one of the different execution units through an introspection of the one of the different execution units, and generating an assertion result reporting a failure of the assertion responsive to the failure of the assertion.

Abstract: Systems and methods automatically detect violations of coding rules of a coding standard in computer programming code. The systems and methods may mark the locations in the code where the violations are found. The coding rules may be mapped to code verification checks that check for undesired runtime behavior in the code. The systems and methods may identify the code verification check mapped to a given violation detected in the code. The systems and methods may apply that check to the code. If the check proves that the undesired runtime behavior will not occur, the violation may be marked as justified. If the check proves that the undesired runtime behavior will occur, the violation may be marked as not justified.

Abstract: Mechanisms are provided for evaluating test cases for testing a software product based on a requirements change. The mechanisms analyze a test case corpus to identify a plurality of first relationships between elements of test cases in the test case corpus and generate a test case relationship model based on the identified plurality of first relationships. The mechanisms receive a proposed requirements change to change one or more requirements of the software product and then perform a search of the test case relationship model to identify test case relationships corresponding to the proposed requirements change. The mechanisms identify a subset of test cases affected by the proposed requirements change and generate an output specifying the identified subset of test cases.

Abstract: Disclosed is a system and method for real-time identification of anomalous behavior in a software program. The system is configured to generate a set of signatures files corresponding to a set of test cases. In one embodiment, each signature file is configured to maintain trace data generated after running the one or more test cases on the software program in a staging environment. Further, the system may capture real-time trace data from the software program, wherein the software program is deployed in a production environment. Further, the system may analyze the real-time trace data to identify a subset of signature files, from the set of signature files, applicable to the real-time trace data. Further, the system may compare the real-time trace data with the sub set of signature files to identify anomalous behavior in the software program.

Abstract: A test case data set that includes test step data sets is received. The test step data sets include a first test step data set that specifies a dependency data field. Test step objects to be used to execute test steps in a test case are generated based on the test step data sets. The test steps include a first test step to be executed using a first test step object generated based on the first test step data set. The first test step object is used to execute the first test step. The first test step as executed populates values in the dependency data field. The values in the dependency data field are accessed and used in a second test step in the test steps while the second test step is being executed using a second test step object in the test step objects.

Abstract: A computer-implemented method of detecting a likely software malfunction is provided. The method comprises collecting a plurality of software error data sets wherein each software error data set comprises a proposed code section containing an error and a corrected code section containing code changes that fixed the error in the proposed code section. The method further comprises training a computer-implemented algorithmic model using the collected software error data sets to devise a software code classifier for predicting a likely error in a code section, reviewing a section of code using the software code classifier, and identifying suspicious code in the reviewed section of code as containing a suspected error using the software code classifier.

Abstract: Systems, methods and computer program products for performing software regression testing are provided. A sitemap comprising a hierarchy of nodes is displayed on a display, each node representing a block of source code for a program. An indication of a user selection of a plurality of nodes in the hierarchy is received. Responsive to receiving the indication, a lowest node of the nodes that is located at a lowest level of the hierarchy is determined and identified as a user selected node. A list of test cases to test the source code represented by the user selected node is displayed. Responsive to receiving an indication of a selection of one of the test cases in the list of test cases displayed, a message having an indication to execute the one of the test cases in the list of test cases displayed is transmitted, to a server device via a network.

Abstract: A memory storage device, a memory control circuit unit and a data storage method for a rewritable non-volatile memory module are disclosed. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit in a first management unit and not storing the first data to the rewritable nonvolatile memory module if a data content of the first data is identical to a data content of second data stored in the first physical unit. The method also includes storing logical-to-physical bit map information to a second physical unit in the first management unit, wherein the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit. Identifiers or symbols of data content may be compared to determine if first and second data are identical.

Abstract: An arrangement is disclosed comprising a memory arrangement configured to store and retrieve data; an interface to allow data to be received and transmitted by the arrangement from a host and a processor configured to dynamically conduct automatic performance tuning for the memory arrangement.

Abstract: A method for reducing the cost of stack scanning in garbage collection (GC) includes, in the GC of the first-generation heap area, registering, in a nursery object reference list prepared for each thread, one or more addresses, within each stack, which each refer to a nursery object, and updating a scanning unnecessary area starting pointer such that the addresses listed in the nursery object reference list are included in the area from the bottom of the stack to the address pointed to by the scanning unnecessary area starting pointer. The method further includes, in the next GC of the first-generation heap area, for the area from the bottom of the stack to the address pointed to by the scanning unnecessary area starting pointer, performing the GC processing on the addresses included in the nursery object reference list.

Abstract: An object manager can manage memory in a mobile device to provide more effective use of resources and a better user experience. The object manager can store objects in different types of memory (e.g., ashmem or native memory) instead of the JAVA heap. When storing data objects in different types of memory, the system can use reference counting to manage objects. The object manager can also coordinate retrieval and display of images to further improve a user experience by progressively displaying images or asynchronously retrieving images from a network. The object manager can, for example, display a low resolution image first while a second higher resolution image is retrieved from a network and that image is progressively displayed. Also, the object manager can retrieve objects from local memory, a cache, or the network sequentially or in parallel.

Abstract: An apparatus includes: a processor core to execute an instruction; a first cache to retain data used by the processor core; and a second cache to be coupled to the first cache, wherein the second cache includes a data-retaining circuit to include storage areas to retain data, an information-retaining circuit to retain management information that includes first state information for indicating a state of data retained in the data-retaining circuit, a state-determining circuit to determine, based on the management information, whether requested data that is requested with a read request from the first cache is retained in the data-retaining circuit, and an eviction-processing circuit to, where the state-determining circuit determines the requested data not to be retained in the data-retaining circuit with no enough space in the storage areas to store the requested data, evict data from the storage areas without issuing an eviction request based on the read request.

Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.

Abstract: Examples disclosed herein relate to partial cache coherence. In some examples disclosed herein, a node connected to a memory fabric may include local cache connected to a local processor and a memory coherency proxy to. The memory coherency proxy may configure a portion of a fabric memory on the memory fabric as a proxy backing memory and expose the proxy backing memory to other nodes in the memory fabric as a fictitious local memory on the node, and may implement partial coherency for memory requests directed to the fictitious local memory. The fictitious local memory may have a memory address region different from a memory address region of a native local memory on the node.

Abstract: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.

Abstract: Systems and methods for data storage management technology that enables a guest module of a virtual machine to indicate an order in which a host module should write data from physical memory to a secondary storage. An example method may comprise: identifying, by a processing device executing a host module, a plurality of modifications to direct access excited (DAX) memory made by a plurality of direct access operations executed by a guest module of a virtual machine; determining, by the host module, an order of the plurality of modifications to DAX memory; receiving, by the host module, a synchronization request from the guest module; and responsive to the synchronization request, copying, by the host module, data from the DAX memory to a secondary storage in view of the order of the plurality of modifications.

Abstract: A filtered data cache eviction method preserves data that might otherwise be evicted by condensing the data into fewer containers. In particular, hot pages or pages that are associated with a particular application's working set of data are condensed into fewer containers rather than being evicted. The data that is copy forwarded includes blocks or pages of data tracked as having been recently and/or frequently accessed or otherwise associated with an active file.

Abstract: A cache memory, such as a translation lookaside buffer cache 16, includes a plurality of blocks of bit storage circuits 26 which can operate in either a first mode to store a plurality of shared-tagged data values having a shared tag, which his stored in a tag memory 24, or in a second mode to store a plurality of individual-tag data values and respective individual tags. The tag entries within the tag memory comprise the shared tag value for a given block operating in the first mode and a composite value for a given block operating in the second mode. The composite value includes a discriminator value indicative of the respective individual tags, such as a hash value or a Bloom filter value calculated in dependence upon the individual tags, using which potential matches with the individual tags may be identified from the discriminator value.

Abstract: Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device management system to maintain an access history of a plurality of storage blocks of solid state drives (SSDs) managed by the storage device management system; and automatically configure each of a plurality of storage blocks to operate in cache mode or tier mode, wherein a ratio of storage blocks operating in cache mode and storage blocks operating in tier mode is based on the access history.

Abstract: A memory system has a first memory to be accessed per first data size, a second memory to be accessed per second data size smaller than the first data size, the second memory being accessible at a higher speed than the first memory; and a third memory to store address conversion information that converts an address for accessing the second memory into an address for accessing the first memory. The first and third memories are non-volatile memories.

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.

Abstract: Embodiments include techniques for receiving a cacheline of data, hashing the cacheline into a plurality of chunks, wherein each chunk includes a pattern of bits, storing the plurality of chunks in a pattern table, wherein the plurality of chunks are indexed in the pattern table based on the pattern of bits of each chunk, and identifying a repeated pattern of bits of the plurality of chunks and selecting the repeated pattern of bits as candidate pattern. Techniques include comparing a threshold number of bits of the candidate pattern to the pattern of bits of the plurality of chunks in the pattern table; based on the comparison, inserting valid bits and a tag into the pattern table for the candidate pattern by replacing bits in the candidate pattern, and writing the candidate pattern, including the valid bits and the tag, into a location of the memory corresponding to the candidate pattern.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

Abstract: Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.

Abstract: The following description is directed to the use of encryption by a computing system. In one example, a method can include determining whether information associated with a logical address is stored unencrypted within an on-chip memory of an integrated circuit or whether the information associated with the logical address is stored encrypted within an off-chip memory external to the integrated circuit. When the information is not stored unencrypted within the on-chip memory and is stored encrypted within the off-chip memory: a page associated with the logical address can be retrieved from the off-chip memory containing the encrypted information; the retrieved page can be decrypted to generate unencrypted information; and the unencrypted information can be stored in a frame of the on-chip memory.

Abstract: A method and a system for transmitting data are disclosed. A method embodiment comprises: acquiring a most recent shared memory block index of a shared memory segment by a data receiver, the shared memory segment being used by a data transmitter and the data receiver to transmit data; deciding whether the most recent shared memory block index is consistent with a shared memory block index corresponding to data recently read by the data receiver; and determining, according to the decision, whether to read the data in the shared memory block corresponding to the most recent shared memory block index, where the determining includes reading the data in the shared memory block corresponding to the most recent shared memory block index when the decision indicates that the most recent shared memory block index is inconsistent with the shared memory block index corresponding to the data recently read by the data receiver.

Abstract: An input/output response relation data storage 5 stores input/output response relations which are inputted by the user and in each of which an I/O station for input and an I/O station for output are defined. For input/output response relations in each of which the I/O station for input differs from the I/O station for output and each of which needs communications between the I/O stations, an interchange searcher 9 searches for an interchange candidate with which to make the I/O station for input and the I/O station for output be the same as a result of interchanging either of the I/O station for input and the I/O station for output with another I/O station, an interchanger 10 performs an interchange, and a display 3 displays a result of the interchange.

Abstract: An apparatus includes a processor having an array of processor interconnects arranged to connect the processor to conductive paths, a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects, an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate, and at least one peripheral circuit connected to the at least one conductive trace.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage platform includes data storage assemblies each comprising one or more storage drives that service data storage operations over associated storage interfaces. A control processor is coupled to ones of the data storage assemblies over at least two types of sideband communication interfaces different than the storage interfaces of the storage drives. During an initialization process for the one or more storage drives, the control processor configured to transfer initialization data to each of the data storage assemblies over a first type of sideband communication interface and transfer further initialization data to at least one of the data storage assemblies over a second type of sideband communication interface when the at least one of the data storage assemblies does not respond to the initialization data over the first type of sideband communication interface.

Abstract: A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.

Abstract: Provided is a computer system, comprising a plurality of devices and a plurality of management computers. The devices further comprise one or more objects. The plurality of management computers provides services with the one or more objects being subjects to be managed. An information provision period is set for each of the objects of each of the services. On the basis of an information collection policy relating to collecting information about the objects and the information provision period which is set for each of the objects of each of the services which is running, a primary management computer determines the management computer which handles the collection of the information of each of the objects, and notifies each of the management computer that has been so determined of the objects which said management computer will handle the management for.

Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a device operating as a bus master may include transmitting a first pulse on a first wire of a multi-wire interface, transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, and initiating a low-latency mode of communication immediately after termination of the first pulse. The second pulse may be shorter in duration than the first pulse.

Abstract: A data structure is accessed that defines configuration parameters of one or more integrated blocks in an integrated circuit device. One or more of the integrated blocks is configured based on corresponding configuration parameters defined in the data structure. The configuration parameters are set prior to runtime and are to be persistently stored in the data structure.

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

Abstract: A data storage device includes a case and a connector housed within the case. The connector includes a first connection interface having a plurality of connection fingers and a second connection interface having a plurality of springs. The case is positionable within a data storage device port such that the data storage device is completely disposed within the data storage device port when used.

Abstract: The present disclosure is directed to an apparatus for forming an interface for interfacing a remote access appliance (“RAC”) to a target device (“TD”) and enabling video and serial communications between the RAC and TD. The apparatus makes use of a housing having a first port, a second port and a third port. A circuit board may be housed within the housing for enabling serial and video communications between the TD and the RAC. The first port enables an interface to the apparatus via a communications cable in communication with the RAC. The second port enables a serial connection between the apparatus and the TD via an independent serial communications cable. The third port forms a video connector connectable directly to a video port of the target device for enabling video communications between the TD and the apparatus.

Abstract: Even in the case where a ring bus interface that is connected to an internal ring bus of an LSI is provided as an interface of the LSI in order to add a new image processing function, the position of a function extension module on the ring bus is fixed. An information processing apparatus including: a first controller unit having a plurality of modules and a ring bus that connects the plurality of modules in the form of a ring; and a second controller unit having a plurality of modules and a ring bus that connects the plurality of modules in the form of a ring, and the first controller unit having an interface that transmits data to the ring bus within the second controller unit and a switch capable of switching an output destination of data output from at least one of the plurality of modules of the first controller unit to the interface.

Abstract: A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.

Abstract: A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.

Abstract: A hot plug method, a host controller, a host, and a PCIe bridge device. The method includes: generating, by a host controller, a first notification packet, where the first notification packet includes hot plug interruption information, and the hot plug interruption information indicates that a first PCIe device is to be hot-plugged; sending, by the host controller, the first notification packet to a host, so that the host performs, according to the first notification packet, a hot plug operation corresponding to the PCIe device; and receiving, by the host controller, a second notification packet sent by the host, and sending the second notification packet to a user equipment controller, to facilitate the user equipment controller to instruct a user to insert or remove the PCIe device, where the second notification packet is for indicating that the hot plug operation corresponding to the PCIe device is completed.

Abstract: An example computing device includes a module interface to communicate with a peripheral device. The computing device also includes a hot swapping prediction circuit to detect a physical movement of the computing device and to generate a hot swapping prediction signal based on the detected physical movement. The computing device further includes a processor coupled to the hot swapping circuit. The processor is to, in response to detecting the hot swapping prediction signal from the hot swapping circuit, change a parameter of a peripheral device detection operation to be executed by an operating system of the computing device.

Abstract: An information processing apparatus including processing units and a connection control unit that controls the connections between the processing units, in which the connection control unit is provided with a table creation unit which, with respect to a first logical channel established with a processing unit, creates table information showing a correspondence between logical channels without designating a logical channel that corresponds to the first logical channel when there is no second logical channel established with another processing unit that corresponds to the first logical channel, a table storage unit that stores the table information created by the table creation unit, and a table update unit that updates the table information for the second logical channel that is stored in the table storage unit so as to configure the first logical channel as a logical channel that corresponds to the second logical channel when there is a second logical channel.

Abstract: Embodiments for a memory access broker system with application-controlled early write acknowledgment support. A memory access broker may be selectively enabled to facilitate early write acknowledgement (EWACK) operations and notification of failed EWACK write requests to one or more issuing applications such that the failed EWACK write requests are logged by the memory access broker for inspection by the one or more issuing applications.

Abstract: Examples of a competing device for universal serial bus data routing are disclosed. In one example implementation according to aspects of the present disclosure, a computing device may include one or more processors, a memory, and a data store. The computing device may also include a first universal serial bus (USB) connection port to communicatively couple an attached computing device to the host computing device, and a second USB connection port to communicatively couple a peripheral device to the host computing device. The computing device may further include a USB data routing module stored in the memory and executing on at least one of the one or more processors to route data between the attached computing device and the peripheral device via the host computing device.

Abstract: A data transmission system is provided. The data transmission system includes a plurality of data transmitters that respectively constitute a plurality of transmission lanes. Each of the plurality of data transmitters includes a serializer and an output signal storage circuit. The serializer coverts parallel input data into serial output data and outputs the serial output data. The output signal storage circuit stores the serial output data output from the serializer.

Abstract: In an electronic device and a method for operating the electronic device according to various embodiments, the electronic device may comprise a housing, a USB Type-C connector configured to be connected to the housing or exposed through the housing and to include at least one configuration channel (CC) pin, a circuit configured to be disposed in the housing and connected electrically to the connector, and a processor configured to be disposed in the housing and connected electrically to the circuit. The circuit may be configured to transmit and receive a packet through the CC pin. The packet may sequentially comprise a message header, a first vendor defined message (VDM) header, and a second VDM header including a product identifier and a data type. Further, various other embodiments can be implemented according to the present disclosure.