Abstract: Nanowire-based integrated circuit devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a heterostructure over a substrate. A gate structure is formed traversing the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and defines a channel region between the source region and the drain region. A source/drain nanowire release process is performed on the heterostructure to release a nanowire in the source region and the drain region. Nanowire spacers are then formed in the source region and the drain region. The nanowire is disposed between the nanowire spacers. During a gate replacement process, a channel nanowire release process is performed on the heterostructure to release the nanowire in the channel region. Epitaxial source/drain features are formed over the nanowire and the nanowire spacers in the source region and the drain region before the gate replacement process.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

Abstract: A fabrication method of a thin film transistor, a fabrication method of an array substrate, a display panel, and a display device are provided. The fabrication method of the thin film transistor comprises: forming a gate electrode, a gate insulating layer and an oxide active layer; forming an inverted trapezoidal dissolution layer whose cross section is inverted trapezoidal on the oxide active layer, the inverted trapezoidal dissolution layer being soluble in an organic solvent; forming a source/drain layer on the oxide active layer, the gate insulating layer and the inverted trapezoidal dissolution layer, a thickness of the inverted trapezoidal dissolution layer being greater than a thickness of the source/drain layer; and dissolving and removing the inverted trapezoidal dissolution layer with the organic solvent and removing the source/drain layer on the inverted trapezoidal dissolution layer, to form a source electrode and a drain electrode.

Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

Abstract: A semiconductor device includes a channel region, a source region having a first type semiconductor and a drain region having a second type semiconductor on opposing sides of the channel region. A gate stack is disposed over the channel region. A low-k spacer is disposed over the source region and abreast the gate stack. The source region includes a first type dopant, and the drain region includes a second type dopant. A pocket is disposed between the channel region and the source region. The pocket has the first type semiconductor and a higher first type dopant concentration than a first type dopant concentration of the source region.

Abstract: An electric assembly includes a bipolar switching device and a transistor circuit. The transistor circuit is electrically connected in parallel with the bipolar switching device and includes a normally-on wide bandgap transistor.

Abstract: A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement having a first configuration region of emitter-side insulated gate bipolar transistor structures, a second configuration region of emitter-side insulated gate bipolar transistor structures, a collector layer and a drift layer. The drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region. The collector layer includes at least a first doping region laterally adjacent to a second doping region, the doping regions having different charge carrier life times, different conductivity types or different doping concentrations. The first configuration region is located with at least a partial lateral overlap to the first doping region, and the second configuration region is located with at least a partial lateral overlap to the second doping region.

Abstract: Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm?3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm?3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

Abstract: The present invention provides an epitaxial structure of N-face AlGaN/GaN, its active device, and the method for fabricating the same. The structure comprises a substrate, a C-doped buffer layer on the substrate, a C-doped i-GaN layer on the C-doped buffer layer, a i-AlyGaN buffer layer on the C-doped i-GaN layer, an i-GaN channel layer on the C-doped i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of N-face AlGaN/GaN below the p-GaN inverted trapezoidal gate structure will be depleted. Then the 2DEG is located at the junction between the i-GaN channel layer and the i-AlyGaN layer, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs).

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.

Abstract: A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.

Abstract: A MOSFET includes a semiconductor base substrate where a super junction structure is formed of an n-type column region and a p-type column region. A total amount of a dopant in the n-type column region is set to a value greater than a total amount of a dopant in the p-type column region. The MOSFET is configured to be operated during a period from a point of time when a drain current starts to decrease to a point of time when the drain current becomes 0 for the first time in response to turning off of the MOSFET such that a first period during which the drain current is decreased, a second period during which the drain current is increased or the drain current becomes constant, and a third period during which the drain current is decreased again occur in this order.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

Abstract: A drift layer is made of a wide bandgap semiconductor. First well regions are formed on the drift layer. A source region is formed on each of the first well regions. A gate insulating film is formed on the first well regions. A first electrode is in contact with the source regions, and has diode characteristics allowing unipolar conduction to the drift layer between the first well regions. A second well region is formed on the drift layer. A second electrode is in contact with the second well region, and separated from a gate electrode and the first electrode.

Abstract: An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.

Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a first insulating film around the fin-shaped semiconductor layer. A first contact is on the fin-shaped semiconductor layer, where the first contact is metal contact. A first gate insulating film is around the first contact and a fourth contact on the first contact, and a second gate insulating film is around the fourth contact.

Abstract: Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same.

Abstract: A ferroelectric memory device includes a substrate, a ferroelectric layer, a variable resistive memory layer and a gate electrode which are sequentially stacked on a surface of the substrate. The ferroelectric layer has any one of a plurality of different remanent polarization values depending on a resistive state of the variable resistive memory layer.

Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication process includes providing a semiconductor substrate having a first region and a second region and having a plurality of first fins in the first region and a plurality of second fins in the second region; performing a first oxidation process on the first fins to form a first oxide layer on surfaces of the first fins and to cause corners between top surfaces and side surface of the first fins to form first rounded corners; and performing a second oxidation process on the second fins to form a second oxide layer on surfaces of the second fins and to cause corners between top surfaces and side surface of the second fins to form second rounded corners. A radius of curvature of the first rounded corner is different from a radius of curvature of the second rounded corner.

Abstract: A method of manufacturing a semiconductor device includes forming a nanowire foundation layer on a semiconductor substrate. A first nanowire is formed on the nanowire foundation layer. A gate structure is formed over the nanowire foundation layer and wrapping the first nanowire. A second nanowire is formed on and in contact with the first nanowire in a bottom-up manner. A source/drain region is formed on the gate structure and wrapping the second nanowire.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a first oxide over the first insulator; a second oxide in contact with at least a portion of the top surface of the first oxide; a second insulator over the second oxide; a first conductor over the second insulator; a second conductor over the first conductor; a third insulator over the second conductor; a fourth insulator in contact with side surfaces of the second insulator, the first conductor, the second conductor, and the third insulator; and a fifth insulator in contact with the top surface of the second oxide and a side surface of the fourth insulator. The top surface of the fourth insulator is substantially aligned with the top surface of the third insulator.

Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.

Abstract: A method for preparing a layered metal oxide field effect material includes depositing a first metal oxide, a core-layer metal, and a second metal oxide sequentially on the substrate by vacuum vapor deposition, the first metal oxide and the core-layer metal undergoing a redox reaction to form a first surface layer and a core-layer precursor on the substrate, and the core-layer precursor and the second metal oxide undergoing a redox reaction to form a core layer and a second surface layer; and the band gap of the metal oxide in the core layer is ?3 eV, the band gaps of the metal oxide in the first surface layer and the second surface layer are independently ?3 eV, and the difference between the band gap of the metal oxide in the core layer and the band gap of the metal oxide in the first surface layer is ?1 eV. The present preparation method has advantages of simple operation, a low production cost, a good film forming property, and the high carrier mobility of the product.

Abstract: A thin film transistor having a high operation speed with a field effect mobility greater than 20 cm2/Vs and a method for manufacturing the same, and a semiconductor device having the same are provided. A thin film transistor in which a gate electrode, a gate insulating film and an oxide semiconductor film are laminated on a substrate, a source region and a drain region are respectively formed in outer portions of the oxide semiconductor film in the width direction, and a channel region is formed in a region between the source region and the drain region; and a source electrode is connected to the source region, while a drain electrode is connected to the drain region. The gate insulating film contains fluorine; and the ratio of the width W of the channel region to the length L thereof, namely W/L is less than 8.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis.

Abstract: An optical sensor package includes a substrate, a wall disposed upon the substrate, and a cover layer disposed on the wall. The substrate, the wall, and the cover layer at least partially define a cavity. The optical sensor package also includes a sensor disposed upon the substrate within the cavity. A cloaking layer is disposed upon to the cover layer. The cloaking layer is transmissive to at least a portion of a light spectrum and is configured to at least partially conceal the sensor. In some examples, the optical sensor package also includes a light source disposed upon the substrate within another cavity at least partially defined by the wall and the cover layer.

Abstract: A process for producing conductive pastes for forming solar cell electrodes, including a step of measuring binding energies of oxygen in a glass frit by X-ray photoelectron spectroscopy, a step of selecting a glass frit providing an X-ray photoelectron spectrum representing binding energies of oxygen in which the signal intensity of a peak with a peak top at a range from 529 eV to less than 531 eV has a proportion of 40% or more relative to the total of signal intensities from 526 eV to 536 eV, and a step of mixing together a conductive powder, the glass frit and an organic vehicle.

Abstract: Provided is a photoelectric conversion element comprising ITiO as a transparent electrode that is formed using an inline-type sputtering method, and utilizing the high transmittance up to the near-infrared ray region and excellent conductivity of ITiO. Using the inline-type sputtering method, a first transparent conductive oxide film 8 comprising indium oxide or tin-containing indium oxide that includes indium oxide as a main component and tin at an atomic ratio Sn/(In+Sn) of 19 atomic % or less is formed on a photoelectric conversion layer 7 side, and a second transparent conductive oxide film 9 comprising a titanium-containing indium oxide that includes indium oxide as a main component, and titanium at an atomic ratio Ti/(In+Ti) of 0.5 atomic % to 3.5 atomic % is laminated on an opposite side of the first transparent conductive film 8 from the photoelectric conversion layer 7.

Abstract: An optical device includes an active region and packaging glass located on top of the active region. A top surface of the packaging glass includes hierarchical nanostructures comprised of honeycombed nanowalls (HNWs) and nanorod (NR) structures extending from the HNWs.

Abstract: A photodetector has a two dimensional conductive channel and a quantum dot layer configured to generate charge on exposure to incident electromagnetic radiation. The surface texture of the quantum dot layer has texturing to provide surface roughness which increases the amount of electromagnetic radiation absorbed in the quantum dot layer in comparison to a photodetector having a flat (non-textured) incident electromagnetic radiation surface.

Abstract: A photodetector cell may include a substrate, and a first contact carried by the substrate and having a first work function value. The photodetector cell may include a second contact carried by the substrate and having a second work function value different from the first work function value, and a semiconductor wire carried by the substrate and having a third work function value between the first and second work function values. The semiconductor wire may be coupled between the first and second contacts and comprising a photodiode junction.

Abstract: The object of the present invention is to provide a white polyester film for a solar cell that is excellent in transfer-mark concealment properties (properties that transferred irregularities are hard to be seen) while having high whiteness, and exhibiting good light resistance and hydrolysis resistance, a sealing sheet for a back surface of a solar cell and a solar cell module using the same.

Abstract: A solar cell module is discussed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and a plurality of first electrodes and a plurality of second electrodes, which are formed on a back surface of the semiconductor substrate and are separated from each other, the plurality of solar cells disposed in a first direction; a plurality of first conductive lines connected to the plurality of first electrodes included in a first solar cell of the plurality of solar cells, and the plurality of first conductive lines extended in the first direction; a plurality of second conductive lines connected to the plurality of second electrodes included in a second solar cell of the plurality of solar cells which is adjacent to the first solar cell, and the plurality of second conductive lines extended in the first direction.

Abstract: A bipolar solar cell includes a backside junction formed by a silicon substrate and a first doped layer of a first dopant type on the backside of the solar cell. A second doped layer of a second dopant type makes an electrical connection to the substrate from the front side of the solar cell. A first metal contact of a first electrical polarity electrically connects to the first doped layer on the backside of the solar cell, and a second metal contact of a second electrical polarity electrically connects to the second doped layer on the front side of the solar cell. An external electrical circuit may be electrically connected to the first and second metal contacts to be powered by the solar cell.

Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.

Abstract: A photovoltaic device includes a liquid-repelling layer between the edges of a first amorphous semiconductor layer and the edges of a second amorphous semiconductor layer. No such a liquid-repelling layer is provided between the first amorphous semiconductor layer and the second amorphous semiconductor layer, except between the edges of the first amorphous semiconductor layer and the edges of the second amorphous semiconductor layer. The semiconductor layer in the photovoltaic device is therefore precisely patterned.

Abstract: A method of fabricating a visibly transparent, ultraviolet (UV) photodetector is provided. The method includes laying a first electrode onto a substrate surface, the first electrode being formed of a carbon-based, single-layer material. A block is patterned over an end of the first electrode and portions of the substrate surface. The block is formed of a visibly transparent material that is able to be deposited into the block at 75° C.-125° C. In addition, the method includes masking a section of the block and exposed sections of the first electrode. A second electrode is laid onto an unmasked section of the block with an end of the second electrode laid onto the substrate surface. The second electrode is formed of the carbon-based, single-layer material.

Abstract: An optical coupling device includes a first lead frame, a second lead frame, a first mounting member, a second mounting member, the members respectively provided on the first lead frame and, the second lead frame a light emitter provided on the first mounting member, a light receiver provided on the second mounting member, a first wire and a second wire electrically connecting the light emitter to the first lead frame, and the light receiver to the second lead frame, and an outer resin enclosure enclosing a part of the first lead frame and the second lead frame, the light emitter, and the light receiver, wherein at least the light emitter and the light receiver in the outer resin enclosure are covered with a silicone resin cured material.

Abstract: A light-emitting device includes an active structure, wherein the active structure includes a well layer and a barrier layer. A first semiconductor layer of first conductivity type and a second semiconductor layer of second conductivity type sandwich the active structure. A first intermediate layer is between the first semiconductor layer and the active structure, wherein the first semiconductor layer has a first band gap, the second semiconductor layer has a second band gap, the well layer has a third band gap, and the first intermediate layer has a fourth band gap, wherein the first band gap and the second band gap are both larger than the fourth band gap, and the fourth band gap is larger than the third band gap. A first window layer is on the first semiconductor layer, wherein the first intermediate layer includes Alz1Ga1?z1As, the first window layer includes Alz2Ga1?z2As, and z1>z2.

Abstract: A method for producing an optoelectronic semiconductor chip is disclosed. A substrate is provided and a first layer is grown. An etching process is carrying out to initiate V-defects. A second layer is grown and a quantum film structure is grown. An optoelectronic semiconductor chip is also disclosed. The method can be used to produce the optoelectronic semiconductor chip.

Abstract: There are provided a Group III nitride semiconductor light-emitting device having complicated irregularities on the light extraction surface. The light-emitting device comprises a substrate, a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer. The light-emitting device has protrusions extending upward from the surface of the n-type semiconductor layer on the n-type semiconductor layer. Each protrusion has a wall portion disposed so as to intersect with the surface of the n-type semiconductor layer. The wall portion has a first surface facing the n-type semiconductor layer. An angle between the first surface and the n-type semiconductor layer is 10° to 85°.