Patents Issued in January 9, 2020
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Publication number: 20200012587Abstract: A method, computer program product, and computing system device for monitoring a plurality of individual actions executed on at least a portion of a software application. It may be determined whether the plurality of individual actions executed on the at least a portion of the software application complete at least one test case of a plurality of test cases. The at least one test case may be marked as completed based upon, at least in part, determining that the plurality of individual actions executed on the at least a portion of the software application complete the at least one test case of the plurality of test cases.Type: ApplicationFiled: July 6, 2018Publication date: January 9, 2020Inventors: John Girata, JR., Bryan R. Florkiewicz, Martin Presler-Marshall
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Publication number: 20200012588Abstract: Systems, methods, and computer-readable media are disclosed for generating a test case based on valid function codes that have not been selected for test case generation bypassing. A test program is provided that allows a user to specify, for each instruction, one or more function codes that the user does not want to use to generate a test case (e.g., that should be bypassed). A test stream generator is provided that has knowledge of valid and invalid function codes for any given supported instruction. A test case generator is provided that compares the function codes selected for bypassing to the valid function codes to identify a valid non-bypassed function code, which is used to generate a test case. Systems, methods, and computer-readable media are also disclosed for generating an exception test case using only one or more invalid function codes that have not been selected for bypassing.Type: ApplicationFiled: July 9, 2018Publication date: January 9, 2020Inventor: Louis P. GOMES
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Publication number: 20200012589Abstract: Aspects of the disclosure are directed to providing access to the contents of a computing platform definition. A computing platform definition includes entries indicating devices and executables to deploy to a computing platform. An orchestration engine is communicatively connected to a computing platform that implements the computing platform definition. An interface includes callable units that provide access to the computing platform definition which may be invoked by the orchestration engine during execution of a stage of an orchestration pipeline performed with respect to the computing platform. The interface receives from the orchestration engine a request indicating one of the callable units. In response to the request, the interface retrieves the portion of the computing platform definition that is associated with the callable unit indicated and provides that portion of the computing platform definition to the orchestration engine for use during execution of the stage of the orchestration pipeline.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: Suresh G. Nair, Hemanth G. Jayakumar, Sundar Krishnamoorthy, Georges M. Nkamicaniye
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Publication number: 20200012590Abstract: Development-time awareness of production environment dependency injection configuration in a software development or test environment. In a software development or test environment, metadata is retrieved relating to configuration data of injection sources and target injection sites in applications of a configured target production server or a representation of a configured target production server. A configuration data structure is formed that cross-references target injection sites and injectable sources determined from the configuration data, the configuration data structure being associated with the production server and available to the software development or test environment. The configuration data structure is referenced to carry out dependency injection related features.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: Fenghui Jiang, Ashley Robertson, Gordon Hutchison, Benjamin A. Confino, Thomas A. Evans
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Publication number: 20200012591Abstract: Methods, systems, and computer program products are provided to identify a set of functions within a first service module that calls a second service module. Both the first service module and the second service module are associated with an application that is structure with a plurality of interworking service modules. The first service module is executed to send requests to the second service module when the set of functions is called. The responses to the requests are captured, and stored in a snapshot data structure. A modified first service module is created, in which the set of functions are modified to return a response from the snapshot data structure in place of the second service module. A unit test is performed on the modified first service module.Type: ApplicationFiled: July 3, 2018Publication date: January 9, 2020Applicant: Red Hat Israel, Ltd.Inventors: Boaz Shuster, Oded Ramraz
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Publication number: 20200012592Abstract: A system and methods to emulate an application executing in real time in a mobile device. The mobile device is emulated in real time using a model running on a processor extrinsic to the mobile device. The model is based on characteristics indicative of performance of the mobile device. The application is executed in real time within the model and the application executing in the model is monitored to determine resource utilization information by the application for the mobile device. The resource utilization information for the mobile device is displayed.Type: ApplicationFiled: July 14, 2019Publication date: January 9, 2020Applicant: WAPP TECH CORP.Inventor: DONAVAN PAUL POULIN
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Publication number: 20200012593Abstract: Discussed herein are embodiments of methods and systems which allow engineers or administrators to create modular plugins which represent the logic for various fault detection tests that can be performed on data pipelines and shared among different software deployments. In some cases, the modular plugins each define a particular test to be executed against data received from the pipeline in addition to one or more configuration points. The configuration points represent configurable arguments, such as variables and/or functions, referenced by the instructions which implement the tests and that can be set according to the specific operation environment of the monitored pipeline.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: Peter Maag, Jacob Albertson, Jared Newman, Matthew Lynch, Maciej Albin, Viktor Nordling
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Publication number: 20200012594Abstract: According to one embodiment, a shared FIFO device includes a write pointer control circuit, a read pointer control circuit, a write pointer selection circuit, a read pointer selection circuit, a selection circuit, and a memory array. The shared FIFO device performs FIFO access through n transfer routes (where n is an integer of 2 or greater).Type: ApplicationFiled: December 20, 2018Publication date: January 9, 2020Inventors: Wataru Furuichi, Makoto Kanda, Shigeru Itoh, Hiroshi Nishikawa, Akihiro Kobayashi, Kiyoshige Taga
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Publication number: 20200012595Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.Type: ApplicationFiled: July 9, 2018Publication date: January 9, 2020Applicant: Western Digital Technologies, Inc.Inventors: KALPIT BORDIA, RAGHAVENDRA GOPALAKRISHNAN, SACHIN KRISHNA KUDVA, ASHIM RANJAN SAIKIA, BHANUSHANKAR DONI GURUDATH, RAMANATHAN MUTHIAH, PRADEEP SREEDHAR, PRASHANTH REDDY ENUKONDA, RAMKUMAR RAMAMURTHY
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Publication number: 20200012596Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Applicant: Macronix International Co., Ltd.Inventor: Ting-Yu Liu
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Publication number: 20200012597Abstract: A memory system including: a memory device having an open block and a closed memory block; a page counting unit counting the number of program pages in the open block whenever a data is programmed in the open block, and counting the number of valid pages of the closed memory block; a valid page decrease amount counting unit calculating a total sum of valid pages decreased in the closed memory block before and after a map update operation; and a garbage collecting unit performing a garbage collection operation onto a victim block when the number of free blocks included in the memory device is less than a first threshold value and greater than a second threshold value, and a ratio of the number of the program pages in the open block to the total sum of the valid pages decreased is greater than or equal to a fourth threshold value.Type: ApplicationFiled: December 20, 2018Publication date: January 9, 2020Inventors: Hyeong-Ju NA, Jong-Min LEE
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Publication number: 20200012598Abstract: A garbage collection technology for a storage medium that includes a plurality of blocks, where each storage unit has a collection parameter related to data in one of the blocks, and where each block includes a plurality of pages. A group of blocks is selected from the plurality of blocks based on the collection parameter. A difference between values of collection parameters of any two blocks in the group of blocks is not greater than a preset value. Data in a first valid page and a second valid page in the group of blocks is replicated to a same destination block, to facilitate garbage collection.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Inventors: Rui Feng, Shengqian Jia, Dingguo Yang
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Publication number: 20200012599Abstract: The invention introduces an apparatus for controlling data access that includes a memory, an access interface and a processing unit. The processing unit is arranged to operably receive logical-to-physical (L2P) mapping information corresponding to a programming operation through the access interface and store the L2P mapping information in the memory; searching the L2P mapping information to obtain a first logical address associated with user data stored in space of each physical address and a second logical address associated with user data stored in space of each next physical address; generating content of a plurality of entries of a link-based L2P mapping sub-table in the order of logical addresses, wherein each entry of the link-based L2P mapping sub-table stores information about a physical address and a second logical address associated with a corresponding first logical address; and store the link-based L2P mapping sub-table.Type: ApplicationFiled: January 31, 2019Publication date: January 9, 2020Applicant: SILICON MOTION, INC.Inventor: Shen-Ting CHIU
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Publication number: 20200012600Abstract: Some embodiments are directed to a computing device comprising a volatile memory comprising multiple rows of memory cells, each row of the multiple rows of memory cells having a neighboring row, and a memory mapper configured to map a first plurality of the multiple rows to a safe memory region, and a second plurality of the multiple rows to an unsafe memory region, wherein a row of the first plurality does not have a neighboring row in the first plurality.Type: ApplicationFiled: August 9, 2018Publication date: January 9, 2020Inventors: Radesh Krishnan KONOTH, Andrei TATAR, Marco OLIVERIO, Dennis ANDRIESSE, Hendrik Jaap BOS, Cristiano GIUFFRIDA, Kaveh RAZAVI
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Publication number: 20200012601Abstract: A memory system includes a memory device including a main memory and a cache memory that includes a plurality of cache lines for caching data stored in the main memory, wherein each of the cache lines includes cache data, a valid bit indicating whether or not the corresponding cache data is valid, and a loading bit indicating whether or not read data of the main memory is being loaded; and a memory controller suitable for scheduling an operation of the memory device with reference to the valid bits and the loading bits.Type: ApplicationFiled: December 26, 2018Publication date: January 9, 2020Inventors: Seung-Gyu JEONG, Su-Hae WOO, Chang-Soo HA
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Publication number: 20200012602Abstract: A cache allocation method and an apparatus are applied to software as a service (SaaS) that serves at least two tenants. The at least two tenants include a target tenant, and a cache partition of the target tenant is a target cache partition. The method includes: obtaining a first cache size and a monitoring record of the target tenant, where the monitoring record includes a correspondence between an adjustment size and a cache benefit change, and the first cache size is a current cache size of the target cache partition; and analyzing the monitoring record, and adjusting the first cache size to a second cache size when determining that adjustment of the first cache size to the second cache size meets a cache benefit target. According to the method, a higher cache benefit can be obtained, and a cache sharing utilization rate is correspondingly increased.Type: ApplicationFiled: September 10, 2019Publication date: January 9, 2020Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Qingwei ZHAO, Chong GU
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Publication number: 20200012603Abstract: A memory system may include: a nonvolatile memory device; a write buffer; and a controller suitable for: checking whether first write data have been committed at a point of time that a flush operation is performed on the write buffer, separating the flush operation into first and second flush operations which do not overlap each other but are consecutive to each other, according to the check result, and performing the first and second flush operations, when the first write data grouped into a transaction and second write data, which are not grouped into a transaction, are mixed and stored in the write buffer according to the sequence of the write data, among the write data stored in the write buffer, the controller may select and may store the first write data which are committed, in a first storage region of the nonvolatile memory device during the first flush operation.Type: ApplicationFiled: February 27, 2019Publication date: January 9, 2020Inventor: Hae-Gi CHOI
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Publication number: 20200012604Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; at least one cache memory; and a coherence circuit coupled to the at least one cache memory. The coherence circuit may have a direct memory access circuit to receive a write request, and based at least in part on an address of the write request, to directly send the write request to a device coupled to the processor via a first bus, to cause the device to store data of the write request to a device-attached memory. Other embodiments are described and claimed.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Inventor: Ishwar Agarwal
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Publication number: 20200012605Abstract: Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access rules defining permissible access to the identified memory addresses that depends on the value of one or more registers stored in the memory system. In some examples, the value of the registers (e.g., a Platform Configuration Register) may depend on a state of a computing device in which the memory system is installed.Type: ApplicationFiled: July 10, 2019Publication date: January 9, 2020Inventor: Lance W. Dover
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Publication number: 20200012606Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: ApplicationFiled: July 9, 2019Publication date: January 9, 2020Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Publication number: 20200012607Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Inventors: Wongyu SHIN, Leesup KIM, Youngsuk MOON, Yongkee KWON, Jaemin JANG
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Publication number: 20200012608Abstract: A computer-implemented method includes receiving, by a computing device, input activations and determining, by a controller of the computing device, whether each of the input activations has either a zero value or a non-zero value. The method further includes storing, in a memory bank of the computing device, at least one of the input activations. Storing the at least one input activation includes generating an index comprising one or more memory address locations that have input activation values that are non-zero values. The method still further includes providing, by the controller and from the memory bank, at least one input activation onto a data bus that is accessible by one or more units of a computational array. The activations are provided, at least in part, from a memory address location associated with the index.Type: ApplicationFiled: July 17, 2019Publication date: January 9, 2020Inventors: Dong Hyuk Woo, Ravi Narayanaswami
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Publication number: 20200012609Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having: an accelerator interface for connection to the subsystem to enable transfer of batches of data between the subsystem and the gateway; a data connection interface for connection to external storage for exchanging data between the gateway and storage; a gateway interface for connection to at least one second gateway; a memory interface connected to a local memory associated with the gateway; and a streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data are selectively via at least one of the accelerator interface, data connection interface, gateway interface and memory interface.Type: ApplicationFiled: December 28, 2018Publication date: January 9, 2020Applicant: Graphcore LimitedInventors: Ola Tørudbakken, Brian Manula, Harald Høeg
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Publication number: 20200012610Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Applicant: Amazon Technologies, Inc.Inventors: Leah Shalev, Adi Habusha, Georgy Machulsky, Nafea Bshara, Eric Jason Brandwine
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Publication number: 20200012611Abstract: The present invention relates to a bridge device operable between a master device and a slave device of a communication system, said master device and said slave device arranged for communicating with each other via a parent I2C bus and a child I2C bus and using the I2C protocol, said bridge device comprising—a parent module arranged for connecting said parent I2C bus and comprising a parent I2C transmitter/receiver device and a parent module state machine, —a child module arranged for connecting said child I2C bus and comprising a child I2C transmitter/receiver device and a child module state machine, whereby said parent module and said child module each comprise an internal bridge interface to exchange messages between said parent module and said child module, said messages being generated by said parent module state machine or said child module state machine in response to a change of state caused by an event on their respective I2C buses, whereby said parent module and said child module are each arrangedType: ApplicationFiled: December 15, 2017Publication date: January 9, 2020Inventors: Jasper Van Bourgognie, Vianney Le Clément de Saint-Marcq, Riemer Grootjans, Peter Verstraeten
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Publication number: 20200012612Abstract: This disclosure relates to a communicating apparatus, a communication method, a program, and a communication system that each enable execution of more reliable communication. A communicating apparatus includes a transmitting and receiving part that executes transmission and reception of signals with at least one or more other communicating apparatuses through a data signal line and a clock signal line, and an error avoiding part that, in a state where a communication system configured to be able to execute communication through a bus already operates, executes a process of avoiding occurrence of any error occurring when a communicating apparatus is additionally connected to the communication system. This technique is applicable to, for example, a bus IF.Type: ApplicationFiled: January 31, 2018Publication date: January 9, 2020Inventors: Hiroo Takahashi, Takashi Yokokawa, Toshihisa Hyakudai, Naohiro Koshisaka
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Publication number: 20200012613Abstract: In example implementations, a method to change a data transfer configuration of a data cable is provided. The method includes receiving a selection of a data transfer configuration option from a plurality of different data transfer configuration options of a data cable that has data lanes to transfer video data and non-video data. A reported number of supported resolutions or refresh rates is modified in accordance with the data transfer configuration option that is selected. The reported number of supported resolutions or refresh rates that is modified is then transmitted to a computing device connected to a display device via the data cable to transmit data via the data cable in accordance with the data transfer configuration option that is selected.Type: ApplicationFiled: February 1, 2017Publication date: January 9, 2020Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: John W. Frederick, Tim Guynes, Wen-Shih Chen
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Publication number: 20200012614Abstract: For adjusting a signal transmission direction in a cable, which is configured to be electrically coupled between a first interface port and a second interface port, an electric characteristic on at least a first pin of the first interface port is detected. Then a signal transmission direction of at least one pair of differential signal transmission channels in the cable is controlled to change from a first direction to a second direction different from the first direction, provided that a communication protocol between the first interface port and the second interface port is changed from a first communication protocol to a second communication protocol, and the electric characteristic complies with a first condition.Type: ApplicationFiled: July 5, 2019Publication date: January 9, 2020Inventors: YU-LUNG LIN, HSUAN-JUI CHANG
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Publication number: 20200012615Abstract: The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. An I3C master receives a max read length and a max write length from an I3C slave. Then, when transmitting/receiving data to/from the I3C slave, the I3C master controls transmission/reception of the data so that the data to be transferred in one data transfer has a data length equal to or shorter than the max read length and the max write length, and transmits transfer length information indicating the data length of the data to be transferred, prior to data transfer of the data. The present technology is applicable to a bus IF, for example.Type: ApplicationFiled: March 9, 2018Publication date: January 9, 2020Inventors: Hiroo Takahashi, Naohiro Koshisaka
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Publication number: 20200012616Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.Type: ApplicationFiled: July 1, 2019Publication date: January 9, 2020Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Publication number: 20200012617Abstract: Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.Type: ApplicationFiled: July 1, 2019Publication date: January 9, 2020Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Publication number: 20200012618Abstract: Providing reconfigurable fusion of processing elements (PEs) in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device provides a vector processor including a plurality of PEs and a decode/control circuit. The decode/control circuit receives an instruction block containing a vectorizable loop comprising a loop body. The decode/control circuit determines how many PEs of the plurality of PEs are required to execute the loop body, and reconfigures the plurality of PEs into one or more fused PEs, each including the determined number of PEs required to execute the loop body. The plurality of PEs, reconfigured into one or more fused PEs, then executes one or more loop iterations of the loop body. Some aspects further include a PE communications link interconnecting the plurality of PEs, to enable communications between PEs of a fused PE and communications of inter-iteration data dependencies between PEs without requiring vector register file access operations.Type: ApplicationFiled: July 5, 2018Publication date: January 9, 2020Inventors: Hadi Parandeh Afshar, Amrit Panda, Eric Rotenberg, Gregory Michael Wright
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Publication number: 20200012619Abstract: A size associated with a first content file is determined to be less than a threshold size. In response to determining that the size associated with the first content file is less than the threshold size, a combined metadata structure is updated at least in part by combining metadata of the first content file with metadata of a second content file in the combined metadata structure. A snapshot tree is updated to reference a first portion of the combined metadata structure corresponding to the first content file and to reference a second portion of the combined metadata structure corresponding to the second content file.Type: ApplicationFiled: May 30, 2019Publication date: January 9, 2020Inventors: Apurv Gupta, Anirvan Duttagupta
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Publication number: 20200012620Abstract: A system and method for performing an image level restore of data is described. In some examples, the system receives a request to restore a file and transmits the request to an intermediate component. The intermediate component may then retrieve a directory file from an image of a secondary copy of a data set, identify a location of the file from the directory file, and provide the location to the requestor.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Inventor: Kamleshkumar K. Lad
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Publication number: 20200012621Abstract: Merging directory information from a user directory to a common directory includes based on a rule associated with contents of a user directory of a local database, extracting a department indicator from the user directory, mapping the department indicator to a corresponding user record in a common directory of a registry database, and based on the department indicator, marking the user record in the common directory with a department that corresponds to the contents from the user directory with a department for controlling access to that user record in the registry database.Type: ApplicationFiled: August 26, 2019Publication date: January 9, 2020Inventors: Gordon E. Hegfield, Russell Holden, Stanley K. Jerrard-Dunne, Ravi Ranjan
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Publication number: 20200012622Abstract: In embodiments, secure compression algorithms are provided that may be employed as a single operation on raw data to produce compressed and encrypted data. In embodiments, the algorithms described herein may be performed using any type of dictionary based encryption. In one embodiment, upon adding a new prefix to a dictionary table, the dictionary table may be permuted to randomize the entries into the table. The randomization may be based upon a permutation value generated by a deterministic pseudo-random generator and/or pseudo-random function. Other embodiments of randomization may be employed to provide secure compression. For example, instead of permuting the entire table upon adding a prefix, the prefix may be randomly added to the table.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: James KELLEY, Roberto TAMASSIA
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Publication number: 20200012623Abstract: Embodiments of systems and methods as disclosed may provide a platform agnostic way to edit content within an enterprise. For example, a platform independent thin client editor may be provided such that this editor can be accessed by users at a variety of computing platforms across the distributed computer network of an enterprise, regardless of the platform from which the thin client editor is being accessed. Moreover, certain embodiments may provide a role based mechanism for controlling the editing of content. Embodiments of such a role based mechanism may allow one editor of a content item to designate a role associated with the content item so that only users associated with that role may be allowed to edit the content item or portion of the content item.Type: ApplicationFiled: December 3, 2018Publication date: January 9, 2020Inventors: Jeffrey Alan Cole, James Matthew Downs, Steven Mark Cheal, Jack Dwane Gilvin, Jeffrey Michael Doyle
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Publication number: 20200012624Abstract: Techniques for enabling fail-safe operations of storage devices are described. A device may be configured to delete an inode in a failsafe manner. A device may be configured to mark directory entries as not in use and ensure this goes to disk before anything else. A device may be configured to create an inode in a failsafe manner. A device may be configured to allocate and initialize a cluster and ensure this is written to disk before anything else. In this manner, a volume may be in a predictable state upon a failure occurring.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Applicant: Tuxera Inc.Inventors: Anton Ivanov ALTAPARMAKOV, Szabolcs SZAKACSITS
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Publication number: 20200012625Abstract: The present disclosure is directed to a novel system that incorporates extended recognition capabilities to a node in a distributed ledger network. In particular, a node within a distributed ledger network may be configured to simultaneously perform DLT functions while also performing information server and data management functions with respect to outside networked systems. By operating a multi-function DLT node with extended recognition mechanism in this way, an entity may efficiently distribute computing workloads when performing DLT and non-DLT functions.Type: ApplicationFiled: September 10, 2019Publication date: January 9, 2020Applicant: Bank of America CorporationInventors: Govinda Rajulu Nelluri, Srinivasa Rao Dakshinyam
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Publication number: 20200012626Abstract: Systems and methods for searching data are disclosed. For example, the system may include one or more memory units storing instructions and one or more processors configured to execute the instructions to perform operations. The operations may include receiving a sample dataset and identifying a data schema of the sample dataset. The operations may include generating a sample data vector that includes statistical metrics of the sample dataset and information based on the data schema of the sample dataset. The operations may include searching a data index comprising a plurality of stored data vectors corresponding to a plurality of reference datasets. The stored data vectors may include statistical metrics of the reference datasets and information based on corresponding data schema. The operations may include generating, based on the search and the sample data vector, one or more similarity metrics of the sample dataset to individual ones of the reference datasets.Type: ApplicationFiled: May 7, 2019Publication date: January 9, 2020Applicant: CAPITAL ONE SERVICES, LLCInventors: Austin WALTERS, Vincent PHAM, Galen RAFFERTY, Anh TRUONG, Mark WATSON, Jeremy GOODSITT
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Publication number: 20200012627Abstract: According to an embodiment, a method of building a database in which voice signals match texts comprises providing a captcha-purposed voice signal including a first voice signal matched with a first text and a second voice signal matched with no text, sending a request for a first input text and a second input text for the captcha-purposed voice signal, when the first input text and the second input text are received, comparing the first text with the first input text, and when the first text is identical to the first input text, matching the second voice signal with the second input text and storing the match. Embodiments of the present invention may be related to artificial intelligence (Al) modules, unmanned aerial vehicles (UAVs), robots, augmented reality (AR) devices, virtual reality (VR) devices, and 5G service-related devices.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Applicant: LG ELECTRONICS INC.Inventor: Dami Kim
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Publication number: 20200012628Abstract: Systems and methods for managing recent data items in a database. A method typically includes determining whether a data object managed by an on demand service is designated as able to be accessed by a user at a mobile device and storing locally at a mobile device a plurality of most recently used items viewed for a data object designated as able to be accessed by a user at a mobile device. The method also typically includes determining a single most recently used set from among the stored plurality of most recently used items viewed for at least one data object designated as able to be accessed by a user at a mobile device.Type: ApplicationFiled: July 19, 2019Publication date: January 9, 2020Inventors: Larry Robinson, Erik Forsberg
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Publication number: 20200012629Abstract: A system and method for generating a column-oriented data structure repository for columns of single data types. The method includes: receiving instructions to generate a new column of a single data type for a first data structure, wherein the first data structure is a column oriented data structure; and storing, based on the instructions, the new column within the column-oriented data structure repository, wherein the column-oriented data structure repository is accessible to at least a second user account.Type: ApplicationFiled: June 26, 2019Publication date: January 9, 2020Applicant: Monday.com Ltd.Inventors: Daniel LEREYA, Roy MANN, Eran ZINMAN, Tal HARAMATI
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Publication number: 20200012630Abstract: A data management system accesses a set of vectors containing binary values and generates vector blocks comprising binary values from each vector. Each of at least a portion of the vector blocks for each vector contain a set of two or more binary values from the vector. The data management system generates a block index based on the vector blocks. The block index includes a set of vector block arrays, each vector block array corresponding to a position in the vectors and including the binary values of a vector block from each vector. The data management system can identify relevant vectors for a target vector by generating vector blocks from the target vector and querying the block index to identify candidate vectors.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Inventors: Roberto Daniel Konow Krause, Seema Jethani, Mohnish Kodnani, Vishnusaran Ramaswamy, Jonathan Baggott, Harish Kumar Vittal Murthy
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Publication number: 20200012631Abstract: Aspects described herein relate to methods and systems for comparing data stored in disparate parallel systems using hash sums. A database having a parallel system architecture may comprise a plurality of nodes each storing a plurality of records. A central node may initiate parallel calculation of a set of node hash sums for each individual node. Calculating a node hash sum for an individual node may comprise calculating, by the individual node, a set of hash values for each individual record of the plurality of records stored by the individual node and combining each hash value of the set of hash values to generate the node hash sum for the individual node. The central processor may combine each node hash sum to generate a database hash sum. The central processor may store the generated database hash sum and/or utilize it in comparisons with database hash sums for other databases.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Dirk Anderson, Haresh Kurani
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Publication number: 20200012632Abstract: Techniques for improving database searches are described herein. In an embodiment, a server computer system stores one or more first datasets in a first data repository and one or more second datasets in a second data repository. The server computer receives a request to perform an analysis on a particular dataset. The server computer determines that the particular dataset is stored in the first data repository and the second data repository. Based, at least in part, on an attribute of the request, the server computer selects the second data repository and responds to the request with data from the particular dataset stored in the second data repository.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Inventors: Christopher Brockington-Hill, Neil Rickards
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Publication number: 20200012633Abstract: A computer implemented method is provided comprising receiving a group of transaction logs from a first database, allocating transaction logs from the group of transaction logs to a first queue and to a second queue, generating an end-of-group transaction log indicative of an end of the group of transaction logs, allocating the end-of-group log to the first queue and the second queue; replaying transaction logs from the first queue including the end-of-group transaction log allocated to the first queue, replaying transaction logs from the second queue including the end-of-group transaction log allocated to the second queue; and changing visibility of one or more transactions in response to replaying the end-of-group transaction log allocated to the first queue and the end-of-group transaction log allocated to the second queue. Related apparatus, systems, techniques and articles are also described.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Inventors: Kyu Hwan Kim, Juchang Lee, Beomsoo Kim, Chang Gyoo Park, Reiner Singer, Christoph Roterring, Werner Thesing, Michael Muehle
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Publication number: 20200012634Abstract: Systems and methods are disclosed for certifying an equipment by connecting to a distributed ledger; capturing a physical location and a schematic location of the equipment; performing a test on the equipment; taking a picture of the equipment being tested; and certifying a test result and rendering the test results as immutable records on the distributed ledger.Type: ApplicationFiled: January 18, 2019Publication date: January 9, 2020Inventor: Christopher Eberhardt
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Publication number: 20200012635Abstract: Methods, systems, and products characterize consistency of data in a stream warehouse. A warehouse table is derived from a continuously received a stream of data. The warehouse table is stored in memory as a plurality of temporal partitions, with each temporal partition storing data within a contiguous range of time. A level of consistency is assigned to each temporal partition in the warehouse table.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Applicant: AT&T Intellectual Property I, L.P.Inventors: Theodore Johnson, Lukasz Golab
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Publication number: 20200012636Abstract: A method for identifying maximal independent sets in parallel may include, on a processor, accessing data representing an undirected graph, generating a respective initial priority value for each vertex, dependent on the vertex degree and an average degree for vertices in the graph, and recording an indication of the initial priority value for each vertex. The method may include determining, for multiple vertices, that no neighbor vertex has a priority value that is higher than that of the vertex. In response, the method may include recording respective indications that each neighbor vertex connected is not to be included in a maximal independent set for the undirected graph and recording an indication that the vertex is to be included in the maximal independent set. The determinations and recordings may be performed in parallel by respective processing elements of the processor. The processor may be a GPU.Type: ApplicationFiled: February 6, 2017Publication date: January 9, 2020Inventors: Martin Burtscher, Sindhu Devale