Abstract: Arithmetic circuits and methods that perform efficient conversion of fractional RNS representations to fractional binary representations is disclosed herein.

Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.

Abstract: Methods, computer systems, computer-storage media, and graphical user interfaces are provided for facilitating application development. In embodiments, input is received from a designer, the input including an indication of a class of applications and one or more preferences for designing a module specification. Thereafter, the module specification is created in association with the class of applications. Input is received from a teacher in association with the module specification. At least a portion of such input indicates how to recognize when a user intends to run an application. An application is generated based on the input provided from the teacher. Such an application can be used by one or more users.

Abstract: A program is executed that includes multiple script functions. For a selected script function, the following are performed during program execution. It is determined whether the selected script function should or should not be executed based on a utility corresponding to the selected script function. The utility was determined prior to determining whether the selected script function should be executed. The selected script function is executed in response to a determination the selected script function should be executed. Execution of the selected script function is skipped in response to a determination the selected script function should not be executed. These techniques may be applied in real-time to crawl a program such as a webpage or may be applied using offline learning followed by a real-time crawling of the program. Apparatus, methods, and program products are disclosed.

Abstract: Methods and systems are disclosed that automate and institutionalize many aspects of the process of creating software. Embodiments automate aspects of pricing, software creation, and delivery using a manufacturing-styled approach to development that reuses existing code and other existing software design features.

Abstract: During a process called live design, a computing system may receive, from a repository, an instance of a first component comprising a first set of one or more metaobjects that provides a binary representation of the instance of the first component. In turn, the computing system may render the instance of the first component as an icon and a first set of one or more underlying panes that provide a visual expression of the instance of the first component. The computing system may then receive, via the first set of one or more underlying panes, a user modification to the instance of the first component. Thereafter, the computing device and/or the repository may determine whether the user modification to the instance of the first component is valid, and may process the user modification in accordance with the determining.

Abstract: The present disclosure relates to an electronic application developing method. The method comprises providing a development platform with a plurality of cross-industry application templates. Users can design applications and plan business processes via the development platform efficiently without building any infrastructure or writing any programming code.

Abstract: Apparatus and methods are described for adapting a programming environment to handle renamed programming constructs such as classes and packages. Non-canonical identifiers that reference renamed programming constructs can be used in code parts to be executed in the programming environment, and the code parts can execute, without disruption or user intervention, using related canonical identifiers. The solutions described herein provide backward and forward compatibility for code and data affected by renaming of programming constructs.

Abstract: Disclosed are examples related to building a customized data collection widget. Building of the customized data collection widget includes receiving a selection of several universal modules for inclusion in the widget. Each universal module of the selected several universal modules may include programming code that causes rendering of user-fillable data fields on a display, and a summary page including data requirements of the respective universal module. Based on the data requirements in a summary page of each respective universal module of the selected several universal modules, the selected several universal modules retrieved from a module repository may be combined in a customized data collection container stored in a composite repository. The selected customized data collection container may be combined with selected other data collection containers to form a uniquely identifiable, customized data collection widget. The customized data collection widget may be delivered to the composite repository.

Abstract: A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.

Abstract: The invention pertains to a method of implementing packet-processing devices on multi-table datapath processors, comprising of a high-level, Turing-complete programming language that permits programmers to express time-invariant or time-variant packet-processing behavior using general-purpose programming languages, suitable compilation and analysis methods to transform a given input program into a datapath design, and a runtime control program to be executed on a general-purpose processor which can communicate with a configurable datapath element and which configures the datapath element according to the compiled datapath design and which implements appropriate dynamic control (e.g. flow table population) for the configured datapath element.

Abstract: Methods and systems for optimizing a build order of component source modules comprises creating a dependency graph based on dependency information. Historical build information associated with previous build failures is then used to calculate relative failure factors for paths of the dependency graph; and the relative failure factors are used to determine an order of traversal of the dependency graph during a build process in which component binary modules are built from the component source modules.

Abstract: Systems and methods are described for enabling cross-environment application of tracing information for code, such as code executed within an on-demand (or “serverless”) code execution system. Various optimizations exist that allow execution of code to proceed faster or more efficiently over time, by collecting tracing information regarding the execution and using that tracing information to guide compilation of the code. These optimizations are typically designed for long-lived environments. However, executions within an on-demand code execution system often occur in short-lived environments, reducing or eliminating any gains from these optimizations. To address this issue, tracing information can be maintained across multiple environments on the system, allowing subsequent executions to be optimized based on tracing information of prior executions in other environments.

Abstract: An apparatus includes a processor to: receive a job flow definition; retrieve the most recent versions of a set of task routines for the defined job flow; translate, into an intermediate representation, executable instructions of each task routine implementing an interface for data input and/or output during execution; translate executable instructions of the job flow definition that defines the interface for each task routine into an intermediate representation; compare each intermediate representation from a task routine to the corresponding intermediate representation from the job flow definition to determine if there is a match; and in response to there being a match for each comparison and to the executable instructions of the job flow definition being written in a secondary programming language, translate the executable instructions of the job flow definition into a primary programming language, and store the resulting translated form of the job flow definition in a federated area.

Abstract: A technique for deploying an application in a cloud computing environment includes: collecting, while a user is deploying an application, metadata and instructions issued by the user on deploying the application, the metadata comprising service metadata, application metadata and topology metadata, wherein the service metadata comprise metadata on a service required for deploying the application, the application metadata comprise metadata on the application, and the topology metadata comprise metadata indicative of a relationship between the service and the application; and storing the collected metadata and instructions as a model for re-deploying the application.

Abstract: Sharing data among computing systems can include receiving, using a processor, a data transfer event indicating a transfer of a data file from a source system to a target system, querying, using the processor, the source system for an operating system executed by the source system and a file type of the data file, and querying, using the processor, the target system for an operating system executed by the target system. A target application can be determined using the processor. The target application is adapted for execution on the operating system executed by the target system and is adapted for operating on the file type. Installation of the target application on the target system can be initiated. Further, transfer of the data file from the source system to the target system can be initiated using the processor.

Abstract: A device can store a plurality of variants of an application. The device can receive, from a user device that is associated with a first variant of the application, a request for a second variant of the application. The first variant can include a first set of features and include a file size that is different than the second variant. The second variant can include a second set of features. The device can determine a first version identifier of the first variant of the application, and determine that a second version identifier associated with the second variant of the application is different than the first version identifier. The device can provide, to the user device, the second variant of the application to permit the user device to install the second variant of the application.

Abstract: An electronic whiteboard includes a white list in which predetermined software is registered, a mode switching unit configured to switch a normal mode in which software unregistered in the white list is not permitted to be installed and an install mode in which the unregistered software is permitted to be installed, an invalidating/validating processor configured to invalidate the white list in the install mode, and a registerer configured to register software installed while the white list is invalidated in the white list, in which the invalidating/validating processor validates the white list after the installed software is registered in the white list.

Abstract: A user account that does not have administrator privileges may request mounting of a disk image prior to installing a new application. An agent, registered with operating system, receives notification and determines whether or not to allow mounting of the disk image. If so, the agent causes the disk image to be mounted by the operating system. The agent examines the mounted disk image to detect an application bundle. The agent determines whether or not to proceed with installation of the application bundle and, if so, then causes the application bundle to be copied to a privileged system location, thereby installing the application on the computer device.

Abstract: Systems and methods for centralized client application management are provided. In an example embodiment, device data is received from a user device. The user device is identified according to an identification rule. A client state is received from the user device. A match between the client state and a specified state is determined. Based on the client state matching the specified state, an instruction to be performed on the user device is generated. The instruction is caused to be performed on the user device. The instruction causes a change to the client state stored on the user device.

Abstract: A method and system for automating application of software patches to a server system having a virtualization layer. A plurality of software patches are downloaded to a computer system having a first operating system. The software patches to apply to a server console operating system are then determined. The software patches are automatically copied to the server system by executing a first script file. The copied software patches are automatically decompressed by executing a second script file. The decompressed software patches are installed in a specified order by executing the second script file. The console operating system is rebooted only after all software patches are installed.

Abstract: Techniques that facilitate group patching recommendation and/or remediation with risk assessment are provided. In one example, a system includes a vertical stack component, a horizontal stack component and a risk classification component. The vertical stack component identifies a first patch profile from a software system associated with a computer system environment. The horizontal stack component identifies a second patch profile from a hardware system associated with network nodes of the computer system environment. The system learns over time to identify repetitive patterns using machine learning techniques. Then, the risk classification component performs a machine learning process to determine a risk classification for the computer system environment based on the first patch profile and the second patch profile.

Abstract: A deployment subsystem provides updates to an application and/or software executed by server computer systems. The update is included in an update script. Execution of the update script by a server computer system causes the server computer system to execute a set of checks. After completing the set of checks the server computer system may execute the update to the application and/or software executed by server computer systems.

Abstract: An information processing apparatus to which an input apparatus is connected through a wire or wirelessly is provided. The information processing apparatus includes a memory and a processor coupled to the memory. The processor executes an application program in accordance with an operation by a user accepted by the input apparatus, obtains update data for firmware of the input apparatus from a server through a network, and performs processing for updating the firmware of the input apparatus in response to a request from the application program while the application program is being executed. The processor suspends execution of the application program before update of the firmware and resumes execution of the application program in response to completion of update of the firmware.

Abstract: Embodiments of the present invention provide an application upgrade method and an apparatus. The application upgrade method includes: receiving an application deployment request; determining a deployment package of a to-be-deployed application; determining that a version of a first platform node is below a version requirement of a node template of the to-be-deployment application for a first platform node template; acquiring a first platform node upgrade package that meets the version requirement of the node template of the to-be-deployed application for the first platform node template; upgrading the first platform node indicated by an identifier of the first platform node by using the first platform node upgrade package; determining an identifier of a to-be-upgraded application node; and upgrading the application node indicated by the identifier of the to-be-upgraded application node by using the deployment package of the to-be-deployed application.

Abstract: An object of the present invention is to reduce a time taken for updating of firmware data using unrecoverable data in an apparatus having a plurality of nonvolatile memories. The present invention is an apparatus having a plurality of nonvolatile memories, the apparatus including: an acquisition unit configured to acquire firmware updating data for updating firmware data saved in each of the plurality of nonvolatile memories; and a control unit configured to perform control so as to perform in parallel updating of the firmware data saved in a first nonvolatile memory by unrecoverable data included in the acquired firmware updating data and updating of the firmware data saved in a second nonvolatile memory by the unrecoverable data.

Abstract: The disclosed technology is generally directed to the patching of executing binaries. In one example of the technology, at separate times, a plurality of hot patch requests is received. Each hot patch request of the plurality of hot patch requests includes a corresponding hot patch to hot patch the executing binary. A cardinality of the plurality of hot patch requested is greater than the fixed number of logical patch slots. with the executing binary continuing to execute, each time a request to apply a hot patch to the executing binary is received, the corresponding hot patch is assigned to an inactive logical patch slot of the fixed number of logical patch slots. The corresponding hot patch is executed from the assigned logical patch slot to hot patch the executing binary based on the corresponding hot patch.

Abstract: An aspect of module mirroring during an non-disruptive upgrade includes creating a mirrored set of management processes for a storage cluster that is subject to an upgrade a new software version, interconnecting components of the mirrored set and an original set of the management processes while the storage cluster is actively managed by an original set of management processes, and performing a handover between the management processes of the storage cluster.

Abstract: Systems and methods for preventing service disruptions in a computing system. The methods comprise: receiving, at a cloud-based computing system, messages for initiating software updates requiring system reboots by remote computing machines; and performing operations by the cloud-based computing system to cause an operational state of only one remote computing machine to be transitioned from an online state to an offline state at any given time by scheduling the software updates and system reboots in a one-machine-at-a-time manner.

Abstract: A non-stop multi-host transaction processing environment may be created by receiving incoming user calls to components through a vestibule bank, and by utilizing an installation manager during the replacement of software. The installation manager may be used in connection with a vestibule bank to handle user calls during the installation of a replacement software component such that user calls for a component can be processed while that component is being replaced, without an error being passed back to the end user. During the replacement of a software component, user calls from the old component may be drained and diverted to a replacement component. User calls received during the installation may be queued and then routed to the replacement component once the component has been replaced.

Abstract: The embodiments herein disclose a method and a system for creating a singular platform to harness a plurality of technical capabilities in order to deliver multiple digital services such as end user device management, analytics, enterprise mobility, digital identity management, smart device management and so on by orchestrating certain service related support capabilities. The embodiments function as an interface between the user equipment and the applications that are running on several operating systems. Further, an enablement platform is created and modified for a digital ecosystem that sits on the network and user equipment to act as an interface. Essentially, a flexible and extensible API driven platform capable of seamlessly integrating multiple platforms spanning across network services and functions, analytics, device management and orchestration platforms in enabled.

Abstract: A technology is described for redirecting a service request to a service proxy on a software development host. An example method may include receiving a service request directed to a service hosted in a service provider environment. In receiving the service request, a determination may be made that a service proxy simulates the service on a software development host, and that the service proxy may be used to execute development code on the software development host. In response, the service request may be redirected to the service proxy on the software development host for handling of the service request.

Abstract: The present invention provides a vehicle-mounted control device, a program writing device, a program generating device, and a program, which are capable of quickly and easily carrying out reprogramming. An ECU 300 is provided with: a microcomputer 301, an SRAM 302, a flash memory 303, and a communication device 305. The flash memory 303 is configured from a plurality of blocks and stores older versions of the program. The communication device 305 receives (S250) a frame including block data, the type of the block data, and an address of a block in which the block data is to be written. The microcomputer 301 restores (S260) a new program from the block data in the SRAM 302 according to the type of the block data (S255, S260) and writes (S265, S270) one piece of the restored new program in a block corresponding to the address.

Abstract: In one embodiment, a method includes accessing a query vector; accessing object vectors; determining input distances corresponding to a distance between the query vector and the object vectors; accessing thread queues; accessing a warp queue; for each of the input distance values: selecting one of the thread queues, when the input distance value is less than a greatest one of the distance values stored in the selected thread queue, inserting the input distance value into the thread queues and ejecting the greatest distance values stored in the thread queue, and when a greatest distance value stored in any of the thread queues is less than a greatest distance value stored in the warp queue, merging the thread queue with the warp queue; identifying the objects represented by an object vector corresponding to the distance values stored in the warp queue; and providing the search results for presentation.

Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

Abstract: Disclosed embodiments relate to a method and apparatus for efficient matrix transpose. In one example, a processor to execute a matrix transpose instruction includes fetch circuitry to fetch the matrix transpose instruction specifying a destination matrix and a source matrix having (N×M) elements and (M×N) elements, respectively, a (N×M) load buffer, decode circuitry to decode the fetched matrix transpose instruction, and execution circuitry, responsive to the decoded matrix transpose instruction to, for each row X of M rows of the specified source matrix: fetch and buffer N elements of the row in a load register, and cause the N buffered elements to be written, in the same relative order as in the row, to column X of M columns of the load buffer, and the execution circuitry subsequently to write each of N rows of the load buffer to a same row of the load buffer.

Abstract: A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.

Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

Abstract: Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length search sequence of prior read commands is generated and that search sequence is then converted into an index value in a predetermined set of index values. A history pattern match table having entries indexed to that predetermined set of index values contains a plurality of read commands that have previously followed the search sequence represented by the index value. The index value is obtained via application of a many-to-one algorithm to the search sequence. The index value obtained from the search sequence may be used to find, and pre-fetch data for, a plurality of next read commands in the table that previously followed a search sequence having that index value.

Abstract: Prefetching data by determining that a first set of instructions that is processed by a computer processor indicates that a second set of instructions includes multiple iteration groups, where each of the iteration groups includes one or more loop-unrolled instructions, monitoring the second set of instructions as the second set of instructions is processed by the computer processor after the first set of instructions is processed by the computer processor, mapping a corresponding one of the loop-unrolled instructions in each of the iteration groups of the second set of instructions to a stride-tracking record that is shared by the corresponding loop-unrolled instructions, and prefetching data into a cache memory of the computer processor based on the stride-tracking record.

Abstract: A method of optimized congruence class matching for concurrent memory translation requests to avoid memory access conflicts with respect to a virtual memory managed by a processor is provided. The method includes initiating a first table walk by a first memory access of the concurrent memory translation requests and pending a subsequent table walk initiated by a subsequent memory access of the concurrent memory translation requests. Then, the method determines whether the subsequent table walk will cause a memory access conflict with the first table walk based on the optimized congruence class matching. The subsequent memory access is rejected when the subsequent table walk will cause the memory access conflict with the first table walk.

Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.

Abstract: A data processing apparatus and method are provided for executing a stream of instructions out-of-order with respect to original program order. At least some of the instructions in the stream identify one or more architectural registers from a set of architectural registers. The apparatus comprises a plurality of out-of-order components configured to manage execution of a first subset of instructions out-of-order, the plurality of out-of-order components being configured to remove false dependencies between instructions in the first subset. The plurality of out-of-order components include a first issue queue into which the instructions in the first subset are buffered prior to execution. A second issue queue is used to buffer a second subset of instructions prior to execution, the second subset of instructions being constrained to execute in order.

Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

Abstract: An apparatus and method are provided for controlling branch prediction. The apparatus has processing circuitry for executing instructions, and branch prediction circuitry that comprises a plurality of branch prediction mechanisms used to predict target addresses for branch instructions to be executed by the processing circuitry. The branch instructions comprise a plurality of branch types, where one branch type is a return instruction. The branch prediction mechanisms include a return prediction mechanism used by default to predict a target address when a return instruction is detected by the branch prediction circuitry. However, the branch prediction circuitry is responsive to a trigger condition indicative of misprediction of the target address when using the return prediction mechanism to predict the target address for a given return instruction, to switch to using an alternative branch prediction mechanism for predicting the target address for the given return instruction.

Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.

Abstract: A system includes a memory including a ring buffer having a plurality of slots, a processor in communication with the memory, a guest operating system, and a hypervisor. The hypervisor is configured to detect a request associated with a memory entry, retrieve up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot, and test a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged. Additionally, the hypervisor is configured to execute the request associated with the memory entries and respective valid descriptors. The hypervisor is also configured to walk the ring buffer backwards from the end slot to the original slot while clearing the valid descriptors.

Abstract: One or more architected registers are restored from a snapshot previously taken of the one or more architected registers. The snapshot indicates one or more physical registers previously assigned to the one or more architected registers. The restoring replaces the one or more physical registers currently assigned to the one or more architected registers with the one or more physical registers previously assigned to the one or more architected registers as indicated by the snapshot. A determination is made as to the validity of the one or more architected registers restored using the snapshot. The determining validity includes checking memory locations associated with the one or more architected registers to determine whether contents of the one or more architected registers have changed since the snapshot was taken. If the contents of the one or more architected registers have not changed, the one or more architected registers are valid.

Abstract: Embodiments are generally directed to a multithreaded processor for executing a plurality of threads, as well as an associated method and system. The multithreaded processor comprises a first control register configured to store a stack limit value, and instruction decode logic configured to, upon receiving a procedure entry instruction for a stack associated with a first thread, determine whether to throw a stack limit exception based on the stack limit value and a first predefined stack region size associated with the stack.