Abstract: To set data breakpoints on properties and certain other functions, constituent data locations (CDLs) that can contribute to computation of the property value or other function result are identified, and respective constituent data breakpoints are added at one or more CDLs by data breakpoint adder code. Each constituent data breakpoint will suspend execution of an inspectable software in response to occurrence of a CDL data entry. The CDLs are identified by CDL identifier code using static data flow analysis, enhanced interpretation, or disassembly, with recursion as appropriate. Kernel or runtime routines, and other routines designated as known, can be excluded from the CDL search. Data locations marked read-only, or that are effectively read-only because they will not be written, can also be excluded.

Abstract: A tool includes an interface, a memory, a conversion engine, an identifier tool, and a script engine. The interface communicatively couples the tool to a server. The tool obtains a plurality of visual inputs from a computer program specification document. The memory stores the plurality of visual inputs and a set of known computer code elements. Each respective element of the set of known computer code elements includes predetermined testing criteria for testing computer code that includes the respective element. The conversion engine generates a plurality of textual objects from the plurality of visual inputs. The identifier determines whether each respective textual object matches a respective element of the set of known computer code elements. If a match is found, the identifier tool associates the predetermined testing criteria of the respective element to the respective textual object. The script engine generates a test script using the predetermined testing criteria.

Abstract: An inventive method for validating an end user device for use with a medical application. A medical application and a validation application are received in the end user device and the validation application is then executed, which includes: (i) determining the hardware and software environment of the end user device; (ii) providing a validation process compatible with the hardware and software environment; (iii) executing a test mode of the medical application; (iv) running the validation process during the test mode; and (v) determining from running the validation process whether the medical application is compatible with the end user device. When the medical application is determined to be compatible with the end user device, a validation report is generated and stored in the end user device and/or a server. When the medical application is determined to be incompatible with the end user device, the medical application is at least partially blocked.

Abstract: A method for monitoring software testing applicable in an electronic device includes controlling a first communication device of the electronic device to communicate with a terminal device when the terminal device running a testing software is placed on the electronic device. A capturing device of the electronic device is controlled to capture a display screen of the terminal device to record a video of what appears on the screen as part of the software testing. The first communication device is controlled to acquire a test log of the terminal device when the test is completed; and the first communication device transmits the recorded video and the test log to a device to analyze the software testing.

Abstract: A system, method, and computer-readable medium for performing a customer service channel selection operation. The customer service channel selection operation includes identifying a plurality of customer service channels associated with an organization; collecting channel data associated with each of the plurality of customer service channels; processing the channel data associated with each of the plurality of customer service channels to generate channel metrics associated with each of the plurality of customer service channels; and, generating channel insights and predictions based upon the channel data associated with each of the plurality of customer services channels.

Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

Abstract: One embodiment facilitates data storage. During operation, the system receives data to be stored in a non-volatile memory of a storage device. The system determines, by a flash translation layer module of a control unit which is distinct from the storage device, a physical page address at which the data is to be stored in the non-volatile memory, wherein the flash translation layer module of the control unit determines physical page addresses for data to be stored in a plurality of storage devices. The system stores, by the flash translation layer module of the control unit, a mapping between a logical page address for the data and the physical page address. The system writes the data to the non-volatile memory at the physical page address.

Abstract: A memory control method for a rewritable non-volatile memory module which includes a plurality of physical groups is provided according to an exemplary embodiment of the disclosure. The memory control method includes: storing first table information into a first physical group among the physical groups, wherein the first table information records management information corresponding to a first logical range; storing second table information into a second physical group among the physical groups, wherein the second table information also records the management information corresponding to the first logical range; and instructing a reading of the second table information from the second physical group to obtain the management information corresponding to the first logical range in response to that the first physical group is in a default status.

Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to determine a set of requirements for a persistent storage media based on input from an agent, dedicate one or more banks of the persistent storage media to the agent based on the set of requirements, and configure at least one of the dedicated one or more banks of the persistent storage media at a program mode width which is narrower than a native maximum program mode width for the persistent storage media. Other embodiments are disclosed and claimed.

Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.

Abstract: Systems and methods for object load introspection using guarded storage are disclosed. In embodiments, a computer-implemented method includes: determining objects of interest designated by a user; splitting a first subset of a predetermined memory heap into guarded regions based on a number of objects of interest; allocating each of the objects of interest to a respective one of the guarded regions and remaining objects to a second subset of the predetermined memory heap; executing a program; detecting one of the objects of interest is loaded from one of the guarded regions; generating a trap that transfers control of the executing the program to a signal handler, wherein the signal handler is designated to perform a user-defined task associated with the one of the objects of interest; and executing, by the signal handler of the computing device, the user-defined task.

Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: A data storage device includes a nonvolatile memory apparatus including a plurality of memory blocks, and a controller configured to control the nonvolatile memory apparatus. The controller determines update frequency for data stored in first memory blocks of the plurality of memory blocks, controls the nonvolatile memory apparatus to store target data of the data stored in the plurality of memory blocks in second memory blocks, of the plurality of memory blocks, the target data indicating data having the update frequency exceeding preset threshold update frequency, sets garbage collection execution conditions of the first memory blocks and the second memory blocks to be different from each other, and controls the nonvolatile memory apparatus to perform garbage collection for the first memory blocks and the second memory blocks according to the garbage collection execution conditions set to be different from each other.

Abstract: A data storage device may include a storage including a plurality of memory blocks composed of system memory blocks for storing system data and user memory blocks for storing user data; and a controller configured to: control exchange of the system and user data with the storage in response to a request of a host device; and determine whether a start condition for performing a garbage collection operation on the storage is satisfied, based on a number of bad memory blocks in the plurality of memory blocks.

Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.

Abstract: Techniques are provided for providing a fully active and non-replicated block storage solution in a clustered filesystem that implements cache coherency. In a clustered filesystem where one or more data blocks are stored in a respective cache of each host node of a plurality of host nodes, a request is received at a host node of the plurality of host nodes from a client device to write the one or more data blocks to a shared storage device. In response to the request, the one or more data blocks are stored in the cache of the host node and a particular notification is sent to another host node of the plurality of host nodes that the one or more data blocks have been written to the shared storage device. In response to receiving the notification, the other host node invalidates a cached copy of the one or more data blocks in the respective cache of the other host node.

Abstract: A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each snoop filter is associated with a subset of all caching agents within the system. Each snoop filter uses an algorithm chosen for best performance on the caching agents associated with the snoop filter. The number of snoop filter entries in each snoop filter is primarily chosen based on the caching capacity of just the caching agents associated with the snoop filter. The type of information stored in each snoop filter entry of each snoop filter is chosen to meet the desired filtering function of the specific snoop filter.

Abstract: To deliver up-to-date, coherent user data to applications upon request, the disclosed technology includes systems and methods for caching data and metadata after it has been synchronously loaded—for future retrieval with a page load time close to zero milliseconds. To provide this experience, data needs to be stored as locally to a user as possible, in the cache on the local device or in an edge cache located geographically nearby, for use in responding to requests.

Abstract: The present disclosure relates to computer-implemented systems and methods for locking a region in a cache. In one implementation, a system for locking a cache region may include least one cache configured to store data; at least one register configured to store addresses; and at least one logic circuit configured to perform operations. The operations may include select a portion of the at least one cache for storing one or more lines of data; apply one or more comparator functions to one or more addresses of the selected portion and the stored addresses; and when the one or more addresses of the selected portion and the stored addresses do not overlap, store the one or more lines of data in the selected portion.

Abstract: Apparatuses and methods of operating apparatus are disclosed. A processing element performs data processing operations with respect to data items stored in data storage. In a first mode the processing element references the data items using physical addresses and in a second mode the processing element references the data items using virtual addresses. A data access request handling unit receives data access requests issued by the processing element and cache stores cache lines of temporary copies of the data items retrieved from the data storage, wherein a cache line in which a data item is stored in the cache is selected in dependence on an address index portion.

Abstract: A data storage device may include a storage that store data in a plurality of physical storage spaces to which physical addresses are assigned, respectively, and a controller that control the storage, wherein the controller includes a mapping table of the physical addresses corresponding to logical addresses managed by a host, and wherein the controller is further configured to read data, in a primary read operation, from a physical storage space of a physical address corresponding to a logical address requested to be read by the host among the plurality of physical storage spaces according to the mapping table, obtain a normal physical address corresponding to the logical address requested to be read through the mapping table when the data read in the primary read operation is erased data; and read data, in a secondary read operation, from a physical storage space of the normal physical address.

Abstract: A data caching device includes a first recorder, configured to record busy identifiers and idle identifiers in a plurality of read identifiers with each busy identifier corresponding to a data burst to be read; and a cache, including a head pointer and a tail pointer for performing loop access to the cache, and a cache space defined by the head pointer and the tail pointer. Corresponding to each busy identifier, the cache space includes a cache subspace for storing the corresponding data burst. The data caching device also includes a controller, configured to write the data burst read from a memory into the cache subspace corresponding to each busy identifier in a preset order, and in response to a last data block of the data burst being written in the cache subspace, update the first recorder, and change the busy identifier to an idle identifier.

Abstract: A system and method for efficiently performing maintenance on a cache. In various embodiments, control logic in a cache controller or elsewhere receives an indication for invalidating a range of virtual-to-physical mappings in a given translation lookaside buffer (TLB). The logic determines a first latency to invalidate entries of the TLB based on a number of addresses in the range and a number of supported page sizes simultaneously stored in the TLB. The logic determines a second latency based on a number of entries in the TLB. If the first latency is greater, then the logic traverses through each TLB entry and invalidates TLB entries storing a virtual address within the range. If the first latency is smaller, then the logic traverses through each address in the range and invalidates TLB entries storing a virtual address within the range.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

Abstract: An apparatus has an address translation cache (12, 16) having a number of cache entries (40) for storing address translation data which depends on one or more page table entries of page tables. Control circuitry (50) is responsive to an invalidation request specifying address information to perform an invalidation lookup operation to identify at least one target cache entry to be invalidated. The target cache entry is an entry for which the corresponding address translation data depends on at least one target page table entry corresponding to the address information. The control circuitry (50) selects one of a number of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicating the page size of the target page table entry. The different invalidation lookup modes correspond to different ways of identifying the target cache entry based on the address information.

Abstract: A system transmits a target data file as a set of mathematical functions and data values representative of the target data file to a receiver, the system comprising at least one hardware processor and memory storing computer instructions, the computer instructions when executed by the at least one hardware processor configured to cause the system to identify a target bit pattern of a target data file; generate a set of mathematical functions and data values operative to generate the target bit pattern; and transmit the set of mathematical functions and data values to a receiver, which can use the set of mathematical functions and data values to generate the target data file.

Abstract: An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target sub-mapping table corresponding to the data address has been cached, wherein the target sub-mapping table is one of the sub-mapping tables; and if false, reading and caching the target sub-mapping table from the sub-mapping tables.

Abstract: A main memory device includes a first memory device; and a second memory device having an access latency different from that of the first memory device. The first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region.

Abstract: An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

Abstract: On power-up, self-encrypting drives (SEDs, 150) are unlocked one after another in an order based on the SEDs' unlocking priorities. In determining the priorities, one or more of the following factors are taken into account: (1) the content stored on the SEDs; the SEDs storing the OS are given higher priorities; (2) the SEDs' access history on previous power-ups: if a SED was accessed earlier than other SEDs, then this SED is given a higher priority; (3) whether there is an access request pending for a SED. Such prioritization allows the system to reach full functionality faster on power-ups. Other features are also provided.

Abstract: A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. The one semiconductor device may include an address output circuit configured to output the addresses. The one semiconductor device may include an encryption circuit configured to output the encrypted data based on normal data and the addresses. The one semiconductor device may include a decryption circuit configured to output the normal data based on the addresses and the encrypted data.

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to supply supported voltages to a host, provide temperature throttling information to the host, or provide an indication that a host attempting to read a result was not the host that caused the placement of the result in a result register. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Abstract: A realm management unit (RMU) maintains an ownership table specifying ownership entries for corresponding memory regions defining ownership attributes specifying, from among a plurality of realms, an owner realm of the corresponding region. Each realm corresponds to at least a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the corresponding region. Memory access is controlled based on the ownership table. In response to a region fuse command specifying a fuse target address indicative contiguous regions of memory to be fused into a fused group of regions, a region fuse operation updates the ownership table to indicate that the ownership attributes for the fused group of regions are represented by a single ownership entry. This provides architectural support for enabling improvement of TLB performance.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.

Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

Abstract: Enabling a protocol for efficiently and reliably using the NVME protocol over a network, referred to as NVME over Network, or NVMEoN, may include an NVMEoN exchange layer for handling exchanges between initiating and target nodes on a network, a burst transmission protocol that provides guaranteed delivery without duplicate retransmission, and an exchange status block approach to manage state information about exchanges.

Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.

Abstract: A system having a field bus coupler, a first module and a second module is provided. The field bus coupler includes a first field bus interface to a field bus and a first sub-bus interface to a sub-bus. The first module includes a control interface for connection to a control bus, a second sub-bus interface for communication with the field bus coupler and a first control output. The second module includes a control input and a power output. The first module is configured to derive a control signal from a signal which is received via the control interface during operation, and the second module is configured to control the power output of the second module in coordination with the control signal received via the control input.

Abstract: The present invention provides a method for automatically identifying host operating system. By applying the method of automatically identifying host operating system in a USB control unit of a USB device by a form of application program, library, variables, and/or operands, the USB control unit is therefore provided with a host operating system identifying function. As such, in case of a specific OS of a host device applying a USB enumeration to the forgoing USB device, the central processing unit would automatically identify (or detect) what the specific OS is. For example, the specific OS is identified as an Apple iOS operating system, a Microsoft Windows operating system, an Apple Mac OS operating system, or a Google Android operating system.

Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.

Abstract: Technologies for accessing pooled accelerator resources over a network fabric are disclosed. In disclosed embodiments, an application hosted by a computing platform accesses remote accelerator resources over a network fabric using protocol multipathing mechanisms. A communication session is established with the remote accelerator resources. The communication session comprises at least two connections. The at least two connections at least include a first connection having or utilizing a first transport layer and a second connection having or utilizing a second transport layer that is different than the first transport layer. Other embodiments may be disclosed and/or claimed.

Abstract: In a data access method, a processor of a host converts a first descriptor recognized by a virtual machine interface card of the virtual machine into a second descriptor recognized by a physical interface card of the host. The first descriptor includes a virtual machine physical memory address and a data length of accessible data. The physical interface card of the host obtains, based on the second descriptor, a physical address that is in a memory and to which the virtual machine physical memory address is mapped, and accesses the accessible data according to the physical address in the memory.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: A system comprises a plurality of nodes connected in a peer-to-peer network via a communication interface. At least one node of the plurality of nodes comprises a transceiver, at least two connectors, at least one termination resistance module coupled to the transceiver, the at least one termination resistance module providing termination resistance within the node, a first detection circuit coupled to a first connector of the at least two connectors, and a second detection circuit coupled to a second connector of the at least two connectors. The first and second detection circuits are configured to detect that the node is coupled to one or more other nodes in the peer-to-peer network, and automatically adjust the termination resistance based on the detecting.

Abstract: This application provides a data validation method and apparatus, and a network interface card. A first RNIC validates, by determining whether first data and second data are the same, data stored in a first memory, determines that first data in to-be-transmitted target data is correctly stored in the first memory, and notifies a second RNIC by using an acknowledgement ACK character. Reliability of the ACK sent by the first device to the second device is enhanced. The ACK sent by the first device to the second device may further be used to indicate that the first data in the target data is correctly stored in the first memory. In this case, a direct memory access result of RDMA is more reliable for an upper-layer service application.