Abstract: The disclosure relate to testing software for operating an autonomous vehicle. For instance, a first simulation may be run using log data and the software to control a first simulated vehicle. During this, one or more characteristics of the simulated vehicle may be compared with one or more characteristics of a vehicle from the log data. The comparison may be used to determine a divergence point for starting a timer. In addition, a second simulation may be run using the log data and the software to control a second simulated vehicle. The divergence point may be used to determine a handover time to allow the software to take control of the second simulated vehicle. Whether the software is able to continue through the first simulation before the timer expires without a particular type of event occurring and/or the second simulation without the particular type of event occurring is determined.

Abstract: Processing automation scripts used for testing pages includes running the automation scripts using a processor, searching for an element on the page according to locating information in an instruction of the automation scripts, collecting element-related information of the element in response to finding of the element on the page according to the locating information, and associating the collected element-related information of the element with the instruction of the automation scripts. The element-related information associated with the instruction is saved.

Abstract: A method for measuring code coverage of runtime generated code is provided that can be used for unit testing. In some implementations, the method may include performing unit testing of one or more lines of code of an application by at least: executing during runtime the one or more lines of code, generating, from the executed one or more lines of code, additional code including generated code including instructions to increment at least one counter in a map, the map mapping one or more frames to the at least one counter, compiling the generated code, incrementing, each time the compiled generated code is executed during runtime, the at least one counter in the map, and providing the at least one counter to enable verification of the unit testing of the generated code. Related methods and articles of manufacture are also described.

Abstract: Program execution coverage is expanded by selectively capturing inputs and execution state information in a production environment after identifying test insufficiencies in a test environment. A program being tested has a non-covered portion and a covered portion. The non-covered portion includes code which is not exercised by a set of tests with regard to an execution coverage, e.g., path coverage, statement coverage, Boolean condition coverage, etc. A non-covered portion identifier identifies the non-covered portion, e.g., by noting breakpoint misses or static analysis constraint solution computational requirements. A trigger inserter inserts a trigger in the program, at a position which permits capture of data which aids exercise of the non-covered portion. A data capturer captures such execution coverage expansion data (“ECE data”) in response to trigger activation.

Abstract: An application module is read and parsed into a text file to store source code lines included into the implementation of the application module. The text file is analyzed and predicate conditions are identified in one or more of source code lines. Key values associated with a predicate condition from the predicate conditions are determined. Key values are associated with a key field defined for the application module. A plurality of paths of execution of the application module is determined based on the text file analysis and on the determined predicate conditions. A path includes one or more lines from the source code lines corresponding to a sequence of execution steps of the application module. Based on determining key values for the predicate conditions and the plurality of paths, generating test cases corresponding to the path and corresponding predicate conditions.

Abstract: A method and system generates extended patterns from base patterns with an automatic pattern generation engine. The method and system tests the extended patterns with an automatic pattern testing engine. The patterns correspond to configurations for implementing cloud-based applications. The patterns are extendable to make additional extended patterns. Extended patterns carry the characteristics of the patterns from which they were extended. Updating a base pattern with new security measures causes a cascade effect that updates all extended patterns that descend from the base pattern.

Abstract: Data is received that characterizes graphical user interface elements of a software application. Thereafter, labels within the received data are identified. Further, those labels having corresponding input fields are identified. These identified input fields are used to poll a test data repository for test data appropriate for such input fields. Using the test data obtained as part of the polling, a testing script for the software application is executed which injects the test data into the identified input fields. Related apparatus, systems, techniques and articles are also described.

Abstract: First data units can be sampled from a set of data units of a memory component. The first data units can be a subset of the set of data units. An initial data unit is determined from the first data units as a first candidate data unit based on a wear metric associated with the first data units. The wear metric is indicative of a level of physical wear of the first data units. A wear leveling operation can be performed in view of the first candidate data unit.

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

Abstract: A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.

Abstract: Technology is disclosed for dynamically assigning apps to non-volatile memory based on monitoring the apps' usage of memory resources. For a memory system having a high endurance section, such as binary (or single level cell, SLC) memory, and a lower endurance section, such as multi-level cell (MLC) memory, an app, including both the code for executing the app and the associated data payload, may initially be stored in the lower endurance section. The memory system monitors the activity of the app for high levels of activity and, if the app is being frequently written, the memory system notifies the host. In response, the host can request the memory system to move the app or just its associated payload to the high endurance section.

Abstract: A semiconductor device may include a media controller configured to output an address in response to receiving a write request for writing to a nonvolatile memory. The semiconductor device may also include a hot address detector. The hot address detector is configured to store a list including the address output from the media controller and including meta data related to the address, to update the meta data according to the address output from the media controller, to determine whether the address output from the media controller is a hot address, and to adjust a length of the list.

Abstract: A data writing method, a memory control circuit unit and a memory storage device are provided. The method includes: executing a first programming operation to data according to a first RAID ECC rate, programming the data into at least a portion of a plurality of first physical programming units, and generating a first RAID ECC; and executing a second programming operation to the data programmed into at least the portion of the first physical programming units according to a second RAID ECC rate, programming the data into at least a portion of a plurality of second physical programming units, and generating a second RAID ECC, wherein the first RAID ECC rate is different from the second RAID ECC rate.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller electrically connected to the nonvolatile memory. The controller receives, from a host, a write command including a logical block address. The controller obtains a total amount of data written to the nonvolatile memory by the host during a time ranging from a last write to the logical block address to a current write to the logical block address, or time data associated with a time elapsing from the last write to the logical block address to the current write to the logical block address. The controller notifies the host of the total amount of data or the time data as a response to the received write command.

Abstract: A method and a system for accelerating computer data garbage collection (GC) on a non-volatile memory (NVM) computer storage device may include: monitoring, by a processor, a data validity parameter of at least one physical write unit (PWU), where the PWU may include a plurality of physical data pages of the NVM device; sending at least one GC command from the processor to an accelerator associated with the NVM device, based on the monitored data validity parameter; copying, by the accelerator, a plurality of data-objects stored on at least one first PWU, to a read address space comprised within the accelerator; copying valid data-objects from the read address space to a write address space comprised within the accelerator until the amount of data in the write address space exceeds a predefined threshold; and storing, by the accelerator, the data content in at least one second PWU in the NVM media.

Abstract: A method of managing a solid state drive (SSD), comprising: storing a first set of data in a first plurality of non-volatile memory dies, the first plurality of non-volatile memory dies communicatively arranged in one or more first communication channels; storing a second set of data in a second plurality of non-volatile memory dies, the second plurality of non-volatile memory dies communicatively arranged in one or more second communication channels; generating a first set of system data corresponding only to the first set of data; generating a second set of system data corresponding only to the second set of data; and managing the first set of system data corresponding to the first set of data independently of the second set of system data corresponding to the second set of data, wherein the one or more first communication channel and the one or more second communication channel are communicatively coupled to one or more channel controllers, the one or more channel controls are communicatively coupled to a

Abstract: A method of cache hit ratio simulation using a partial data set includes determining a set of sampled addresses, the set of sampled addresses being a subset of all addresses of a storage system of a storage environment. The method further includes using, by a simulation engine, a cache management algorithm to determine a cache hit ratio of the sampled addresses, the cache management algorithm being also used by a cache manager to place a portion of the addresses of the storage system into cache during a runtime operation. The method further includes determining a quantity of memory access operations to frequently accessed addresses in the set of sampled addresses, and correcting, by the simulation engine, the cache hit ratio of the sampled addresses based on the quantity of memory access operations to the frequently accessed addresses in the set of sampled addresses. The simulation also handles sequential operations accurately.

Abstract: A high-bandwidth adaptive cache reduces unnecessary cache accesses by providing a laundry counter indicating whether a given adaptive cache region has any dirty frames to allow write-back without a preparatory adaptive cache read. An optional laundry list allows the preparatory adaptive cache read to also be avoided if the tags of the data being written back match all tags of the data in the adaptive cache that is dirty.

Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.

Abstract: An information processing apparatus includes a first memory and a processor coupled to the first memory. The processor is configured to acquire a first address in the first memory, at which an instruction included in a target program is stored. The processor is configured to simulate access to a second memory, such as a cache memory, corresponding to an access request for access to the first address on a basis of configuration information of the second memory. The processor is configured to generate first information, such as cache profile information, indicating whether the access to the second memory regarding the instruction is a hit or miss. The processor may be configured to acquire a number of cache misses for each of a plurality of pieces of arrangement information, and select a piece of arrangement information where the number of cache misses is smallest.

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

Abstract: In response to receipt by a first coherency domain of a memory access request originating from a master in a second coherency domain and excluding from its scope a third coherency domain, coherence participants in the first coherency domain provide partial responses, and one of the coherence participants speculatively provides, to the master, data from a target memory block. The data includes a memory domain indicator indicating whether the memory block is cached, if at all, only within the first coherency domain. Based on the partial responses a combined response is generated representing a systemwide coherence response to the memory access request. In response to the combined response indicating success and the memory domain indicator indicating that a valid copy of the memory block may be cached outside the first coherence domain, the master discards the speculatively provided data and reissues the memory access request with a larger broadcast scope.

Abstract: A high performance, low power, and cost effective multiple channel cache-system memory system is disclosed.

Abstract: A computer system, comprising first computers, an application operate on each of the first computers; the each of the first computers is coupled to a second computer for providing a storage area; the each of the first computers includes a processor, a memory, a cache device to which a cache area, and a interface; the memory includes a program for realizing an operating system; the operating system includes a cache driver; and a cooperation control module configured to issue a control I/O request for instructing arrangement control; and the cooperation control module generate the control I/O request from a detected I/O request based on a analysis result of the detected I/O request in a case where an issuance of the I/O request from the cache driver is detected; and transfer the control I/O request to an apparatus different from an apparatus of a transfer destination of the detected I/O request.

Abstract: A cache memory for a processor including an arbiter, a tag array and a request queue. The arbiter arbitrates among multiple memory access requests and provides a selected memory access request. The tag array has a first read port receiving the selected memory access request and has a second read port receiving a prefetch request from a prefetcher. The tag array makes a hit or miss determination of whether data requested by the selected memory access request or the prefetch request is stored in a corresponding data array. The request queue has a first write port for receiving the selected memory access request when it misses in the tag array, and has a second write port for receiving the prefetch request when it misses in the tag array. The additional read and write ports provide a separate and independent pipeline path for handing prefetch requests.

Abstract: Embodiments of the present disclosure relate to a controller that includes a monitor to determine an access pattern for a range of memory of a first computer memory device, and a pre-loader to pre-load a second computer memory device with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the subset includes a plurality of cache lines. In some embodiments, the controller includes a specifier and the monitor determines the access pattern based at least in part on one or more configuration elements in the specifier. Other embodiments may be described and/or claimed.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

Abstract: A method and a Memory Availability Managing Module (110) “MAMM” for managing availability of memory pages (130) are disclosed. A disaggregated hardware system (100) comprises sets of memory blades (105, 106, 107) and computing pools (102, 103, 104). The MAMM (110) receives (A010) a message relating to allocation of at least one memory page to at least one operating system (120). The message comprises an indication about availability for said at least one memory page. The MAMM (110) translates (A020) the indication about availability to a set of memory blade parameters, identifying at least one memory blade (105, 106, 107). The MAMM (110) generates (A030) address mapping information for said at least one memory page, including a logical address of said at least one memory page mapped to at least two physical memory addresses of said at least one memory blade (105, 106, 107).

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for data processing are provided. One of the methods includes: obtaining a bytecode compiled from source code comprising one or more input parameters, the source code including an encoding function to encode the one or more input parameters, save the encoded one or more input parameters in a memory segment, and provide a memory location of the memory segment; executing, according to the bytecode, the encoding function to encode the one or more input parameters to obtain the memory location of the memory segment storing the encoded one or more input parameters; and providing the memory location to a function for retrieving and decoding the encoded one or more input parameters to obtain the one or more input parameters.

Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.

Abstract: A mapping table updating method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: calculating a plurality of updated data counts of a plurality of updated logical units in at least one active physical erasing unit respectively according to a physical-logical mapping table; selecting a first updated logical unit from a plurality of updated logical units according to the plurality of updated data counts, and the number of the first updated logical unit is less than the number of the plurality of updated logical units; loading a first logical-physical mapping table corresponding to the first updated logical unit; and updating mapping information in the first logical-physical mapping table according to mapping information of the first updated logical unit in the physical-logical mapping table.

Abstract: Efficiently generating effective address translations for memory management test cases including obtaining a first set of EAs, wherein each EA comprises an effective segment ID and a page, wherein each effective segment ID of each EA in the first set of EAs is mapped to a same first effective segment; obtaining a set of virtual address corresponding to the first set of EAs; translating the first set of EAs by applying a hash function to each virtual address in the set of virtual addresses to obtain a first set of PTEG addresses mapped to a first set of PTEGs; and generating a translation for a second set of EAs to obtain a second set of PTEG addresses mapped to the first set of PTEGs.

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

Abstract: On a computer system having a processor, a single OS and a first instance of a system driver installed and performing system services, method for sharing driver pages among Containers, including instantiating a plurality of Containers that virtualize the OS, wherein the first instance is loaded from an image, and instantiating a second instance of the system driver upon request from Container for system services by: allocating virtual memory pages for the second instance and loading, from the image, the second instance into a physical memory; acquiring virtual addresses of identical pages of the first instance compared to the second instance; mapping the virtual addresses of the identical pages of the second instance to physical pages to which virtual addresses of the corresponding pages of the first instance are mapped, and protecting the physical pages from modification; and releasing physical memory occupied by the identical pages of the second instance.

Abstract: An information processing apparatus includes a first memory, a second memory, and a processor coupled to the first memory and the second memory. The first memory is configured to store data and has a first access speed. The second memory is configured to store data and has a second access speed different from the first access speed. The processor is configured to determine respective storage destinations of first data stored in the first memory and second data stored in the second memory from among the first memory and the second memory based on a first access probability and a first latency of the first data and a second access probability and a second latency of the second data.

Abstract: A computer system generates snapshot backups of a virtual machine by creating a metadata snapshot and a backup snapshot. The computer system identifies a backup request for a virtual machine operating on a host computing system, initiates a backup snapshot of storage devices in use by the virtual machine, generates a metadata snapshot of a configuration of the virtual machine, and maintains the metadata snapshot in a data store.

Abstract: Interface circuitry is provided for a host device, the interface circuitry for controlling data connections between the host device and a peripheral device.

Abstract: Examples of techniques for wireless communication are presented. In some examples, an apparatus comprises a wireless transceiver and a hardware processor configured to perform: receiving, from a host device, a first indication of a host device clock signal, the apparatus and the host device being coupled via a wired interconnect; determining, based on the first indication and a second indication of an endpoint device clock signal, a phase relationship between the host device clock signal and the endpoint device clock signal; determining, based at least on the phase relationship, a first time for transmitting a sensor data request to a peripheral device of a computer; transmitting, using the wireless transceiver, the sensor data request to the peripheral device at the first time; receiving, from the peripheral device, the sensor data; and providing the sensor data to the host device via the wired interconnect as input data to the computer.

Abstract: A peripheral processing device comprises a physical interface for connecting the processing device to a host computing device through a communications protocol. A local controller connected to local memory across an internal bus provides input/output access to data stored on the processing device to the host through a file system API. A neural processor comprises at least one network processing engine for processing a layer of a neural network according to a network configuration. A memory at least temporarily stores network configuration information, input image information, intermediate image information and output information produced by each network processing engine. The local controller is arranged to receive network configuration information through a file system API write command, to receive input image information through a file system API write command; and to write output information to the local memory for retrieval by the host through a file system API read command.

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

Abstract: An inter-process signaling system and method support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

Abstract: Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.

Abstract: A semiconductor apparatus includes first transmitters allocated to a first data byte, and second transmitters allocated to a second data byte, wherein a power supply node of each transmitter allocated to a deactivated byte of the first data byte and the second data byte is coupled with a ground terminal.

Abstract: A data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer. The first switching re-timer is configured to double a link rate per lane and halve the number of lanes, and the second switching re-timer is configured to halve the doubled link rate and double the halved number of lanes.

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node, a second computer node and a control unit. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; (B) transmitting, by the first BMC and to the control unit, a control signal that corresponds to the reset command; and (C) transmitting, by the control unit and to the second BMC, a reset signal that corresponds to the control signal, so as to trigger reset of the second BMC.

Abstract: Embodiments of the present disclosure relate to a computer-implemented method. According to the method, a series of valid control codes for a calibration stage in a channel corresponding to a plurality of calibration cycles are acquired from the calibration logic. The acquired valid control codes are analyzed to obtain changing characteristics for the calibration stage in the channel. The calibration logic for the calibration stage in the channel is adjusted in one or more subsequent calibration cycles based on the changing characteristics.

Abstract: Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.

Abstract: The present disclosure is directed to accelerator circuitry useful in a network applications, such as cloud-based radio access networks. The accelerator circuitry includes interface circuitry that couples the accelerator circuitry to each of a plurality of processor circuits and to system memory circuitry. The accelerator circuitry also includes queue management circuitry, local storage circuitry, direct memory access (DMA) circuitry, and a plurality of accelerator circuits. In operation, the processor circuit communicates a message to the queue management circuitry. The message includes pointer data and prioritized data. The queue management circuitry enqueues the message in one of a plurality of queues. The DMA circuitry receives the message and locates a descriptor at the address designed by the pointer. The DMA circuitry retrieves input data, selects an accelerator circuit, and provides the input data to the selected accelerator circuit.

Abstract: A method of interfacing a memory controller and a memory device in a memory system includes transmitting a control signal between the memory controller and the memory device using a time division multiplexing (TDM) communication process, and transmitting data between the memory controller and the memory device using a serializer/deserializer (SERDES) communication process. Data communication in the memory system is performed via a physical channel and a plurality of virtual channels corresponding to the physical channel.