Abstract: An adaptive gate driver for a driving a power MOSFET to switch is disclosed. The adaptive gate driver includes a load sense circuit to sense a current through the power MOSFET. A controller coupled to the load sense circuit compares the sensed current to a threshold to determine if the load on the power MOSFET is a normal load or a heavy load. Based on the comparison, the controller controls the gate driver to drive the power MOSFET with a first strength level when a normal load determined and at second strength level when a heavy load is determined. The driving strength in the heavy-load condition is lower than the normal-load condition and by lowering the driving strength of the gate driver during the heavy-load condition a voltage across the power MOSFET may be prevented from exceeding a threshold related to a breakdown condition during a switching period.

Abstract: In one embodiment, a control circuit may be configured to form a switching signal to switch a power transistor at a frequency to regulate an output voltage of the power supply to a target value wherein the control circuit is configured to operate in a normal operating mode and a start-up mode and wherein the control circuit is configured to switch the switching signal at a target frequency in response to operating in the normal operating mode. A first circuit may be configured to control the frequency of the switching signal to increase from a first frequency to a second frequency that is less than the target frequency in response to operating in the start-up mode.

Abstract: A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.

Abstract: Each of a P-side IGBT and an N-side IGBT connected in series to implement an arm includes a first gate and a second gate. In each of a drive circuit unit configured to control a voltage of the first gate with respect to a collector of the P-side IGBT, a drive circuit unit configured to control a voltage of the second gate with respect to an emitter of the P-side IGBT, and a drive circuit unit configured to control a voltage of the second gate with respect to a collector of the N-side IGBT, a signal processing circuit and an output circuit are electrically isolated from each other by an isolation structure.

Abstract: Apparatus and methods for reducing charge injection mismatch are provided herein. In certain implementations, an electronic circuit includes one or more switch banks. Each switch bank can include a selection circuit and a plurality of switches that can be controlled using one or more clock signals. The selection circuit can select a first portion of the switches for operation in a first switch group and a second portion of the switches for operation in a second switch group. During a calibration, the electronic circuit's charge injection mismatch can be directly or indirectly observed for different switch configurations of the switch banks. The electronic circuit can be programmed to operate with the selected switch configurations of the switch banks to provide the electronic circuit with small charge injection mismatch.

Abstract: An apparatus comprises multiple power supply switches each including a respective power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) to receive a respective one of multiple power voltages ranked incrementally from a lowest priority to a highest priority, and multiple control modules each coupled to, and configured to control, a respective one of the power MOSFETs, each control module to receive all of the power voltages having higher priorities than the power voltage received at the respective power MOSFET controlled by that control module, each control module to control the respective power MOSFET so as to turn off the respective power MOSFET if any of the higher priority power voltages are present, or permit the respective power MOSFET to turn on responsive to the respective power voltage if all of the higher priority power voltages are absent.

Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.

Abstract: According to one embodiment, a semiconductor device includes: a boost circuit configured to apply a first voltage to a gate terminal; a first switching element, a first resistor, and a second resistor that are coupled in parallel between the gate terminal and a source terminal; a second switching element coupled in series with the second resistor between the gate terminal and the source terminal; a switching element control circuit configured to switch, in response to a change of a voltage from the first voltage applied from the boost circuit to the gate terminal to being indeterminate, the first switching element to on state after switching the second switching element to on state. A resistance value of the second resistor is smaller than a resistance value of the first resistor.

Abstract: A power conversion apparatus includes positive-side and negative-side switching elements, positive-side and negative-side gate drive circuits, and a gate signal controller. The positive-side switching element is disposed between a positive-side direct-current bus and an output node. The negative-side switching element is disposed between a negative-side direct-current bus and the output node. The positive-side and negative-side gate drive circuit are configured to turn on and off the positive-side and negative-side switching elements, respectively. The gate signal controller is configured to transmit to the positive-side and negative-side gate drive circuits gate signals to instruct turning on and off the positive-side and negative-side switching elements.

Abstract: An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.

Abstract: Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.

Abstract: A frequency-agile phase modulator with glitch-free multiplexer in CMOS process technologies for applications including wireless communications, radar, automotive radar, etc. Examples herein offer a novel phase modulator architecture that, when combined with either a wideband power amplifier or multiple narrowband amplifiers, allows for a single transmitter to transmit radar, communication, telemetry, or other similar waveforms across multiple frequency bands. The embodiments herein allow one transmitter to cover a very large operating frequency range, resulting in a decrease in size, weight, power consumption, and cost for future “small” platform systems. In an embodiment, the phase modulator circuit includes a reconfigurable delay-locked loop (DLL) circuit that is configured to receive a radio frequency (RF) input signal (RFin) and a configuration signal.

Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

Abstract: A communication technique for converging internet of everything (IoT) technology with a 5th generation (5G) communication system for supporting a higher data transfer rate beyond a 4G system is provided. The communication technique can be applied to intelligent services, based on 5G communication technology and IoT-related technology. In an embodiment, an electronic device includes a first processor configured to output a first signal for generating a first frequency signal, a second processor configured to output a second signal for generating a second frequency signal, a first radio frequency (RF) chip configured to output the first frequency signal, based on the first signal received from the first processor and a baseband signal, and a second RF chip configured to output the second frequency signal, based on the second signal received from the second processor and the first frequency signal outputted from the first RF chip.

Abstract: Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

Abstract: An offset voltage VOFST is compensated in a digital to analog (DA) convertor using a switched-capacitor circuit, including an input circuit, a first differential amplifier, and an offset cancel circuit comprising a second differential amplifier, in a sampling period, when the second feedback circuit is short, an output voltage of the first differential amplifier is input to a first end of a first capacitor, the offset cancel circuit feeds back a reference voltage to an inverting input terminal of the second differential amplifier and a second end of the first capacitor from an output of the second differential amplifier, in a holding period, when the second feedback circuit is not short, the offset cancel circuit inputs a differential voltage between the reference voltage and the output voltage of the first differential amplifier into an inverting input terminal of the first differential amplifier via a second capacitor.

Abstract: Comparator input noise or offset suppression can include an error detector circuit that can operate in a feedback loop, such as during an autozero phase. The error detector circuit can include a time-varying filter response to improve accuracy and convergence time. The comparator can be used in a successive approximation routine (SAR) or other analog-to-digital converter (ADC) circuit, such as to control a digital-to-analog converter (DAC), such as can be used to adjust a tuning circuit within the comparator to compensate for noise or offset. The DAC can be combined with a DAC used for carrying out SAR bit-trials or bit decisions.

Abstract: Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.

Abstract: An analog-to-digital converter includes a cycle processing unit and a control unit. The cycle processing unit converts an analog input signal into a digital signal having a plurality of bits by performing a plurality of cycle processing on the analog input signal to acquire values of each bit in order from a higher-order bit to a lower-order bit. The control unit controls the cycle processing unit such that a period of the cycle processing is shortened according to a cycled number of the cycle processing.

Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

Abstract: A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.

Abstract: A computer system includes a hardware controller and a host system. The hardware controller includes an accelerator to encode a data stream requested by an application based on a version of the accelerator. The host system executes a compression library linked to the application. The compression library operates according to one or more behavior characteristics to execute a compression algorithm that compresses the encoded data provided by the hardware controller. The behavior characteristics of the compression library is actively changed based on the version of the accelerator.

Abstract: Described is an apparatus and method for data compression using compressive sensing in a wearable device. Described is also a machine-readable storage media having instruction stored thereon, that when executed, cause one or more processors to perform an operation comprising: receive an input signal from a sensor; convert the input signal to a digital stream; and symmetrically pad on either ends of the digital stream with a portion of the digital stream to form a padded digital stream.

Abstract: A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.

Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predictive information, and therefore can demodulate/decode signals more quickly. Earlier completion of demodulation/decoding of signals can terminate the operation earlier and thereby achieve the effect of power savings. The convolutional code decoder performs decoding according to received data and auxiliary data to obtain target data, and includes a first error detection data generation circuit, a channel coding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit, and a second Viterbi decoding circuit.

Abstract: A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed.

Abstract: A radio frequency transmitter includes a digital-to-analog converter (DAC), a load circuit, and a modulator circuit. The load circuit is coupled to an output of the DAC. The modulator circuit is coupled to the DAC and the load circuit. The modulator circuit includes a driver circuit configured to provide a bias voltage to the load circuit, and an amplifier configured to receive an output of the DAC biased by an output of the load circuit.

Abstract: Methods, systems, and devices for wireless communications are described. A device, which may be otherwise known as user equipment (UE), may support spurious emission attenuation. A device may determine, based on a first frequency scan on a radio frequency (RF) spectrum band, that a signal strength of a signal at a frequency of the RF spectrum band satisfies a threshold. The device may perform, based on the first frequency scan on the RF spectrum band, a second frequency scan on the RF spectrum band to determine whether the signal strength of the signal at the frequency of the RF spectrum band satisfies the threshold during the second frequency scan. Subsequently, the device may determine that the signal is a spurious emission at the frequency based on the signal strength of the signal, and configure a notch filter for mitigating the spurious emission at the frequency.

Abstract: A method for operating a communications system includes transmitting a preamble sequence including a plurality of tones. Each tone of the plurality of tones has a first characteristic and a second characteristic. The first characteristic of each of the tones of the plurality of tones has a predetermined relative relationship to the first characteristic of each of the other tones of the plurality of tones and the second characteristic of each of the tones of the plurality of tones has a predetermined relative relationship to the second characteristic of each of the other tones of the plurality of tones. The first and second characteristics may include relative power and relative phase.

Abstract: Described is a multi-input cognitive signal processor (CSP) for estimating time-difference-of-arrival (TDOA) of incoming signals. The multi-input CSP receives a mixture of input signals from an antenna a and an antenna b. The multi-input CSP predicts and temporally de-noises input signals a and b received from antennas a and b, respectively, using an input corresponding to each input signal, resulting in de-noised state vectors for input signals a and b. Using the de-noised state vectors for input signals a and b, cross-predicting and spatially de-noising the other of the de-noised state vectors for input signals a and b. TDOA values of signal pulses to each of antennas a and b are estimated and converted into estimated angles of arrival for each signal pulse.

Abstract: Provided is an electronic device includes an interface for connection to an external device; and a processor electrically connected to the interface, wherein the at least one processor is configured to: set a first radio frequency (RF) signal port of a first chipset to operate in RF signal transmission mode, and set a second RF signal port of a second chipset to operate in RF signal reception mode; obtain an error of transmission performance of the first RF signal port based on a comparison between a designated transmission reference that is input to the first RF signal port and a characteristic of a first intermediate frequency (IF) signal that is output via the second RF signal port; obtain a first compensation value to enable the transmission performance of the first RF signal port to converge to the transmission reference, on the basis of the error of the transmission performance; and store at least one of the error of the transmission performance and the first compensation value in the first chipset via

Abstract: A mobile terminal includes a terminal body, a metal case forming an appearance of the terminal body and including a side region and a second region integrally formed with the side region and supporting the inside of the terminal body, and a rear molding part formed in a region of the metal caser. The rear molding part includes a first molding region formed to have a closed loop shape along an inner surface of the side region and a second molding region extending from the first molding region and forming a receiving space for receiving at least one electronic component. The side region includes a plurality of opening holes, and the first molding region is formed to cover the plurality of opening holes.

Abstract: A method of securing a portable electronic device with a touchscreen interface for use in a sterile environment comprises providing a sterilizable enclosure and providing a transfer device. The transfer device has an upper wall and a lower wall defining a passage. The enclosure provides a frame and a base movable between open and closed positions. The enclosure is held open with the transfer device. The electronic device is inserted through the passage and into the enclosure. One of the transfer device and the enclosure is moved away from the other.

Abstract: A wireless communication system with scalable diversity and multi-transceiver diversity deployment is disclosed. An example communication system includes a first wireless transceiver, having a first bandwidth and a first center frequency, a second transceiver, having a second bandwidth and a second center frequency, and a processor. The processor is configured to operate the wireless communication system in a first mode when a difference between the first center frequency and the second center frequency is greater than or equal to half of the first bandwidth plus the second bandwidth. The processor is also configured to operate the wireless communication system in a second mode when a difference between the first center frequency and the second center frequency is less than half of the first bandwidth plus the second bandwidth.

Abstract: An antenna switching system comprises an antenna switch module comprising a switch network that includes RF switches connectable to signal receive and transmit paths, and a switch control unit. First and second receiver/transmitter units are connected to the antenna switch module. A single antenna is connected to the receiver/transmitter units through the antenna switch module. The switch control unit receives mutual suppression signal pulses routed from the receiver/transmitter units. The mutual suppression signal pulses are decoded by the switch control unit to generate control signals to open and close the RF switches as needed for a signal transmit operation mode or a signal receive operation mode. The signal transmit operation mode comprises a first transmit mode in which either of the receiver/transmitter units transmits RF signals along the transmit path, or a second transmit mode in which both of the receiver/transmitter units transmit RF signals along the transmit path.

Abstract: An apparatus for removing a magnetic interference signal according to a use of a full duplex radio (FDR) scheme comprises a plurality of Rat race couplers; and a plurality of antenna pairs in which two antennas are paired, wherein each of the plurality of antenna pairs are disposed at equal intervals from each other, a first output port between two output ports of a first Rat race coupler from among the plurality of Rat race couplers is connected to a first antenna of a first antenna pair and a second output port is connected to a second antenna of the first antenna pair, a third output port between two output ports of a second Rat race coupler from among the plurality of Rat race couplers is connected to a third antenna of a second antenna pair, and a fourth output port is connected to a fourth antenna of the second antenna pair.

Abstract: A transmit receive switch (TRSW) system is disclosed. The system has a transmission line, a transformer based matching network, a shunt switch, an amplifier and circuitry. The transmission line is connected to an antenna port. The transformer based matching network is connected to the transmission line and has a first coil and a second coil, wherein the second coil is connected to the transmission line. The amplifier can be configured as a shunt switch when inactive. The shunt switch, including the amplifier configured as the shunt switch, can be connected to the first coil of the transformer based matching network. The circuitry is configured to cause the shunt switch to be ON during an inactive mode and create a short across the first coil. Combined, the length of transmission line needed to complete the impedance transformation is reduced, thereby lowering the overall insertion loss of the transmit/receive switch.

Abstract: An inductor circuit includes first inductive circuit, second inductive circuit, and third inductive circuit. First inductive circuit at receiver side has a first end coupled to a first port of an antenna and a second end coupled to an input port of a receiving circuit. Second inductive circuit at transmitter side has a first end and a second end respectively coupled to output ports of a power amplifier. Third inductive circuit at antenna side has a first end coupled to a first port of the antenna and having a second end. Second inductive circuit and the third inductive circuit are disposed on an outer ring to form a ring shape and the third inductive circuit is disposed on an inner ring within the outer ring to form a spiral shape. Third inductive circuit is disposed between the second inductive circuit and the first inductive circuit.

Abstract: This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.

Abstract: A spread spectrum based audio frequency communication system at least includes a transmitting apparatus. The transmitting apparatus includes a first dot-product module, a summation module, a transmitting modulation module, a mixture module, a digital-to-analog converter, and a transmitter. The first dot-product module is configured to perform a dot-product of a first data and a first pseudo-noise code, and derive a first spreading data. The summation module is configured to sum up the first spreading data and a second spreading data to form a summed data. The transmitting modulation module is configured to vary a carrier signal with the summed data to form a modulated signal. The mixture module is configured to mix the modulated signal and an acoustic signal up to form a mixed signal. The digital-to-analog converter is configured to convert the mixed signal into acoustic waves. The transmitter transmits the acoustic waves.

Abstract: A system and method for transmitting a digital signal comprising includes a random number generator for generating a pseudorandom code. A scheduler stores a plurality of signal sequences each matching a set of bandwidth-time products and center frequencies with a stored code. The scheduler selects a signal sequence by matching the pseudorandom code with one of the stored codes. The scheduler selects a bandwidth-time product and center frequency based on the selected signal sequence. A baseband processing unit generates the digital signal based on a selected bandwidth-time product and center frequency. A front end processing and beamforming unit broadcasts the digital signal.

Abstract: Echo cancellation may be provided. First, a feedback signal corresponding to a plurality of downstream paths may be received. Next, during an upstream silence period, a sample of a combination upstream signal may be received comprising a combination of upstream signals from a plurality of upstream paths. An echo correcting signal may then be created using the received feedback signal and the received sample of the combination upstream signal. Downstream echoes may be cancel from the combination upstream signal based on the created echo correcting signal.

Abstract: Aspects of the subject disclosure may include, a system that guides electromagnetic waves that propagate along a transmission medium without requiring an electrical return path, and at least reduces radiation on an outer surface of a structure reducing a flow of an electrical current from an inner surface of the structure to the outer surface of the structure. Other embodiments are disclosed.

Abstract: In a powerline communications (PLC) network having a first node and at least a second node on a PLC channel utilizing a band including a plurality of tones, based on at least one channel quality indicator (CQI), the first node allocates for a tone map response payload only a single (1) power control bit for each of a plurality of subbands having two or more tones. The power control bit indicates a first power state or a second power state. The first node transmits a frame including the tone map response payload to the second node. The second node transmits a frame having boosted signal power for the tones in the subbands which have the first power state compared to a lower signal power for the tones in the subbands which have the second power state.

Abstract: The present invention relates to a device (700a, 700b, 700c) for wireless transmission of data and/or power between the device and another device of a system, in particular of a patient monitoring system. To meet stringent relative time errors at low complexity the device comprises a connector (701) comprising a data transmission unit (703) and a magnetic coupling unit (702, 704) for transmitting power to and/or receiving power. A detection unit (705) detects coupling of a counterpart connector of another device of the system with the connector (701).