Abstract: A display substrate and a method of manufacturing the same, and a display panel are provided. The display substrate includes: a base substrate, and a first electrode, a first auxiliary electrode, a boss, a pixel definition layer, an organic functional layer and a second electrode provided on the base substrate. The first auxiliary electrode includes a first conductive connection part contacting a side surface of the boss; the pixel definition layer is provided with a pixel accommodating hole and a slot; the organic functional layer is electrically connected with the first electrode through the pixel accommodating hole; and the second electrode is electrically connected with the first conductive connection part through the slot, so that the second electrode is connected with the first auxiliary electrode in parallel.

Abstract: A method of fabricating an integrated circuit includes applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer. The method also includes exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer. The photoresist exposed layer includes a thick photoresist pattern in a first region, a thin photoresist pattern in a second region where a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern, and a gap region between the thick photoresist pattern and the thin photoresist pattern.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

Abstract: A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.

Abstract: Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a second mask layer are formed on each fin. A spacer layer is formed on the source/drain region and between each fin, and a dielectric layer is formed on the spacer layer and along an exterior of each fin. A plurality of gate metal portions is created each having a thickness about equal to a target thickness. The first mask layer and an exposed portion of the dielectric layer are removed from each fin. An interlayer dielectric is deposited on the semiconductor structure. Portions of the interlayer dielectric and the gate metal are removed to a top of the second mask layer. The gate metal portions are each recessed to substantially the same depth.

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

Abstract: A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

Abstract: It is assumed that a defect satisfying relations of Formula 1 and Formula 2 is a first defect, where an off angle is ?. It is assumed that a defect having an elongated shape when viewed in a direction perpendicular to the second main surface, and satisfying relations of Formula 3 and Formula 4 is a second defect. A value obtained by dividing the number of the second defect by the sum of the number of the first defect and the number of the second defect is greater than 0.5.

Abstract: Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.

Abstract: A method for manufacturing a super-junction MOSFET entails forming a recessed shield electrode in a trench in a semiconductor layer of a substrate, the trench being lined with a first oxide layer. When the electrically conductive material forming the shield electrode is removed to recess the shield electrode, the first oxide layer on sidewalls of the trench is exposed. Removal of the first oxide layer from the sidewalls and from shield sidewalls of the electrode produces openings at a top part of the shield sidewalls. A second oxide layer is formed over the shield electrode and fills the openings. Part of the second oxide layer is removed to expose a top surface of the shield electrode. A gate dielectric is formed over the top surface of the shield electrode and conductive material is deposited over the gate dielectric in the trench to form a gate electrode of the MOSFET.

Abstract: An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer.

Abstract: An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

Abstract: A method includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench and forming a hard mask (HM) layer in a space in the gate trench and surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench and depositing a metal layer in the gate trench. The metal layer is in physical contact with a sidewall surface of the gate WF layer that is deposited before the HM layer is formed.

Abstract: Embodiments of the invention are directed to configurations of semiconductor devices. A non-limiting example configuration includes a plurality of first transistors formed over a performance region of a major surface of a substrate. Each of the plurality of first transistors includes a first channel fin structure and a first gate structure along at least a portion of a sidewall surface of the first channel fin structure. The first gate structure includes a first gate thickness dimension. A plurality of second transistors is formed over a density region of the major surface of the substrate. Each of the plurality of second transistors includes a second channel fin structure and a second gate structure along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate, a display panel, and a display device are disclosed. The present disclosure is directed to the field of display technologies. The thin film transistor comprises a drain electrode and a source electrode. At least one of the drain electrode and the source electrode are an yttrium-doped first metal film, and a surface of the first metal film is yttrium-copper complex oxide formed by annealing.

Abstract: It is an object of the present invention to easily perform an electric characteristic test for ensuring quality of a semiconductor device on an electrode pattern defect or deficiency. A method of manufacturing a semiconductor device according to the present invention performs, a first etching having a higher selected ratio with respect to a semiconductor material of a first semiconductor layer than a material of a first electrode film over the first electrode film, and removes a region in the first semiconductor layer below a pattern defective part or a deficiency part of the first electrode film at least partially to form an electrode film in the pattern defective part or the deficiency part of the first electrode film.

Abstract: A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.

Abstract: A vertical tunneling field effect transistor is provided and includes: a semiconductor substrate; a first doped layer on the semiconductor substrate; vertical nanowires on the first doped layer; a second doped layer on a top of each vertical nanowire; an interlayer dielectric layer on the first doped layer, including a cavity between the adjacent vertical nanowires through the interlayer dielectric layer and exposing sidewalls of the adjacent vertical nanowires; a high-K gate dielectric layer in sidewalls and a bottom of each cavity; and a gate electrode layer on the high-K gate dielectric layer to fill each cavity.

Abstract: An electronic device can include an enhancement-mode high electron mobility transistor (HEMT) that includes a source electrode; a drain electrode; and a gate. In an embodiment, the gate can correspond to spaced-apart gate electrodes and a space disposed between the spaced-apart gate electrodes, wherein the first space has a width configured such that, a continuous depletion region forms across all of the width of the first space. In another embodiment, the gate can be a gate electrode having a nonuniform thickness along a line in a gate width direction. In another aspect, a method of using the electronic device can include, during a transient period when the HEMT is in an off-state, flowing current from the drain electrode to the source electrode when Vds>?Vth+Vgs.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate structure over a substrate, forming a disposable spacer on a sidewall of the gate structure, and forming a source region and a drain region at opposite sides of the gate structure. The method also includes depositing an interlayer dielectric layer around the disposable spacer, and forming a first hard mask on the interlayer dielectric layer. The method further includes removing an upper portion of the gate structure, and removing the disposable spacer to form a trench between the gate structure and the interlayer dielectric layer. In addition, the method includes sealing the trench to form an air-gap spacer, and forming a second hard mask on the gate structure.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall

Abstract: In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

Abstract: A semiconductor device having a first surface formed at a first height and a second surface formed at a second height on a semiconductor substrate includes: a base region formed in the semiconductor substrate; a trench formed from the first surface and the second surface into the semiconductor substrate; a gate insulating film covering an inner side of the trench; a gate electrode embedded to a third height; an insulating film formed on the gate electrode; a first region which has the first surface and in which a base contact region is formed; and a second region which has the second surface and in which a source region is formed, the first region and the second region being alternately arranged in the trench extension direction to prevent a reduction in channel formation density.

Abstract: A semiconductor circuit of an embodiment includes semiconductor device and a control circuit. The semiconductor device includes a semiconductor layer that has a first region of a first-conductivity type, a second region of a second-conductivity type, a third region of the first-conductivity type, fourth region of the second-conductivity type, first and second trench, first and second gate electrode, a first gate insulating film in contact with the fourth region, and a second gate insulating film spaced away from the fourth region. The semiconductor device includes a first gate electrode pad connected to the first gate electrode, and a second gate electrode pad connected to the second gate electrode. Prior to changing a first gate voltage from a turn-ON voltage to a turn-OFF voltage, a second gate voltage changed from a first voltage to a second voltage. The second voltage is a negative voltage when the first-conductivity type is p-type.

Abstract: A bidirectional switch includes a semiconductor element and a substrate potential stabilizer which stabilizes a substrate potential of a semiconductor element. The substrate potential stabilizer includes a first switch element and a second switch element. Both the first switch element and the second switch element are on when the semiconductor element is on.

Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.

Abstract: High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.

Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract: Disclosed is a transistor device with at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, and a gate pad arranged on top of the semiconductor body and electrically connected to the gate runner. The gate runner includes a first metal line, a second metal line on top of the first metal line, a first gate runner section, and at least one second gate runner section. The at least one second gate runner section is arranged between the first gate runner section and the gate pad. A cross sectional area of the second metal line in the at least one second gate runner section is less than 50% of the cross sectional area of the second metal line in the first gate runner section.

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

Abstract: In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.

Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

Abstract: A device includes a semiconductor substrate, an isolation structure, and an epitaxial fin portion. The semiconductor substrate has an implanted region. The implanted region has a bottom fin portion thereon, in which a depth of the implanted region is smaller than a thickness of the semiconductor substrate. The isolation structure surrounds the bottom fin portion. The epitaxial fin portion is disposed over a top surface of the bottom fin portion, in which the implanted region of the semiconductor substrate includes oxygen and has an oxygen concentration lower than about 1·E+19 atoms/cm3.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a work function layer and a gate dielectric layer, and tops of the work function layer and the gate dielectric layer are at different height levels. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack.

Abstract: Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions.

Abstract: To provide a highly reliable semiconductor device that is suitable for miniaturization and higher density. A semiconductor device includes a first electrode including a protruding portion, a first insulator over the protruding portion, a second insulator covering the first electrode and the first insulator, and a second electrode over the second insulator. The second electrode includes a first region which overlaps with the first electrode with the first insulator and the second insulator provided therebetween and a second region which overlaps with the first electrode with the second insulator provided therebetween. The peripheral portion of the second electrode is provided in the first region.