Abstract: An audio sharing system is configured to operate in at least two modes of operation. In a private mode, the audio sharing system outputs sound only to a user and may isolate the user from the surrounding acoustic environment. In a public mode of operation, the audio sharing system broadcasts sound to the user and to any other listeners in proximity to the user, thereby sharing sound in a social manner. The audio sharing system may also operate in other modes of operation that allow the selective sharing of sounds.

Abstract: Techniques for switching between different playback modes are described herein. The disclosed techniques include detecting a state of playing a content item using Dynamic Adaptive Streaming over HTTP (DASH); determining whether there is a need of switching between a first playback mode and a second playback mode based on the detected state of playing the content item; determining a segment number of a segment among the plurality of segments currently being played based on a timestamp of the segment in response to determining that there is the need of switching between the first playback mode and the second playback mode; obtaining content of the content item based at least in part on the segment number and a playback mode to be switched to; and playing the content item in a switched playback mode.

Abstract: A method of and system for presentencing a user interface for the visually impaired is carried by dividing a user interface area of a user interface into a plurality of sections, mapping a different audible tone to each one of the plurality of sections, associating each one of the plurality of sections with a category, displaying a pane in one section of the plurality of sections, the pane having information about the category associated with the one section, receiving a first touch gesture on the pane, outputting a first audio signal having an audible tone mapped to the section, and depending on a type of the first touch gesture, outputting speech data for at least some of the information, the some of the information depending on a duration and a direction of the first touch gesture.

Abstract: A printing system includes a server system that receives instruction data based on a voice instruction concerning printing accepted by a voice control device, transmits message data based on the received instruction data, and specifies content data. If the instruction data includes information indicating a first content type, message data to inquire about a content setting item is transmitted, and if the instruction data includes information indicating a second content type different from the first content type, the message data to inquire about the content setting item is not transmitted. The content data of the first content type is specified based on instruction data received in a case where the voice instruction concerning the content setting item of the first content type is accepted, and the printing apparatus executes printing based on print data generated based on the specified content data of the first content type.

Abstract: The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion thereof, a fixed-point or floating-point multiplication operation or a portion thereof, a fixed-point or floating-point multiply-add operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers or a Radix-2 Butterfly circuit, just to name a few.

Abstract: A mechanism is provided in a data processing system having a processor and a memory. The memory comprises instructions which are executed by the processor to cause the processor to implement a graphical editor for managing L-shaped swim lanes in a graphical view of an application process. The graphical editor receives a data serialization file representing a process flow of a software application. The graphical editor renders each synchronous node in the process flow in the graphical view of the application process. A swim lane rendering engine executing within the graphical editor creates an L-shaped swim lane for each asynchronous node in the process flow in the graphical view of the application process. The graphical editor presents the graphical view of the application process via an output device.

Abstract: The programming notebook system, methods, and user interfaces described herein provide software developers with enhanced tools by which a programming notebook workflow and session history associated with code cells in a programming notebook may be tracked and maintained. As a developer progresses through a development workflow, the developer can select an option to save a program code card representing some or all of the program code cell inputs. A card editor user interface may present an aggregated listing of all program code the developer has provided across multiple code cells during the current session which the developer can edit, refine, and/or comment. The card editor may also allow the developer to add associated user interface code to display a UI component associated with the program code card, and allow the developer to add a description and tags for the card so that the card can be searched for and reused.

Abstract: Described is a mechanism that provides the ability to reuse a portion of visual programming logic within an automation building tool. The programming logic may be represented as a directed acyclic graph (DAG) such that the nodes of the graph correspond to various operations and the edges of the graph correspond to the logic flow of the program. The mechanism may provide a new capability to reuse portions of the visual programming logic while adhering to the requirements of a DAG structure. For example, a user may copy a valid substructure of visual programming logic upon a validation the programming logic may be inserted into another portion of the DAG. Accordingly, the mechanism provides an efficient and user-friendly mechanism to reuse a portion of visual programming logic within an automation building tool.

Abstract: Techniques are disclosed for automating application development from requirements information for the application. The requirements information may comprise mockup images of GUI screens for the application, text information, and other information. A model is generated based upon the requirements information. The generated model can then subsequently be used to generate one or more implementations of the application. Generation of the model includes processing the requirements information to identify one or more data objects to be mapped or associated with one or more GUI screens of the application, and further determining, for a particular data object mapped to a particular GUI screen, mappings between one or more components of the particular screen to one or more components of the particular data object. The model stores information about the look-and-feel of the GUI screens and about mappings between data objects to screens and screen components to data object components.

Abstract: A system for software application development comprises at least one processor configured to receive a declarative XML file defining the user interface and the database structure in one integrated file. The processor generates a database schema, user interface, API definition, PDF reports, data export/import using excel. Additionally, the processor automatically enables our unified native mobile application supporting an offline mode. The processor can render any number of extensible formats, including HTML, JSON, XML, and XML schema. On receiving a request, the processor dynamically generates output from the declarative XML file enabling hot and real-time deployment.

Abstract: A method of increasing a speed of operation of a computer via a metadata-based business rule interpreter. The method includes receiving, at a processor, user input defining a business rule. The method also includes translating, by the processor, the user input into a domain-specific language entirely consisting of metadata objects, wherein a translated syntax is formed, the translated syntax being an abstract syntax tree structure consisting of only the metadata objects. The method also includes executing, by the processor, an abstract syntax tree interpreter and taking as input into the abstract syntax tree interpreter the translated syntax. A compiler operation to generate computer code for implementing the business rule is avoided. Executing the abstract syntax tree interpreter produces a result in a browser without using executable code to achieve the result.

Abstract: Computer technology facilitating optimization of a container image is provided. In one example, a computer-implemented method includes: analyzing a source container image to obtain a content of the source container image and building an initial target container image using a set of base image layers based on the content of the source container image. The computer-implemented method also includes determining content difference between the initial target container image and the source container image, and building a final target container image based on the initial target container image and the content difference.

Abstract: If a device driver is simply installed in the same manner for any network environment, there is a possibility that the device driver is installed in a manner improper for a particular network environment. To avoid the above problem, an information processing apparatus selects an optimum installation mode according to property information of the information processing apparatus and property information of an image forming apparatus.

Abstract: An information processing device transmits a downloading request of the installer of the application program to a download server. The downloading request contains first information identifying a model of the particular device. The download server stores second information indicating a transmission source of the downloading request together with the first information in an associated manner in a memory, and transmits the installer to the device indicated by the second information. Thereafter, the information processing device transmits a transmission request for the first information to the download server. The download server searches the memory for the second information coinciding with a transmission source of the transmission request, and transmits the first information associated with the searched second information to the device indicated by the third information.

Abstract: A system and method are described for performing service-initiated updates to IoT devices.

Abstract: Examples described herein are directed to systems and methods for updating software. An update system may generate a first Domain Name System (DNS) record comprising first version data indicating a version of an update to the software. The update system may send the DNS record to a DNS server with an indication of a domain name associated with the software.

Abstract: A system for distributing a basic input output system (BIOS), comprising a BIOS settings system configured to receive BIOS settings data, a BIOS binary system configured to receive BIOS binary code, a processor configured to load BIOS firmware from a memory and a code packager coupled to the memory, the code packager configured to combine the BIOS settings data and the BIOS binary code, to generate the BIOS firmware and to store the BIOS firmware in the memory.

Abstract: In one embodiment, a system for managing a virtualization environment comprises a plurality of host machines, one or more virtual disks comprising a plurality of storage devices, a virtualized file server (VFS) comprising a plurality of file server virtual machines (FSVMs), wherein each of the FSVMs is running on one of the host machines and conducts I/O transactions with the one or more virtual disks, and a virtualized file server backup system configured to back up data stored in a VFS located a cluster of host machines to an object store, and retrieve the backed-up data as needed to restore the data in the VFS. The object store may be located in a public cloud. The object store may include a low-cost storage medium within the cluster. An FSVM of the VFS may provide an object store interface to low-cost storage media.

Abstract: A system and computer-implemented method for providing a load-balanced server architecture to end users and allowing software on the server architecture to be updated without downtime during a transition to the new software version. Run-time errors due to incompatibilities between datatypes, interfaces, deserialization methods, and classes loaded by class loaders in object oriented server software may be avoided by using the system to track a software version used in association with a particular task. By routing requests related to a particular task to a particular server running the same software version, compatibility is maintained and efforts to migrate data across software servers or add code to handle cross-version compatibility are unnecessary.

Abstract: Approaches presented herein enable dynamically updating, based on a status of one or more Internet of Things (IoT) devices in an IoT network, a security setting of an IoT device controller and/or at least one of the one or more IoT devices. A status of each of a plurality of IoT devices in the IoT network is monitored. In response to the monitoring of at least one status among the plurality of IoT devices, an event requiring a security setting update is identified. The security setting update is then dynamically applied.

Abstract: A method including altering the configuration of a system including a processor, firmware storage and a scratchpad from a first configuration in which a first version of firmware enabling a first plurality of system operations is run by the processor, into a second configuration in which a second version of firmware enabling a second plurality of system operations is run by the processor, the altering including: A) re-configuring the system from the first configuration into an intermediate configuration in which the processor continues to run the first version of the firmware, B) while the system is in the intermediate configuration, disallowing at least one of the first plurality of operations, C) re-configuring the system from the intermediate configuration to the second configuration, and D) while the system is in the second configuration, allowing the second plurality of operations. Related apparatus and methods are also provided.

Abstract: Examples described herein include systems and methods for efficiently and effectively managing upgrades to an SDDC. More specifically, examples described herein relate to allowing various upgrade paths that can upgrade an SDDC directly to a desired version, without the need for intermediate upgrades. The upgrades can be selected by a user through a graphical user interface (“GUI”) described herein. The examples further describe a version-compliance configuration matrix that identifies various acceptable combinations of software components and versions. The examples also describe a process for providing a customized upgrade package suited to a particular customer or user. Additional examples describe a mechanism for retracting and correcting bad patches or upgrades after they have been released.

Abstract: Disclosed embodiments relate to generating an update package for updating software on an Electronic Control Unit (ECU) in a vehicle. Operations may include accessing a plurality of attributes of a software update to be stored on the ECU in the vehicle; accessing a corresponding plurality of attributes of current software stored on the ECU in the vehicle; comparing the plurality of attributes with the corresponding plurality of attributes; generating a delta file representing differences between the plurality of attributes and the corresponding plurality of attributes determined in the comparison; and providing the delta file to the ECU, wherein the delta file is configured to be processed by startup code in the ECU that enables the delta file to execute in the ECU in the vehicle.

Abstract: Portable packages containing encodings of processes are applied to software stacks. The packages are portable and distinct from the software stacks. The packages may be in the form of declarative code for configuring the software stack and can be plugged into the software stack to allow the technology stack to play the packages, thereby configuring the stacks to be capable of automating the processes encoded by the packages. An application or software component can be provided to read a package and apply parts thereof to appropriate corresponding software stack components.

Abstract: A software model specification for a software package can be associated with representation of a software downgrade definition. The software model specification can include a publisher of the software package, an application title of the software package, and the version of the software package. One or more entitlements for the software package can be obtained. Based on the software downgrade definition being associated with the software model specification, the software downgrade definition can be associated with the entitlement(s). Compliance of the installations of the software package with the entitlement(s) can be calculated, where the software downgrade definition can cause each of the entitlement(s) to be applicable to the installations of the version of the software package or one or more earlier versions of the software package.

Abstract: Systems, methods, and apparatuses are described for analyzing differences in program dependencies, such as libraries. Code of a computer program may be dependent on a first version of a library. The first version of the library may comprise one or more first functions. Based on the first version of the library, a tree model representing the first version of the library and corresponding functions that the library comprises may be generated. A second version of the library may be determined. The one or more first functions of the first version of the library may be compared to one or more second functions of the second version of the library. The differences may be output by, e.g., displaying the differences using a modified tree model based on the generated tree model, and/or code of the program may be updated.

Abstract: A device may perform a static analysis of a codebase associated with a software application to determine a structure of the codebase and one or more metrics associated with the codebase. The device may generate a structured format of the codebase based on the structure of the codebase. The device may generate a domain specific language format of the codebase based on the structured format of the codebase and the one or more metrics associated with the codebase. The device may generate an extended reality rendered view of the domain specific language format of the codebase. The device may provide, to an extended reality device, the extended reality rendered view of the domain specific language format of the codebase.

Abstract: There is provision of a processing device including an instruction decoder and an arithmetic unit configured to process an immediate instruction for instructing a calculation of a product of an immediate value and a constant. In response to receiving the immediate instruction, the instruction decoder generates a first shift control information and a second shift control information based on the constant. The arithmetic unit generates a first shifted value by bit-shifting the immediate value received from the instruction decoder based on the first shift control information, and a second shifted value by bit-shifting the immediate value or a complement of the immediate value based on the second shift control information. By performing an addition of the first shifted value and the second shifted value, the arithmetic unit calculates the product.

Abstract: Examples of a carry chain for performing an operation on operands each including elements of a selectable size is provided. Advantageously, the carry chain adapts to elements of different sizes. The carry chain determines a mask based on a selected size of an element. The carry chain selects, based on the mask, whether to carry a partial result of an operation performed on corresponding first portions of a first operand and a second operand into a next operation. The next operation is performed on corresponding second portions of the first operand and the second operand, and, based on the selection, the partial result of the operation. The carry chain stores, in a memory, a result formed from outputs of the operation and the next operation.

Abstract: Systems, methods, and apparatuses relating to multiple source blend operations are described. In one embodiment, a processor is to execute an instruction to: receive a first input operand of a first input vector, a second input operand of a second input vector, and a third input operand of a third input vector, compare each element from the first input vector to each corresponding element of the second input vector to produce a first comparison vector, compare each element from the first input vector to each corresponding element of the third input vector to produce a second comparison vector, compare each element from the second input vector to each corresponding element of the third input vector to produce a third comparison vector, determine a middle value for each element position of the input vectors from the comparison vectors, and output the middle values into same element positions in an output vector.

Abstract: A technique for processing IO (Input/Output) requests includes executing a first set of instructions for processing an IO request using a first thread on a CPU core and providing the first thread with an option, based on how busy the CPU core is, either (i) to execute a second set of instructions for further processing the IO request itself or (ii) to pass the IO request to a second thread on the CPU core, such that the second thread executes the second set of instructions instead of the first thread.

Abstract: A processor includes a global register to store a value of an interrupted block count. A processor core, communicably coupled to the global register, may, upon execution of an instruction to flush blocks of a cache that are associated with a security domain: flush the blocks of the cache sequentially according to a flush loop of the cache; and in response to detection of a system interrupt: store a value of a current cache block count to the global register as the interrupted block count; and stop execution of the instruction to pause the flush of the blocks of the cache. After handling of the interrupt, the instruction may be called again to restart the flush of the cache.

Abstract: Techniques are disclosed relating to speculative writes to special-purpose registers (SPRs). In some embodiments, the disclosed techniques may reduce or avoid system instruction stalls while waiting for SPR writes, which may improve processor performance. In some embodiments, a processor includes a first storage element configured to store a non-speculative value of a special-purpose register and speculative storage circuitry configured to store one or more speculative values of the special-purpose register based on one or more speculatively-performed writes to the special-purpose register. In some embodiments, the processor includes control circuitry configured to: propagate the non-speculative value of the special-purpose register to control other circuitry and provide a youngest speculative value of the special-purpose register in the speculative storage circuitry as a speculative read of the special-purpose register.

Abstract: Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

Abstract: Techniques are disclosed relating to fetching items from a compute command stream that includes compute kernels. In some embodiments, stream fetch circuitry sequentially pre-fetches items from the stream and stores them in a buffer. In some embodiments, fetch parse circuitry iterate through items in the buffer using a fetch parse pointer to detect indirect-data-access items and/or redirect items in the buffer. The fetch parse circuitry may send detected indirect data accesses to indirect-fetch circuitry, which may buffer requests. In some embodiments, execute parse circuitry iterates through items in the buffer using an execute parse pointer (e.g., which may trail the fetch parse pointer) and outputs both item data from the buffer and indirect-fetch results from indirect-fetch circuitry for execution. In various embodiments, the disclosed techniques may reduce fetch latency for compute kernels.

Abstract: Apparatuses and techniques are described for accessing redundant columns of data in a memory device. To facilitate scaling of a memory device and reduce a clock rate used to access latches of the redundant columns in program and read operations, one or more first-in, first out (FIFO) buffers are provided to output data to, and receive data from, the latches. The FIFO buffers act as an interface between a controller and the latches, and exchange data with the controller at a relatively high clock rate, and exchange data with the latches of the redundant columns at a slower clock rate. During a read operation, the FIFO can prefetch read data from one or more columns and store it until it is needed to replace the data of a defective primary column.

Abstract: A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.

Abstract: A system and method for efficiently reducing the latency and power of memory access operations. A processor includes a stack pointer (SP) load-store dependence (LSD) predictor which predicts whether a memory dependence exists on a store instruction. The processor also includes a register file (RF) LSD predictor which predicts whether a memory dependence exists on a store instruction or a load instruction by a subsequent load instruction in program order. Each of the SP-LSD predictor and the RF-LSD predictor predicts and performs register renaming in a pipeline stage earlier than a renaming pipeline stage. The RF-LSD predictor also determines whether any intervening instructions between a producer memory instruction and a consumer memory instruction modify a predicted dependence.

Abstract: A branch predictor is provided with a branch state buffer, branch prediction save circuitry responsive to a branch prediction save event associated with a given execution context to save at least a portion of the active branch prediction state associated with the given execution context to a branch state buffer; and branch prediction restore circuitry responsive to a branch prediction restore event associated with the given execution context to restore active branch prediction state based on previously saved branch prediction state stored in the branch state buffer for the given execution context. This is useful for reducing the performance impact of mitigating against speculative side-channel attacks.

Abstract: Branch prediction methods and systems include, for a branch instruction fetched by a processor, indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein each entry of the branch ID table comprises at least a tag field, and an accuracy counter. For a tag hit at an entry indexed by the PC value, if a value of the corresponding accuracy counter is greater than or equal to zero, a prediction counter from a prediction counter pool is selected based on a function of the PC value and a load-path history, wherein the prediction counters comprise respective confidence values and prediction values. A memory-dependent branch prediction of the branch instruction is assigned as the prediction value of the selected prediction counter if the associated confidence value is greater than zero, while branch prediction from a conventional branch predictor is overridden.

Abstract: Systems, apparatuses and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

Abstract: A load request to restore a plurality of architected registers is obtained. Based on obtaining the load request, one or more architected registers of the plurality of architected registers are restored. The restoring uses a snapshot that maps architected registers to physical registers to replace one or more physical registers currently assigned to the one or more architected registers with one or more physical registers of the snapshot corresponding to the one or more architected registers.

Abstract: An apparatus and method for processing array of structures (AoS) and structure of arrays (SoA) data. For example, one embodiment of a processor comprises: a destination tile register to store data elements in a structure of arrays (SoA) format; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch an array of structures (AoS) gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the AoS gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register, to read data elements from the system memory addresses in an AoS format, and to load the data elements to the destination tile register in an SoA format.

Abstract: An illustrative embodiment disclosed herein is a cluster including a plurality of host devices. The plurality of host devices include a first host device. The cluster further includes a cluster controller that receives indication of a contention on the first host device. The cluster controller selects a plurality of candidate host devices among the plurality of host devices based on a plurality of host CPU usages of the plurality of candidate host devices. The cluster controller computes a plurality of projected CPU usages of the plurality of candidate host devices. The cluster controller selects a target host device among the plurality of candidate host devices based on the plurality of projected CPU usages of the plurality of candidate host devices.

Abstract: Examples described herein include systems and methods for bare metal management of computing devices. Firmware of the computing device can be configured to contact a network location as part of an HTTP boot and download a boot agent. The boot agent can be prioritized to execute before a primary OS boot loader. The boot agent can download an OS configuration including a package that is inserted into the primary OS. The primary OS, as configured, can then boot. The boot agent can also attest to OS health and device compliance on subsequent boots. For example, the boot agent can cause the firmware to track how many boots have occurred since compliance verification. If a threshold number of boots occur without verification, the boot agent can initiate restoration. Alternatively, if a decommission flag is set, the boot agent can cause the computing device to boot into its original configuration.

Abstract: Technologies are disclosed herein for saving data, such as state data, during boot-up of a computer system, such that that data may be retrieved at a later time and restored to its original locations. The data that is stored may be from a shared partition of system memory that is accessible by both firmware services and runtime services, as enabled by an operating system and/or applications running on the computer system. The data may be stored in a partition of the system memory that is only accessible by firmware. In some embodiments, due to the data of the shared partition of the system memory being restored, some functions of the boot-up may not be repeated prior to loading a second operating system on the computer system.

Abstract: Method, device, and storage medium for processing a driver on a terminal device side are provided. A driver processing method includes displaying a driver installation interface. The driver installation interface provides a connection method prompt message prompting a user to make a connection between a terminal device and a peripheral device.

Abstract: A network-connected device, and methods for executing operating programs stored in a RAM-based file storage system, where the network-connected device includes a bootloader configured to be executed during a boot of the network-connected device. When executed, the bootloader causes the network-connected device to connect to an external computing device via a network, and to download an operating program. The network-connected device then stores the operating program in a RAM-based file storage system that is located in a simulated disk drive that resides in the RAM memory, and executes the operating program from within the RAM-based file storage system. In some embodiments, the network-connected device also is configured to store configuration files in the RAM-based file storage system, make changes to the configuration files stored in the RAM-based file storage system, and synchronize those changes with a remote persistent file store hosted by an external computing device.

Abstract: An information processing apparatus for performing hibernation startup is provided. The information processing apparatus includes a selecting unit that selects snapshot creation startup or snapshot startup; a startup unit that initiates startup processes of one or more applications when the snapshot creation startup is selected; the applications, which send notifications after the startup processes have progressed to respective points in time for snapshot creation; a creation instructing unit that sends an instruction to create a snapshot after receiving the notifications from all the applications; a creating unit that creates the snapshot based on the instruction; a memory that stores the snapshot; and a startup instructing unit that reads the snapshot stored in the memory when the snapshot startup is selected, and sends, to the applications, an instruction to resume the startup processes subsequent to the respective points in time, so as to complete the startup processes of the applications.