Abstract: A battery management system includes: a plurality of slave controllers configured to be respectively connected with a plurality of battery modules to generate battery sensing information related to the respective battery modules; and a master controller connected with an uppermost slave controller from among the slave controllers, wherein each of the slave controllers includes a first receiver and a first transmitter configured to communicate with a preceding slave controller or the master controller and a second receiver and a second transmitter configured to communicate with a following slave controller, and each of the slave controllers is configured to connect the first receiver with the first transmitter or the second receiver with the second transmitter depending on types of diagnosis packets inputted through the first receiver.

Abstract: A circuit assembly for monitoring the timing behavior of a microcontroller, including: a microcontroller to drive at least one watchdog voltage generating section for a temporally defined generation of at least one monitoring voltage and to detect and read in the generated monitoring voltage at a predetermined sampling point in time; in which the at least one watchdog voltage generating section is arranged to generate the monitoring voltage that is detectable at a predetermined sampling point in time by sampling by the microcontroller, in which a monitoring voltage that is detected at the sampling point in time and lies within a predetermined voltage tolerance range indicates a fault-free microcontroller state, and a monitoring voltage that is detected at the predetermined point in time and lies outside the predetermined voltage tolerance range indicates a faulty microcontroller state. Also described is a related method.

Abstract: The data storage device includes a first memory having error correction capability, and a controller coupled to the first memory. The controller is configured to calculate an error count of the first memory. The controller is configured to report a message to a host when the controller determines that an alarm condition is satisfied. The alarm condition is related to the error count of the first memory and a threshold count.

Abstract: Technologies are provided for determining an identity of a hardware device that transmitted an error message via a communication bus. A chipset of the communication bus can be configured to transmit an interrupt to an interrupt handler in response to receipt of the error message. The interrupt handler can be configured to determine an identity of the hardware device based on the contents of the error message. The interrupt handler can be configured to transmit a notification to an error remediation service, wherein the notification is associated with the identity of the hardware device. The remediation service can be configured to use the identity of the hardware device to perform one or more error remediation operations. In at least some embodiments, the interrupt handler is configured to store the identifier in a memory and the error remediation service is configured to retrieve the identifier from the memory.

Abstract: In some examples, a computing device can determine a data state from telemetry data received from a plurality of client devices, determine a state change using the data state determined from the telemetry data, determine, using the state change, a potential cause of a fault of a component of a client device of the plurality of client devices, where the potential cause of the fault is determined in response to receiving a support inquiry from the client device, and display a timeline of state changes, where the timeline includes the determined state change of the client device.

Abstract: Some embodiments include reception of a time-series of a respective data value generated by each of a plurality of sensors, calculation of a regression associated with a first sensor of the plurality of sensors based on the received plurality of time-series, the regression being a function of the respective data values of the others of the plurality of data sources, reception of respective data values associated with a time from and generated by each the plurality of respective sensors, determination of a predicted value associated with the time for the first sensor based on the regression associated with the first sensor and on the respective data values associated with the time, comparison of the predicted value with the received value associated with the time and generated by the first sensor, and determination of a value indicating a likelihood of an anomaly based on the comparison.

Abstract: Methods, systems, and computer program products for detecting and correcting integration issues and errors between different computer systems are disclosed. For example, a computer-implemented method may include collecting transaction data for each one of a plurality of respective merchants where the transaction data is associated with service integration between computer systems associated with the respective merchants and one or more service provider computer systems, analyzing the transaction data across a plurality of respective issue detection models, generating for each one of the plurality of merchants action data corresponding to one or more of the respective issue detection models based on the analyzing, and providing each one of the plurality of merchants with the respective generated action data.

Abstract: Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.

Abstract: A memory system includes a Nonvolatile Memory (NVM) and storage circuitry. The NVM includes memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The storage circuitry assigns in a recovery scheme, data pages to predefined parity groups, including assigning to a parity group multiple data pages of two or more different bit-significance values in a common group of the memory cells in a WL. The storage circuitry calculates redundancy data over the data pages of a given parity group in accordance with the recovery scheme and stores the redundancy data in a dedicated group of the memory cells. The storage circuitry reads a data page belonging to the given parity group, and upon detecting a read failure, recovers the data page based on other data pages in the given parity group and on the redundancy data calculated for the given parity group.

Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight.

Abstract: Disclosed are devices, systems and methods for improved decoding of a binary linear code. An example method includes receiving a noisy codeword; computing a syndrome based on the noisy codeword; identifying N error patterns that correspond to the syndrome; selecting M error patterns from the N error patterns, wherein M?N are positive integers, wherein a distance between a codeword corresponding to each of the M error patterns and the noisy codeword is less than a distance between a codeword corresponding to any other error pattern and the noisy codeword, and wherein the distance excludes a Hamming distance; modifying the noisy codeword based on each of the M error patterns one-at-a-time; and decoding the modified noisy codeword one-at-a-time until a successful decoding is achieved.

Abstract: A storage client needs to store to-be-written data into a distributed storage system, and storage nodes corresponding to a first data unit assigned for the to-be-written data by a management server are only some nodes in a storage node group. When receiving a status of the first data unit returned by the management server, the storage client may determine quantities of data blocks and parity blocks needing to be generated during EC coding on the to-be-written data. The storage client stores the generated data blocks and parity blocks into some storage nodes designated by the management server in a partition where the first data unit is located. Accordingly, dynamic adjustment of an EC redundancy ratio is implemented, and the management server may exclude some nodes in the partition from a storage range of the to-be-written data based on a requirement, thereby reducing a data storage IO amount.

Abstract: A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code and a second system error correction code based on write data; and a memory including: a memory error correction code generation circuit configured to generate a first memory error correction code based on the write data transferred from the memory controller, and generate a second memory error correction code based on the second system error correction code transferred from the memory controller, and a memory core configured to store the write data, the first system error correction code, the second system error correction code, the first memory error correction code and the second memory error correction code.

Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, detect an uncorrectable error in the user data, detect a sector balanced when the number of 1's and 0's in the user data is within the difference stored in a range register, apply an XOR RAID recovery to correct the uncorrectable error in the user data; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured to forego an additional read of a sector N with a different value of the read threshold when the sector balanced initiates the XOR RAID recovery.

Abstract: One or more blocks from a pool of storage area blocks of the memory component are allocated to a first set of purposed blocks. First write operations are performed to write first data to first data stripes at user blocks of the memory component. Whether the blocks in the first set of purposed blocks satisfy a condition indicating that the first set of purposed blocks are to be retired is determined. Responsive to the blocks in the first set of purposed blocks satisfying the condition, one or more other blocks from the pool of storage area blocks of the memory component are allocated to a second set of purposed blocks. Second write operations are performed to write second data to second data stripes at the user blocks of the memory component.

Abstract: A disclosed method includes selecting one or more regions having a predetermined size or more in a logical address space of a first memory drive when the first memory drive is partially failed, transferring data of the one or more selected regions to a second memory drive, reading data from another memory drive, which forms a RAID group with the first memory drive, to restore lost data caused by the partial failure, and writing the restored lost data to the first memory drive.

Abstract: A method for verifying program flow during execution of a software program in a computer system is disclosed. Program code of the software program includes multiple program instructions and checkpoint data structures, where a given checkpoint data structure is associated with a given program instruction and is linked to at least one other checkpoint data structure. A fault monitor circuit may receive a particular checkpoint data structure and compare the particular checkpoint data structure to a previously received checkpoint data structure that is associated with another program instruction. Based on results of the comparison, the software fault monitor circuit may signal a program flow error.

Abstract: A versioned records management computing system that uses a restart era in order to promote rapid recovery. A persistent store includes a multi-versioned record collection. The records are also associated with a restart era that corresponds to the era of operation of the computing system after a restart. Upon a recovery, the current restart era changes. An object collection media has an object collection that conforms to an object model such that the object model is used to operate upon the records. The object collection media is operable such that the object collection is durable so as to survive restarts of the system to thereby allow for accelerated recovery.

Abstract: A data processing apparatus is provided that comprises volatile storage circuitry to store data while power is provided. Persistent storage circuitry stores data in the absence of power and transfer circuitry transfers data from the volatile storage circuitry to the persistent storage circuitry. The transfer circuitry is adapted to transfer the data from the volatile storage circuitry to the persistent storage circuitry in response to a primary power supply becoming unavailable to the volatile storage circuitry. The transfer circuitry is adapted to transfer a subset of the data from the volatile storage circuitry to the persistent storage circuitry in response to an explicit request comprising an indication of the subset of the data.

Abstract: Methods, non-transitory computer readable media, and computing devices that determine when a storage element of a data storage device has failed. Address(es) mapped to the failed storage element are identified, when the determining indicates that the storage element has failed. Data corresponding to the address(es) is regenerated according to a data loss protection and recovery scheme (e.g., a RAID scheme). The regenerated data is written to other storage element(s) of the data storage device in order to remap the address(es) to the other storage element(s). This technology allows a data storage device (e.g., an SSD) to be repaired in-place following a failure of storage element(s) (e.g., a die) of the data storage device. Advantageously, entire data storage devices do not have to be failed with this technology as a result of a failure of an individual storage element, thereby reducing data storage device failure rates and associated overhead.

Abstract: In one embodiment, I/O operations may be swapped from an original storage unit to a replacement storage unit in a manner which can reduce or eliminate delays caused by copying of data from the original storage unit to the replacement storage unit. A point-in-time snap copy relationship between the original storage unit and the replacement storage unit of storage locations is established and I/O operations are swapped from the original storage unit to the replacement storage unit. The I/O operations are resumed, accessing the replacement storage unit instead of the original storage unit in the input/output operations issued by the at least one host. Other aspects are described.

Abstract: The Source Volume Backup with Adaptive Finalization Apparatuses, Methods and Systems (“SVBAF”) transforms backup request inputs via SVBAF components into backup response outputs. A set of blocks to be copied from a source volume to a target volume is designated and copied while an operating system is configured to write to the source volume. Blocks of the source volume that were written to by the operating system while the operating system was configured to write to the source volume are identified. Finalization settings are analyzed to determine whether to enter a CoW mode. If the CoW mode should not be entered, the designated set of blocks is changed to include at least one of the identified blocks and a pass is repeated. Otherwise, the operating system is instructed to enter the CoW mode and bring the target volume into a state consistent with a state of the source volume.

Abstract: Techniques for scheduling replication events may be based upon establishing a plurality of policy groups. Each policy group has a replication schedule that defines when to initiate replication events and a membership selection pattern used to determine which virtual machines belong to which policy group. The policy groups may contain a first policy group and a second policy group, where each policy group has a unique replication schedule and a unique selection pattern. The system may assign a first set of virtual machines to the first policy group based upon the first selection pattern. A second set of virtual machines may be assigned to a second policy group based upon the second selection pattern. Each of the virtual machines in the first policy group may be assigned a first replication schedule and each of the virtual machines in the second policy group may be assigned a second replication schedule.

Abstract: Contents of a plurality of backups that share a common characteristic are profiled. A portion of the plurality of backups is selected as a base backup reference data to be distributed. A first copy of the base backup reference data is stored at a storage of a backup server. A second copy of the base backup reference data is provided for storage at a storage of a client that shares the common characteristic. The client is located remotely from the backup server.

Abstract: Embodiments of the present disclosure relate to methods, systems, and computer program products for managing a distributed system. In one embodiment, a computer-implemented method is disclosed. In the method, packets that are to be transmitted among a group of nodes in a distributed system may be collected into a queue of packets, here a packet in the queue is associated with a source node and a destination node in the group of nodes. A snapshot in the group of snapshots may be obtained from a node in the group of nodes, therefore a group of snapshots may be obtained from the group of nodes. A snapshot of the distributed system may be generated based on the queue of packets and the group of snapshots. In other embodiments, a computer-implemented system and a computer program product for managing a distributed system are disclosed.

Abstract: A system for providing multiple restore points on a virtual machine includes maintaining a record of a plurality of restore points of virtual machines. Upon receiving a request from a user to access a plurality of restore points of a virtual machine, the system can mount a plurality of backup disks onto a target virtual machine and then notify the user.

Abstract: Systems and methods for live migration of a virtual machine are provided. The methods include: copying, by a destination physical machine according to a recorded dirty page table, dirty memory pages corresponding to dirty memory page identifiers in the dirty page table to a source physical machine when live migration of a virtual machine fails in a delayed-copy mode, and updating and storing, by the source physical machine, the copied dirty memory pages. When live migration of a virtual machine fails, dirty memory pages corresponding to dirty memory page identifiers in a dirty page table are copied to a source physical machine to be updated and stored, so that the source physical machine has complete and the latest memory pages, and the virtual machine can roll back to and run independently on the source physical machine.

Abstract: Restoring of a database table in the database system (e.g., an in-memory insert-only database system, etc.) is initiated. Thereafter, a transaction log volume storing data log records and multi-version concurrency control (MVCC) log records corresponding to the database table is accessed. Based on such access, data log records corresponding to the database table are replayed while insert and update MVCC log records corresponding to the database table are skipped. Subsequently, restoring of the database table in the database system is finalized. Related apparatus, systems, techniques and articles are also described.

Abstract: A test controller interfacing between a master computing device and slave computing devices includes a processor configured to launch a master application on the master computing device and a slave application to be tested on each respective slave computing device, with each slave application being the same as the master application. The processor is also configured to receive from the master computing device an input test command along with a test result based on execution of the input test command by the master application, and transmit the received input test command to each slave computing device. In addition, the processor is configured to receive a respective test result from each slave computing device based on execution of the received input test command, and compare each respective test result from the slave computing devices to the test result from the master computing device.

Abstract: Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.

Abstract: The system and method may receive transaction data for a financial account associated with a user during a first time period and a second time period. A first environmental impact score for the transaction data associated with the user in the first time period may be determined and a second environmental impact score for the transaction data associated with the user in the second time period may also be determined. The first environmental impact score and the second environmental impact score may be compared. The system and method may determine whether there has been a change from the first environmental impact score to the second environmental impact score. In response to a determination that the second environmental impact score is less than the first environmental impact score; a bonus score may be determined for the user.

Abstract: First audit information corresponding to a first set of log entries associated with a transformation performed on first data is obtained, where the first audit information includes a first commutative result produced by applying a commutative function to object identifiers associated with the first set of log entries. Second audit information corresponding to a second set of log entries associated with the transformation performed on second data is obtained, with the second data being a different representation of the first data and where the second audit information includes a second commutative result produced by applying the commutative function to object identifiers associated with the second set of log entries. The first commutative result is compared with the second commutative result to validate whether the second data matches the first data. One or more actions are performed depending on whether the second data is the successful transformation of the first data.

Abstract: Systems, methods, and devices for automatically retrying a query. A method includes receiving a query directed to database data and assigning execution of the query to one or more execution nodes of a database platform. The method includes determining that execution of the query was unsuccessful. The method includes assigning a first retry execution of the query on the first version of the database platform and assigning a second retry execution of the query on a second version of the database platform.

Abstract: An industrial control apparatus that causes a common processing unit to execute a first execution task for executing processing that does not depend on the number of pieces of data and a second execution task for executing processing that depends on the number of pieces of data, and an assistance apparatus are included. The industrial control apparatus calculates a control load amount of a processing unit incurred by executing the first execution task, and extracts the second execution task from the first and second execution tasks. The assistance apparatus calculates a processing load amount of the processing unit according to the type of the extracted second execution task for the number of pieces of analysis data, and using this processing load amount and the control load amount, calculates a margin of processing that indicates a degree of remaining processing capability of the processing unit.

Abstract: Aspects of the subject disclosure may include, for example, a method that includes detecting events relating to user equipment on a communication network, collecting first event data including event times and locations, and collecting second event data regarding second event dimensions determined at least in part by the event type. The method also includes generating, for each of the event types, an event data structure associated with the user, based on the first event data and second event data. The event data structures are concatenated to generate an event history flow associated with the user; the event history flow is analyzed to identify causal events for a detected event. The method also includes generating a model for performance of the user equipment based on the causal events to predict a future event, and identifying potential adjustments to the communication network to prevent that event. Other embodiments are disclosed.

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state.

Abstract: Methods and systems are described for automatically setting multitasking configurations that are used to check, by a code-checking system, implementation code that is to be deployed on a dynamic system. Attributes of implemented tasks and interrupt service routines that can run concurrently on the dynamic system are determined from one or more specification data structures of a specified model and associated with independent, implemented computational threads prepared from the specified model. Configured with information relevant to the concurrent threads, the code-checking system can more accurately determine the presence or absence of defects in the implementation code. The specified model, resulting implemented code, and dynamic system can be complex and comply with a standardized software architecture, such as Automotive Open System Architecture (AUTOSAR).

Abstract: A system for and method of analyzing user tools to detect and remediate those tools posing a high risk to an organization. The system and method involve calculating user tool complexity to predict potential tool failures and displaying the potential failures to a user for further analysis. Remediation tools are provided to permit the user to correct or minimize the potential failures. The user can identify high risk tools and mark potential risks in those tools as mitigated, pending mitigation, or no mitigation action required.

Abstract: The techniques described herein may provide deadlock detection and prevention with improved performance and reduced overhead over existing systems. For example, in an embodiment, a method for improving performance of software code by preventing deadlocks may comprise executing software code in a computer system comprising a processor, memory accessible by the processor, and program instructions and data for the software code stored in the memory, the program instructions executable by the processor to execute the software code, logging information relating to occurrence of deadlock conditions among threads in the executing software code, detecting occurrence of deadlock conditions in the software code based on the logged information, and modifying the software code or data used by the software code so as to prevent occurrence of at least one detected deadlock condition.

Abstract: Performance anomalies in production applications can be analyzed to determine the dynamic behavior over time of hosting processes on the same or different computers. Problematic call sites (call sites that are performance bottlenecks or that are causing hangs) can be identified. Instead of relying on static code analysis and development phase load testing to identify a performance bottleneck or application hang, a lightweight sampling strategy collects predicates representing key performance data in production scenarios. Performance predicates provide information about the subject (e.g., what the performance issue is, what caused the performance issue, etc.). The data can be fed into a model based on a decision tree to identify critical threads running the problematic call sites. The results along with the key performance data can be used to build a call graph prefix binary tree for analyzing call stack patterns. Data collection, analysis and visualizations of result can be performed.

Abstract: Methods, systems and computer program products for intercepting and recording calls of a module in real-time is provided. Each listed target module is loaded into system memory. A link is established between each target module and the recording framework, which begins execution of an application that includes the plurality of target modules. In response to one of the plurality of target modules being called by the application, control is passed to the recording framework, which includes passing to the recording framework original registers from the application and a register containing an entry point of the recording framework. Recording framework records arguments passed to the target module. Tags identifying the execution environment, transaction name, transaction id, calling program name, and whether the call is for input or output are recorded. When the target module completes, control passes back to the recording framework, which records the output parameters from the target module.

Abstract: An equivalence verification unit (130) judges through equivalence verification, for each of corresponding combinations which are each a combination of a function included in pre-change source code and a function included in post-change source code, whether the functions included in the corresponding combination are equivalent to each other. A partial verification judgment unit (150) judges, for each of inequivalent ones of the corresponding combinations, whether the corresponding combination is a partial verification combination including a function where an inequivalent path, in which an inequivalent function is called, and a non-inequivalent path, in which a non-inequivalent function is called, are both included. A partial verification unit (160) judges, for each of the partial verification combinations, whether the functions included in the partial verification combination are partially equivalent to each other by excluding the inequivalent path and performing the equivalence verification.

Abstract: Techniques for monitoring operating statuses of an application and its dependencies are provided. A monitoring application may collect and report the operating status of the monitored application and each dependency. Through use of existing monitoring interfaces, the monitoring application can collect operating status without requiring modification of the underlying monitored application or dependencies. The monitoring application may determine a problem service that is a root cause of an unhealthy state of the monitored application. Dependency analyzer and discovery crawler techniques may automatically configure and update the monitoring application. Machine learning techniques may be used to determine patterns of performance based on system state information associated with performance events and provide health reports relative to a baseline status of the monitored application. Also provided are techniques for testing a response of the monitored application through modifications to API calls.

Abstract: In one embodiment, a method for editing and testing computer programming code is provided. The method includes receiving a first file comprising computer programming code, and a first code overlay comprising one or more modifications to be applied to the computer programming code of the first file. The method further includes determining a first location within the computer programming code of the first file, at which to apply the first code overlay. The method further includes generating a second file comprising uncompiled composite computer programming code, the uncompiled composite computer programming code comprising the computer programming code of the first file modified by the one or more modifications applied at the first location. The method further includes testing the uncompiled composite computer programming code of the second file.

Abstract: A method includes identifying a set of tests for a source code, analyzing the set of tests to identify overlapping blocks of the source code that are to be tested by each of the set of tests, merging a subset of the tests that include the overlapping blocks of the source code to create a merged test, and causing the merged test to be executed to test the source code. In an implementation, code coverage results are used when analyzing the set of tests to identify overlapping blocks of the source code.

Abstract: A test case management system includes an input and output (I/O) interface for receiving a first test case, a database (DB) for storing a second test case, and a controller for comparing the first test case with the second test case based on a similarity score between a string of the first test case and a string of the second test case.

Abstract: Regression testing of software applications is described. Breakpoints are inserted in a programming code of an object to perform testing of all software applications that use the object. A processor in a computing device can receive data representing a programming code of a functionality of a software application rectifying a problem associated with the functionality of the software application. The processor can determine another software application executing the functionality. The processor can insert a breakpoint in the programming code of the functionality of the software application and the another software application. The breakpoint can be inserted at a location in the programming code of the software application where the problem was rectified. The processor can execute the programming code of the functionality including the inserted breakpoint. The processor can determine, based on the executing, whether the problem has been rectified in the software application and the another software application.

Abstract: The present invention relates to a method for controlling a test environment on a mobile device. The method includes the steps of providing a test to a user within a testing phase on the device; detecting an interruption via the device during the testing phase; and generating an action in response to the detected interruption. A system for controlling a test environment is also disclosed.

Abstract: Methods and systems for a deep learning based problem advisor are disclosed. A method includes: obtaining, by a computing device, a log file including events generated during execution of a software application; determining, by the computing device, at least one possible cause for a problem in the software application using the obtained log file and a knowledge base including calling paths for each of a plurality of methods in source code of the software application; for each of the at least one possible cause for the problem, the computing device simulating user actions in the software application; and determining, by the computing device, a root cause based on the simulating user actions in the software application.

Abstract: Embodiments of the present systems and methods may provide techniques that may provide unit-level test of an SUT, but which translates the unit-level test into a valid test of the SUT itself. For example, in an embodiment, a computer-implemented method for testing a system, the method may comprise analyzing the system to determine sub-components of the system and inputs to the sub-components, performing dynamic testing of the system and collecting pairs of inputs to the system and inputs to the sub-components, training a machine learning model to translate from inputs to the sub-components to inputs to the system input using the collected pairs of inputs to the system and inputs to the sub-components and performing sub-component level testing and translating the sub-component level testing to system level testing.